1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_TRGMUX_1.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_TRGMUX_1
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_TRGMUX_1_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_TRGMUX_1_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- TRGMUX_1 Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup TRGMUX_1_Peripheral_Access_Layer TRGMUX_1 Peripheral Access Layer
68  * @{
69  */
70 
71 /** TRGMUX_1 - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t REG_0;                             /**< TRGMUX REG_0, offset: 0x0 */
74   __IO uint32_t REG_1;                             /**< TRGMUX REG_1, offset: 0x4 */
75   __IO uint32_t REG_2;                             /**< TRGMUX REG_2, offset: 0x8 */
76   __IO uint32_t REG_3;                             /**< TRGMUX REG_3, offset: 0xC */
77   __IO uint32_t REG_4;                             /**< TRGMUX REG_4, offset: 0x10 */
78 } TRGMUX_1_Type, *TRGMUX_1_MemMapPtr;
79 
80 /** Number of instances of the TRGMUX_1 module. */
81 #define TRGMUX_1_INSTANCE_COUNT                  (1u)
82 
83 /* TRGMUX_1 - Peripheral instance base addresses */
84 /** Peripheral TRGMUX_1 base address */
85 #define IP_TRGMUX_1_BASE                         (0x40090000u)
86 /** Peripheral TRGMUX_1 base pointer */
87 #define IP_TRGMUX_1                              ((TRGMUX_1_Type *)IP_TRGMUX_1_BASE)
88 /** Array initializer of TRGMUX_1 peripheral base addresses */
89 #define IP_TRGMUX_1_BASE_ADDRS                   { IP_TRGMUX_1_BASE }
90 /** Array initializer of TRGMUX_1 peripheral base pointers */
91 #define IP_TRGMUX_1_BASE_PTRS                    { IP_TRGMUX_1 }
92 
93 /* ----------------------------------------------------------------------------
94    -- TRGMUX_1 Register Masks
95    ---------------------------------------------------------------------------- */
96 
97 /*!
98  * @addtogroup TRGMUX_1_Register_Masks TRGMUX_1 Register Masks
99  * @{
100  */
101 
102 /*! @name REG_0 - TRGMUX REG_0 */
103 /*! @{ */
104 
105 #define TRGMUX_1_REG_0_SEL0_MASK                 (0x3FU)
106 #define TRGMUX_1_REG_0_SEL0_SHIFT                (0U)
107 #define TRGMUX_1_REG_0_SEL0_WIDTH                (6U)
108 #define TRGMUX_1_REG_0_SEL0(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_0_SEL0_SHIFT)) & TRGMUX_1_REG_0_SEL0_MASK)
109 
110 #define TRGMUX_1_REG_0_SEL1_MASK                 (0x3F00U)
111 #define TRGMUX_1_REG_0_SEL1_SHIFT                (8U)
112 #define TRGMUX_1_REG_0_SEL1_WIDTH                (6U)
113 #define TRGMUX_1_REG_0_SEL1(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_0_SEL1_SHIFT)) & TRGMUX_1_REG_0_SEL1_MASK)
114 
115 #define TRGMUX_1_REG_0_SEL2_MASK                 (0x3F0000U)
116 #define TRGMUX_1_REG_0_SEL2_SHIFT                (16U)
117 #define TRGMUX_1_REG_0_SEL2_WIDTH                (6U)
118 #define TRGMUX_1_REG_0_SEL2(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_0_SEL2_SHIFT)) & TRGMUX_1_REG_0_SEL2_MASK)
119 
120 #define TRGMUX_1_REG_0_SEL3_MASK                 (0x3F000000U)
121 #define TRGMUX_1_REG_0_SEL3_SHIFT                (24U)
122 #define TRGMUX_1_REG_0_SEL3_WIDTH                (6U)
123 #define TRGMUX_1_REG_0_SEL3(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_0_SEL3_SHIFT)) & TRGMUX_1_REG_0_SEL3_MASK)
124 
125 #define TRGMUX_1_REG_0_LK_MASK                   (0x80000000U)
126 #define TRGMUX_1_REG_0_LK_SHIFT                  (31U)
127 #define TRGMUX_1_REG_0_LK_WIDTH                  (1U)
128 #define TRGMUX_1_REG_0_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_0_LK_SHIFT)) & TRGMUX_1_REG_0_LK_MASK)
129 /*! @} */
130 
131 /*! @name REG_1 - TRGMUX REG_1 */
132 /*! @{ */
133 
134 #define TRGMUX_1_REG_1_SEL0_MASK                 (0x3FU)
135 #define TRGMUX_1_REG_1_SEL0_SHIFT                (0U)
136 #define TRGMUX_1_REG_1_SEL0_WIDTH                (6U)
137 #define TRGMUX_1_REG_1_SEL0(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_1_SEL0_SHIFT)) & TRGMUX_1_REG_1_SEL0_MASK)
138 
139 #define TRGMUX_1_REG_1_SEL1_MASK                 (0x3F00U)
140 #define TRGMUX_1_REG_1_SEL1_SHIFT                (8U)
141 #define TRGMUX_1_REG_1_SEL1_WIDTH                (6U)
142 #define TRGMUX_1_REG_1_SEL1(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_1_SEL1_SHIFT)) & TRGMUX_1_REG_1_SEL1_MASK)
143 
144 #define TRGMUX_1_REG_1_SEL2_MASK                 (0x3F0000U)
145 #define TRGMUX_1_REG_1_SEL2_SHIFT                (16U)
146 #define TRGMUX_1_REG_1_SEL2_WIDTH                (6U)
147 #define TRGMUX_1_REG_1_SEL2(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_1_SEL2_SHIFT)) & TRGMUX_1_REG_1_SEL2_MASK)
148 
149 #define TRGMUX_1_REG_1_SEL3_MASK                 (0x3F000000U)
150 #define TRGMUX_1_REG_1_SEL3_SHIFT                (24U)
151 #define TRGMUX_1_REG_1_SEL3_WIDTH                (6U)
152 #define TRGMUX_1_REG_1_SEL3(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_1_SEL3_SHIFT)) & TRGMUX_1_REG_1_SEL3_MASK)
153 
154 #define TRGMUX_1_REG_1_LK_MASK                   (0x80000000U)
155 #define TRGMUX_1_REG_1_LK_SHIFT                  (31U)
156 #define TRGMUX_1_REG_1_LK_WIDTH                  (1U)
157 #define TRGMUX_1_REG_1_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_1_LK_SHIFT)) & TRGMUX_1_REG_1_LK_MASK)
158 /*! @} */
159 
160 /*! @name REG_2 - TRGMUX REG_2 */
161 /*! @{ */
162 
163 #define TRGMUX_1_REG_2_SEL0_MASK                 (0x3FU)
164 #define TRGMUX_1_REG_2_SEL0_SHIFT                (0U)
165 #define TRGMUX_1_REG_2_SEL0_WIDTH                (6U)
166 #define TRGMUX_1_REG_2_SEL0(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_2_SEL0_SHIFT)) & TRGMUX_1_REG_2_SEL0_MASK)
167 
168 #define TRGMUX_1_REG_2_SEL1_MASK                 (0x3F00U)
169 #define TRGMUX_1_REG_2_SEL1_SHIFT                (8U)
170 #define TRGMUX_1_REG_2_SEL1_WIDTH                (6U)
171 #define TRGMUX_1_REG_2_SEL1(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_2_SEL1_SHIFT)) & TRGMUX_1_REG_2_SEL1_MASK)
172 
173 #define TRGMUX_1_REG_2_SEL2_MASK                 (0x3F0000U)
174 #define TRGMUX_1_REG_2_SEL2_SHIFT                (16U)
175 #define TRGMUX_1_REG_2_SEL2_WIDTH                (6U)
176 #define TRGMUX_1_REG_2_SEL2(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_2_SEL2_SHIFT)) & TRGMUX_1_REG_2_SEL2_MASK)
177 
178 #define TRGMUX_1_REG_2_SEL3_MASK                 (0x3F000000U)
179 #define TRGMUX_1_REG_2_SEL3_SHIFT                (24U)
180 #define TRGMUX_1_REG_2_SEL3_WIDTH                (6U)
181 #define TRGMUX_1_REG_2_SEL3(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_2_SEL3_SHIFT)) & TRGMUX_1_REG_2_SEL3_MASK)
182 
183 #define TRGMUX_1_REG_2_LK_MASK                   (0x80000000U)
184 #define TRGMUX_1_REG_2_LK_SHIFT                  (31U)
185 #define TRGMUX_1_REG_2_LK_WIDTH                  (1U)
186 #define TRGMUX_1_REG_2_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_2_LK_SHIFT)) & TRGMUX_1_REG_2_LK_MASK)
187 /*! @} */
188 
189 /*! @name REG_3 - TRGMUX REG_3 */
190 /*! @{ */
191 
192 #define TRGMUX_1_REG_3_SEL0_MASK                 (0x3FU)
193 #define TRGMUX_1_REG_3_SEL0_SHIFT                (0U)
194 #define TRGMUX_1_REG_3_SEL0_WIDTH                (6U)
195 #define TRGMUX_1_REG_3_SEL0(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_3_SEL0_SHIFT)) & TRGMUX_1_REG_3_SEL0_MASK)
196 
197 #define TRGMUX_1_REG_3_SEL1_MASK                 (0x3F00U)
198 #define TRGMUX_1_REG_3_SEL1_SHIFT                (8U)
199 #define TRGMUX_1_REG_3_SEL1_WIDTH                (6U)
200 #define TRGMUX_1_REG_3_SEL1(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_3_SEL1_SHIFT)) & TRGMUX_1_REG_3_SEL1_MASK)
201 
202 #define TRGMUX_1_REG_3_SEL2_MASK                 (0x3F0000U)
203 #define TRGMUX_1_REG_3_SEL2_SHIFT                (16U)
204 #define TRGMUX_1_REG_3_SEL2_WIDTH                (6U)
205 #define TRGMUX_1_REG_3_SEL2(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_3_SEL2_SHIFT)) & TRGMUX_1_REG_3_SEL2_MASK)
206 
207 #define TRGMUX_1_REG_3_SEL3_MASK                 (0x3F000000U)
208 #define TRGMUX_1_REG_3_SEL3_SHIFT                (24U)
209 #define TRGMUX_1_REG_3_SEL3_WIDTH                (6U)
210 #define TRGMUX_1_REG_3_SEL3(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_3_SEL3_SHIFT)) & TRGMUX_1_REG_3_SEL3_MASK)
211 
212 #define TRGMUX_1_REG_3_LK_MASK                   (0x80000000U)
213 #define TRGMUX_1_REG_3_LK_SHIFT                  (31U)
214 #define TRGMUX_1_REG_3_LK_WIDTH                  (1U)
215 #define TRGMUX_1_REG_3_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_3_LK_SHIFT)) & TRGMUX_1_REG_3_LK_MASK)
216 /*! @} */
217 
218 /*! @name REG_4 - TRGMUX REG_4 */
219 /*! @{ */
220 
221 #define TRGMUX_1_REG_4_SEL0_MASK                 (0x3FU)
222 #define TRGMUX_1_REG_4_SEL0_SHIFT                (0U)
223 #define TRGMUX_1_REG_4_SEL0_WIDTH                (6U)
224 #define TRGMUX_1_REG_4_SEL0(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_4_SEL0_SHIFT)) & TRGMUX_1_REG_4_SEL0_MASK)
225 
226 #define TRGMUX_1_REG_4_SEL1_MASK                 (0x3F00U)
227 #define TRGMUX_1_REG_4_SEL1_SHIFT                (8U)
228 #define TRGMUX_1_REG_4_SEL1_WIDTH                (6U)
229 #define TRGMUX_1_REG_4_SEL1(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_4_SEL1_SHIFT)) & TRGMUX_1_REG_4_SEL1_MASK)
230 
231 #define TRGMUX_1_REG_4_LK_MASK                   (0x80000000U)
232 #define TRGMUX_1_REG_4_LK_SHIFT                  (31U)
233 #define TRGMUX_1_REG_4_LK_WIDTH                  (1U)
234 #define TRGMUX_1_REG_4_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRGMUX_1_REG_4_LK_SHIFT)) & TRGMUX_1_REG_4_LK_MASK)
235 /*! @} */
236 
237 /*!
238  * @}
239  */ /* end of group TRGMUX_1_Register_Masks */
240 
241 /*!
242  * @}
243  */ /* end of group TRGMUX_1_Peripheral_Access_Layer */
244 
245 #endif  /* #if !defined(S32Z2_TRGMUX_1_H_) */
246