1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SINC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SINC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SINC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SINC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SINC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SINC_Peripheral_Access_Layer SINC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SINC - Size of Registers Arrays */ 72 #define SINC_CHANNEL_COUNT 4u 73 74 /** SINC - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t VERID; /**< Version ID, offset: 0x0 */ 77 __I uint32_t PARAMETER; /**< Parameters, offset: 0x4 */ 78 __IO uint32_t MCR; /**< Main Control, offset: 0x8 */ 79 __IO uint32_t NIE; /**< Normal Interrupt Enable, offset: 0xC */ 80 __IO uint32_t EIE; /**< Error Interrupt Enable, offset: 0x10 */ 81 __IO uint32_t FIFOIE; /**< FIFO And CAD Error Interrupt Enable, offset: 0x14 */ 82 __IO uint32_t NIS; /**< Normal Interrupt Status, offset: 0x18 */ 83 __IO uint32_t EIS; /**< Error Interrupt Status, offset: 0x1C */ 84 __IO uint32_t FIFOIS; /**< FIFO And CAD Error Interrupt Status, offset: 0x20 */ 85 __I uint32_t SR; /**< Status, offset: 0x24 */ 86 uint8_t RESERVED_0[16]; 87 struct SINC_CHANNEL { /* offset: 0x38, array step: 0x30 */ 88 __IO uint32_t CCR; /**< Channel 0 Control..Channel 3 Control, array offset: 0x38, array step: 0x30 */ 89 __IO uint32_t CDR; /**< Channel 0 Data Rate..Channel 3 Data Rate, array offset: 0x3C, array step: 0x30 */ 90 __IO uint32_t CCFR; /**< Channel 0 Configuration..Channel 3 Configuration, array offset: 0x40, array step: 0x30 */ 91 __IO uint32_t CPROT; /**< Channel 0 Protection..Channel 3 Protection, array offset: 0x44, array step: 0x30 */ 92 __IO uint32_t CBIAS; /**< Channel 0 Bias..Channel 3 Bias, array offset: 0x48, array step: 0x30 */ 93 __IO uint32_t CLOLMT; /**< Channel 0 Low Limit..Channel 3 Low Limit, array offset: 0x4C, array step: 0x30 */ 94 __IO uint32_t CHILMT; /**< Channel 0 High Limit..Channel 3 High Limit, array offset: 0x50, array step: 0x30 */ 95 __I uint32_t CRDATA; /**< Channel 0 Result Data..Channel 3 Result Data, array offset: 0x54, array step: 0x30 */ 96 __IO uint32_t CMPDATA; /**< Channel 0 Multipurpose Data..Channel 3 Multipurpose Data, array offset: 0x58, array step: 0x30 */ 97 __IO uint32_t CACFR; /**< Channel 0 Advanced Configuration..Channel 3 Advanced Configuration, array offset: 0x5C, array step: 0x30 */ 98 __IO uint32_t CSR; /**< Channel 0 Status..Channel 3 Status, array offset: 0x60, array step: 0x30 */ 99 __I uint32_t CDBGR; /**< Channel 0 Debug..Channel 3 Debug, array offset: 0x64, array step: 0x30 */ 100 } CHANNEL[SINC_CHANNEL_COUNT]; 101 } SINC_Type, *SINC_MemMapPtr; 102 103 /** Number of instances of the SINC module. */ 104 #define SINC_INSTANCE_COUNT (1u) 105 106 /* SINC - Peripheral instance base addresses */ 107 /** Peripheral SINC base address */ 108 #define IP_SINC_BASE (0x403A0000u) 109 /** Peripheral SINC base pointer */ 110 #define IP_SINC ((SINC_Type *)IP_SINC_BASE) 111 /** Array initializer of SINC peripheral base addresses */ 112 #define IP_SINC_BASE_ADDRS { IP_SINC_BASE } 113 /** Array initializer of SINC peripheral base pointers */ 114 #define IP_SINC_BASE_PTRS { IP_SINC } 115 116 /* ---------------------------------------------------------------------------- 117 -- SINC Register Masks 118 ---------------------------------------------------------------------------- */ 119 120 /*! 121 * @addtogroup SINC_Register_Masks SINC Register Masks 122 * @{ 123 */ 124 125 /*! @name VERID - Version ID */ 126 /*! @{ */ 127 128 #define SINC_VERID_FEATURE_MASK (0xFFFFU) 129 #define SINC_VERID_FEATURE_SHIFT (0U) 130 #define SINC_VERID_FEATURE_WIDTH (16U) 131 #define SINC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SINC_VERID_FEATURE_SHIFT)) & SINC_VERID_FEATURE_MASK) 132 133 #define SINC_VERID_MINOR_MASK (0xFF0000U) 134 #define SINC_VERID_MINOR_SHIFT (16U) 135 #define SINC_VERID_MINOR_WIDTH (8U) 136 #define SINC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SINC_VERID_MINOR_SHIFT)) & SINC_VERID_MINOR_MASK) 137 138 #define SINC_VERID_MAJOR_MASK (0xFF000000U) 139 #define SINC_VERID_MAJOR_SHIFT (24U) 140 #define SINC_VERID_MAJOR_WIDTH (8U) 141 #define SINC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SINC_VERID_MAJOR_SHIFT)) & SINC_VERID_MAJOR_MASK) 142 /*! @} */ 143 144 /*! @name PARAMETER - Parameters */ 145 /*! @{ */ 146 147 #define SINC_PARAMETER_FIFO_DEPTH_MASK (0x1FU) 148 #define SINC_PARAMETER_FIFO_DEPTH_SHIFT (0U) 149 #define SINC_PARAMETER_FIFO_DEPTH_WIDTH (5U) 150 #define SINC_PARAMETER_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << SINC_PARAMETER_FIFO_DEPTH_SHIFT)) & SINC_PARAMETER_FIFO_DEPTH_MASK) 151 152 #define SINC_PARAMETER_FLT_NUM_MASK (0xF00U) 153 #define SINC_PARAMETER_FLT_NUM_SHIFT (8U) 154 #define SINC_PARAMETER_FLT_NUM_WIDTH (4U) 155 #define SINC_PARAMETER_FLT_NUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_PARAMETER_FLT_NUM_SHIFT)) & SINC_PARAMETER_FLT_NUM_MASK) 156 157 #define SINC_PARAMETER_PF_ORD_SEL_MASK (0x180000U) 158 #define SINC_PARAMETER_PF_ORD_SEL_SHIFT (19U) 159 #define SINC_PARAMETER_PF_ORD_SEL_WIDTH (2U) 160 #define SINC_PARAMETER_PF_ORD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_PARAMETER_PF_ORD_SEL_SHIFT)) & SINC_PARAMETER_PF_ORD_SEL_MASK) 161 /*! @} */ 162 163 /*! @name MCR - Main Control */ 164 /*! @{ */ 165 166 #define SINC_MCR_STRIG0_MASK (0x1U) 167 #define SINC_MCR_STRIG0_SHIFT (0U) 168 #define SINC_MCR_STRIG0_WIDTH (1U) 169 #define SINC_MCR_STRIG0(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG0_SHIFT)) & SINC_MCR_STRIG0_MASK) 170 171 #define SINC_MCR_STRIG1_MASK (0x2U) 172 #define SINC_MCR_STRIG1_SHIFT (1U) 173 #define SINC_MCR_STRIG1_WIDTH (1U) 174 #define SINC_MCR_STRIG1(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG1_SHIFT)) & SINC_MCR_STRIG1_MASK) 175 176 #define SINC_MCR_STRIG2_MASK (0x4U) 177 #define SINC_MCR_STRIG2_SHIFT (2U) 178 #define SINC_MCR_STRIG2_WIDTH (1U) 179 #define SINC_MCR_STRIG2(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG2_SHIFT)) & SINC_MCR_STRIG2_MASK) 180 181 #define SINC_MCR_STRIG3_MASK (0x8U) 182 #define SINC_MCR_STRIG3_SHIFT (3U) 183 #define SINC_MCR_STRIG3_WIDTH (1U) 184 #define SINC_MCR_STRIG3(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG3_SHIFT)) & SINC_MCR_STRIG3_MASK) 185 186 #define SINC_MCR_DOZEN_MASK (0x400U) 187 #define SINC_MCR_DOZEN_SHIFT (10U) 188 #define SINC_MCR_DOZEN_WIDTH (1U) 189 #define SINC_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_DOZEN_SHIFT)) & SINC_MCR_DOZEN_MASK) 190 191 #define SINC_MCR_RST_MASK (0x2000U) 192 #define SINC_MCR_RST_SHIFT (13U) 193 #define SINC_MCR_RST_WIDTH (1U) 194 #define SINC_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_RST_SHIFT)) & SINC_MCR_RST_MASK) 195 196 #define SINC_MCR_MEN_MASK (0x8000U) 197 #define SINC_MCR_MEN_SHIFT (15U) 198 #define SINC_MCR_MEN_WIDTH (1U) 199 #define SINC_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MEN_SHIFT)) & SINC_MCR_MEN_MASK) 200 201 #define SINC_MCR_MCLKDIV_MASK (0xFF0000U) 202 #define SINC_MCR_MCLKDIV_SHIFT (16U) 203 #define SINC_MCR_MCLKDIV_WIDTH (8U) 204 #define SINC_MCR_MCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLKDIV_SHIFT)) & SINC_MCR_MCLKDIV_MASK) 205 206 #define SINC_MCR_PRESCALE_MASK (0x6000000U) 207 #define SINC_MCR_PRESCALE_SHIFT (25U) 208 #define SINC_MCR_PRESCALE_WIDTH (2U) 209 #define SINC_MCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_PRESCALE_SHIFT)) & SINC_MCR_PRESCALE_MASK) 210 211 #define SINC_MCR_MCLK0DIS_MASK (0x8000000U) 212 #define SINC_MCR_MCLK0DIS_SHIFT (27U) 213 #define SINC_MCR_MCLK0DIS_WIDTH (1U) 214 #define SINC_MCR_MCLK0DIS(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLK0DIS_SHIFT)) & SINC_MCR_MCLK0DIS_MASK) 215 216 #define SINC_MCR_MCLK1DIS_MASK (0x10000000U) 217 #define SINC_MCR_MCLK1DIS_SHIFT (28U) 218 #define SINC_MCR_MCLK1DIS_WIDTH (1U) 219 #define SINC_MCR_MCLK1DIS(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLK1DIS_SHIFT)) & SINC_MCR_MCLK1DIS_MASK) 220 221 #define SINC_MCR_MCLK2DIS_MASK (0x20000000U) 222 #define SINC_MCR_MCLK2DIS_SHIFT (29U) 223 #define SINC_MCR_MCLK2DIS_WIDTH (1U) 224 #define SINC_MCR_MCLK2DIS(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLK2DIS_SHIFT)) & SINC_MCR_MCLK2DIS_MASK) 225 /*! @} */ 226 227 /*! @name NIE - Normal Interrupt Enable */ 228 /*! @{ */ 229 230 #define SINC_NIE_COCIE0_MASK (0x1U) 231 #define SINC_NIE_COCIE0_SHIFT (0U) 232 #define SINC_NIE_COCIE0_WIDTH (1U) 233 #define SINC_NIE_COCIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE0_SHIFT)) & SINC_NIE_COCIE0_MASK) 234 235 #define SINC_NIE_COCIE1_MASK (0x2U) 236 #define SINC_NIE_COCIE1_SHIFT (1U) 237 #define SINC_NIE_COCIE1_WIDTH (1U) 238 #define SINC_NIE_COCIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE1_SHIFT)) & SINC_NIE_COCIE1_MASK) 239 240 #define SINC_NIE_COCIE2_MASK (0x4U) 241 #define SINC_NIE_COCIE2_SHIFT (2U) 242 #define SINC_NIE_COCIE2_WIDTH (1U) 243 #define SINC_NIE_COCIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE2_SHIFT)) & SINC_NIE_COCIE2_MASK) 244 245 #define SINC_NIE_COCIE3_MASK (0x8U) 246 #define SINC_NIE_COCIE3_SHIFT (3U) 247 #define SINC_NIE_COCIE3_WIDTH (1U) 248 #define SINC_NIE_COCIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE3_SHIFT)) & SINC_NIE_COCIE3_MASK) 249 250 #define SINC_NIE_CHFIE0_MASK (0x100U) 251 #define SINC_NIE_CHFIE0_SHIFT (8U) 252 #define SINC_NIE_CHFIE0_WIDTH (1U) 253 #define SINC_NIE_CHFIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE0_SHIFT)) & SINC_NIE_CHFIE0_MASK) 254 255 #define SINC_NIE_CHFIE1_MASK (0x200U) 256 #define SINC_NIE_CHFIE1_SHIFT (9U) 257 #define SINC_NIE_CHFIE1_WIDTH (1U) 258 #define SINC_NIE_CHFIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE1_SHIFT)) & SINC_NIE_CHFIE1_MASK) 259 260 #define SINC_NIE_CHFIE2_MASK (0x400U) 261 #define SINC_NIE_CHFIE2_SHIFT (10U) 262 #define SINC_NIE_CHFIE2_WIDTH (1U) 263 #define SINC_NIE_CHFIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE2_SHIFT)) & SINC_NIE_CHFIE2_MASK) 264 265 #define SINC_NIE_CHFIE3_MASK (0x800U) 266 #define SINC_NIE_CHFIE3_SHIFT (11U) 267 #define SINC_NIE_CHFIE3_WIDTH (1U) 268 #define SINC_NIE_CHFIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE3_SHIFT)) & SINC_NIE_CHFIE3_MASK) 269 270 #define SINC_NIE_ZCDIE0_MASK (0x10000U) 271 #define SINC_NIE_ZCDIE0_SHIFT (16U) 272 #define SINC_NIE_ZCDIE0_WIDTH (1U) 273 #define SINC_NIE_ZCDIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE0_SHIFT)) & SINC_NIE_ZCDIE0_MASK) 274 275 #define SINC_NIE_ZCDIE1_MASK (0x20000U) 276 #define SINC_NIE_ZCDIE1_SHIFT (17U) 277 #define SINC_NIE_ZCDIE1_WIDTH (1U) 278 #define SINC_NIE_ZCDIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE1_SHIFT)) & SINC_NIE_ZCDIE1_MASK) 279 280 #define SINC_NIE_ZCDIE2_MASK (0x40000U) 281 #define SINC_NIE_ZCDIE2_SHIFT (18U) 282 #define SINC_NIE_ZCDIE2_WIDTH (1U) 283 #define SINC_NIE_ZCDIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE2_SHIFT)) & SINC_NIE_ZCDIE2_MASK) 284 285 #define SINC_NIE_ZCDIE3_MASK (0x80000U) 286 #define SINC_NIE_ZCDIE3_SHIFT (19U) 287 #define SINC_NIE_ZCDIE3_WIDTH (1U) 288 #define SINC_NIE_ZCDIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE3_SHIFT)) & SINC_NIE_ZCDIE3_MASK) 289 /*! @} */ 290 291 /*! @name EIE - Error Interrupt Enable */ 292 /*! @{ */ 293 294 #define SINC_EIE_SCDIE0_MASK (0x1U) 295 #define SINC_EIE_SCDIE0_SHIFT (0U) 296 #define SINC_EIE_SCDIE0_WIDTH (1U) 297 #define SINC_EIE_SCDIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE0_SHIFT)) & SINC_EIE_SCDIE0_MASK) 298 299 #define SINC_EIE_SCDIE1_MASK (0x2U) 300 #define SINC_EIE_SCDIE1_SHIFT (1U) 301 #define SINC_EIE_SCDIE1_WIDTH (1U) 302 #define SINC_EIE_SCDIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE1_SHIFT)) & SINC_EIE_SCDIE1_MASK) 303 304 #define SINC_EIE_SCDIE2_MASK (0x4U) 305 #define SINC_EIE_SCDIE2_SHIFT (2U) 306 #define SINC_EIE_SCDIE2_WIDTH (1U) 307 #define SINC_EIE_SCDIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE2_SHIFT)) & SINC_EIE_SCDIE2_MASK) 308 309 #define SINC_EIE_SCDIE3_MASK (0x8U) 310 #define SINC_EIE_SCDIE3_SHIFT (3U) 311 #define SINC_EIE_SCDIE3_WIDTH (1U) 312 #define SINC_EIE_SCDIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE3_SHIFT)) & SINC_EIE_SCDIE3_MASK) 313 314 #define SINC_EIE_WLMTIE0_MASK (0x100U) 315 #define SINC_EIE_WLMTIE0_SHIFT (8U) 316 #define SINC_EIE_WLMTIE0_WIDTH (1U) 317 #define SINC_EIE_WLMTIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE0_SHIFT)) & SINC_EIE_WLMTIE0_MASK) 318 319 #define SINC_EIE_WLMTIE1_MASK (0x200U) 320 #define SINC_EIE_WLMTIE1_SHIFT (9U) 321 #define SINC_EIE_WLMTIE1_WIDTH (1U) 322 #define SINC_EIE_WLMTIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE1_SHIFT)) & SINC_EIE_WLMTIE1_MASK) 323 324 #define SINC_EIE_WLMTIE2_MASK (0x400U) 325 #define SINC_EIE_WLMTIE2_SHIFT (10U) 326 #define SINC_EIE_WLMTIE2_WIDTH (1U) 327 #define SINC_EIE_WLMTIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE2_SHIFT)) & SINC_EIE_WLMTIE2_MASK) 328 329 #define SINC_EIE_WLMTIE3_MASK (0x800U) 330 #define SINC_EIE_WLMTIE3_SHIFT (11U) 331 #define SINC_EIE_WLMTIE3_WIDTH (1U) 332 #define SINC_EIE_WLMTIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE3_SHIFT)) & SINC_EIE_WLMTIE3_MASK) 333 334 #define SINC_EIE_LLMTIE0_MASK (0x10000U) 335 #define SINC_EIE_LLMTIE0_SHIFT (16U) 336 #define SINC_EIE_LLMTIE0_WIDTH (1U) 337 #define SINC_EIE_LLMTIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE0_SHIFT)) & SINC_EIE_LLMTIE0_MASK) 338 339 #define SINC_EIE_LLMTIE1_MASK (0x20000U) 340 #define SINC_EIE_LLMTIE1_SHIFT (17U) 341 #define SINC_EIE_LLMTIE1_WIDTH (1U) 342 #define SINC_EIE_LLMTIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE1_SHIFT)) & SINC_EIE_LLMTIE1_MASK) 343 344 #define SINC_EIE_LLMTIE2_MASK (0x40000U) 345 #define SINC_EIE_LLMTIE2_SHIFT (18U) 346 #define SINC_EIE_LLMTIE2_WIDTH (1U) 347 #define SINC_EIE_LLMTIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE2_SHIFT)) & SINC_EIE_LLMTIE2_MASK) 348 349 #define SINC_EIE_LLMTIE3_MASK (0x80000U) 350 #define SINC_EIE_LLMTIE3_SHIFT (19U) 351 #define SINC_EIE_LLMTIE3_WIDTH (1U) 352 #define SINC_EIE_LLMTIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE3_SHIFT)) & SINC_EIE_LLMTIE3_MASK) 353 354 #define SINC_EIE_HLMTIE0_MASK (0x1000000U) 355 #define SINC_EIE_HLMTIE0_SHIFT (24U) 356 #define SINC_EIE_HLMTIE0_WIDTH (1U) 357 #define SINC_EIE_HLMTIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE0_SHIFT)) & SINC_EIE_HLMTIE0_MASK) 358 359 #define SINC_EIE_HLMTIE1_MASK (0x2000000U) 360 #define SINC_EIE_HLMTIE1_SHIFT (25U) 361 #define SINC_EIE_HLMTIE1_WIDTH (1U) 362 #define SINC_EIE_HLMTIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE1_SHIFT)) & SINC_EIE_HLMTIE1_MASK) 363 364 #define SINC_EIE_HLMTIE2_MASK (0x4000000U) 365 #define SINC_EIE_HLMTIE2_SHIFT (26U) 366 #define SINC_EIE_HLMTIE2_WIDTH (1U) 367 #define SINC_EIE_HLMTIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE2_SHIFT)) & SINC_EIE_HLMTIE2_MASK) 368 369 #define SINC_EIE_HLMTIE3_MASK (0x8000000U) 370 #define SINC_EIE_HLMTIE3_SHIFT (27U) 371 #define SINC_EIE_HLMTIE3_WIDTH (1U) 372 #define SINC_EIE_HLMTIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE3_SHIFT)) & SINC_EIE_HLMTIE3_MASK) 373 /*! @} */ 374 375 /*! @name FIFOIE - FIFO And CAD Error Interrupt Enable */ 376 /*! @{ */ 377 378 #define SINC_FIFOIE_FUNFIE0_MASK (0x1U) 379 #define SINC_FIFOIE_FUNFIE0_SHIFT (0U) 380 #define SINC_FIFOIE_FUNFIE0_WIDTH (1U) 381 #define SINC_FIFOIE_FUNFIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE0_SHIFT)) & SINC_FIFOIE_FUNFIE0_MASK) 382 383 #define SINC_FIFOIE_FUNFIE1_MASK (0x2U) 384 #define SINC_FIFOIE_FUNFIE1_SHIFT (1U) 385 #define SINC_FIFOIE_FUNFIE1_WIDTH (1U) 386 #define SINC_FIFOIE_FUNFIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE1_SHIFT)) & SINC_FIFOIE_FUNFIE1_MASK) 387 388 #define SINC_FIFOIE_FUNFIE2_MASK (0x4U) 389 #define SINC_FIFOIE_FUNFIE2_SHIFT (2U) 390 #define SINC_FIFOIE_FUNFIE2_WIDTH (1U) 391 #define SINC_FIFOIE_FUNFIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE2_SHIFT)) & SINC_FIFOIE_FUNFIE2_MASK) 392 393 #define SINC_FIFOIE_FUNFIE3_MASK (0x8U) 394 #define SINC_FIFOIE_FUNFIE3_SHIFT (3U) 395 #define SINC_FIFOIE_FUNFIE3_WIDTH (1U) 396 #define SINC_FIFOIE_FUNFIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE3_SHIFT)) & SINC_FIFOIE_FUNFIE3_MASK) 397 398 #define SINC_FIFOIE_FOVFIE0_MASK (0x100U) 399 #define SINC_FIFOIE_FOVFIE0_SHIFT (8U) 400 #define SINC_FIFOIE_FOVFIE0_WIDTH (1U) 401 #define SINC_FIFOIE_FOVFIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE0_SHIFT)) & SINC_FIFOIE_FOVFIE0_MASK) 402 403 #define SINC_FIFOIE_FOVFIE1_MASK (0x200U) 404 #define SINC_FIFOIE_FOVFIE1_SHIFT (9U) 405 #define SINC_FIFOIE_FOVFIE1_WIDTH (1U) 406 #define SINC_FIFOIE_FOVFIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE1_SHIFT)) & SINC_FIFOIE_FOVFIE1_MASK) 407 408 #define SINC_FIFOIE_FOVFIE2_MASK (0x400U) 409 #define SINC_FIFOIE_FOVFIE2_SHIFT (10U) 410 #define SINC_FIFOIE_FOVFIE2_WIDTH (1U) 411 #define SINC_FIFOIE_FOVFIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE2_SHIFT)) & SINC_FIFOIE_FOVFIE2_MASK) 412 413 #define SINC_FIFOIE_FOVFIE3_MASK (0x800U) 414 #define SINC_FIFOIE_FOVFIE3_SHIFT (11U) 415 #define SINC_FIFOIE_FOVFIE3_WIDTH (1U) 416 #define SINC_FIFOIE_FOVFIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE3_SHIFT)) & SINC_FIFOIE_FOVFIE3_MASK) 417 418 #define SINC_FIFOIE_CADIE0_MASK (0x10000U) 419 #define SINC_FIFOIE_CADIE0_SHIFT (16U) 420 #define SINC_FIFOIE_CADIE0_WIDTH (1U) 421 #define SINC_FIFOIE_CADIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE0_SHIFT)) & SINC_FIFOIE_CADIE0_MASK) 422 423 #define SINC_FIFOIE_CADIE1_MASK (0x20000U) 424 #define SINC_FIFOIE_CADIE1_SHIFT (17U) 425 #define SINC_FIFOIE_CADIE1_WIDTH (1U) 426 #define SINC_FIFOIE_CADIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE1_SHIFT)) & SINC_FIFOIE_CADIE1_MASK) 427 428 #define SINC_FIFOIE_CADIE2_MASK (0x40000U) 429 #define SINC_FIFOIE_CADIE2_SHIFT (18U) 430 #define SINC_FIFOIE_CADIE2_WIDTH (1U) 431 #define SINC_FIFOIE_CADIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE2_SHIFT)) & SINC_FIFOIE_CADIE2_MASK) 432 433 #define SINC_FIFOIE_CADIE3_MASK (0x80000U) 434 #define SINC_FIFOIE_CADIE3_SHIFT (19U) 435 #define SINC_FIFOIE_CADIE3_WIDTH (1U) 436 #define SINC_FIFOIE_CADIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE3_SHIFT)) & SINC_FIFOIE_CADIE3_MASK) 437 438 #define SINC_FIFOIE_SATIE0_MASK (0x1000000U) 439 #define SINC_FIFOIE_SATIE0_SHIFT (24U) 440 #define SINC_FIFOIE_SATIE0_WIDTH (1U) 441 #define SINC_FIFOIE_SATIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE0_SHIFT)) & SINC_FIFOIE_SATIE0_MASK) 442 443 #define SINC_FIFOIE_SATIE1_MASK (0x2000000U) 444 #define SINC_FIFOIE_SATIE1_SHIFT (25U) 445 #define SINC_FIFOIE_SATIE1_WIDTH (1U) 446 #define SINC_FIFOIE_SATIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE1_SHIFT)) & SINC_FIFOIE_SATIE1_MASK) 447 448 #define SINC_FIFOIE_SATIE2_MASK (0x4000000U) 449 #define SINC_FIFOIE_SATIE2_SHIFT (26U) 450 #define SINC_FIFOIE_SATIE2_WIDTH (1U) 451 #define SINC_FIFOIE_SATIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE2_SHIFT)) & SINC_FIFOIE_SATIE2_MASK) 452 453 #define SINC_FIFOIE_SATIE3_MASK (0x8000000U) 454 #define SINC_FIFOIE_SATIE3_SHIFT (27U) 455 #define SINC_FIFOIE_SATIE3_WIDTH (1U) 456 #define SINC_FIFOIE_SATIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE3_SHIFT)) & SINC_FIFOIE_SATIE3_MASK) 457 /*! @} */ 458 459 /*! @name NIS - Normal Interrupt Status */ 460 /*! @{ */ 461 462 #define SINC_NIS_COC0_MASK (0x1U) 463 #define SINC_NIS_COC0_SHIFT (0U) 464 #define SINC_NIS_COC0_WIDTH (1U) 465 #define SINC_NIS_COC0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC0_SHIFT)) & SINC_NIS_COC0_MASK) 466 467 #define SINC_NIS_COC1_MASK (0x2U) 468 #define SINC_NIS_COC1_SHIFT (1U) 469 #define SINC_NIS_COC1_WIDTH (1U) 470 #define SINC_NIS_COC1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC1_SHIFT)) & SINC_NIS_COC1_MASK) 471 472 #define SINC_NIS_COC2_MASK (0x4U) 473 #define SINC_NIS_COC2_SHIFT (2U) 474 #define SINC_NIS_COC2_WIDTH (1U) 475 #define SINC_NIS_COC2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC2_SHIFT)) & SINC_NIS_COC2_MASK) 476 477 #define SINC_NIS_COC3_MASK (0x8U) 478 #define SINC_NIS_COC3_SHIFT (3U) 479 #define SINC_NIS_COC3_WIDTH (1U) 480 #define SINC_NIS_COC3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC3_SHIFT)) & SINC_NIS_COC3_MASK) 481 482 #define SINC_NIS_CHF0_MASK (0x100U) 483 #define SINC_NIS_CHF0_SHIFT (8U) 484 #define SINC_NIS_CHF0_WIDTH (1U) 485 #define SINC_NIS_CHF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF0_SHIFT)) & SINC_NIS_CHF0_MASK) 486 487 #define SINC_NIS_CHF1_MASK (0x200U) 488 #define SINC_NIS_CHF1_SHIFT (9U) 489 #define SINC_NIS_CHF1_WIDTH (1U) 490 #define SINC_NIS_CHF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF1_SHIFT)) & SINC_NIS_CHF1_MASK) 491 492 #define SINC_NIS_CHF2_MASK (0x400U) 493 #define SINC_NIS_CHF2_SHIFT (10U) 494 #define SINC_NIS_CHF2_WIDTH (1U) 495 #define SINC_NIS_CHF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF2_SHIFT)) & SINC_NIS_CHF2_MASK) 496 497 #define SINC_NIS_CHF3_MASK (0x800U) 498 #define SINC_NIS_CHF3_SHIFT (11U) 499 #define SINC_NIS_CHF3_WIDTH (1U) 500 #define SINC_NIS_CHF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF3_SHIFT)) & SINC_NIS_CHF3_MASK) 501 502 #define SINC_NIS_ZCD0_MASK (0x10000U) 503 #define SINC_NIS_ZCD0_SHIFT (16U) 504 #define SINC_NIS_ZCD0_WIDTH (1U) 505 #define SINC_NIS_ZCD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD0_SHIFT)) & SINC_NIS_ZCD0_MASK) 506 507 #define SINC_NIS_ZCD1_MASK (0x20000U) 508 #define SINC_NIS_ZCD1_SHIFT (17U) 509 #define SINC_NIS_ZCD1_WIDTH (1U) 510 #define SINC_NIS_ZCD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD1_SHIFT)) & SINC_NIS_ZCD1_MASK) 511 512 #define SINC_NIS_ZCD2_MASK (0x40000U) 513 #define SINC_NIS_ZCD2_SHIFT (18U) 514 #define SINC_NIS_ZCD2_WIDTH (1U) 515 #define SINC_NIS_ZCD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD2_SHIFT)) & SINC_NIS_ZCD2_MASK) 516 517 #define SINC_NIS_ZCD3_MASK (0x80000U) 518 #define SINC_NIS_ZCD3_SHIFT (19U) 519 #define SINC_NIS_ZCD3_WIDTH (1U) 520 #define SINC_NIS_ZCD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD3_SHIFT)) & SINC_NIS_ZCD3_MASK) 521 /*! @} */ 522 523 /*! @name EIS - Error Interrupt Status */ 524 /*! @{ */ 525 526 #define SINC_EIS_SCD0_MASK (0x1U) 527 #define SINC_EIS_SCD0_SHIFT (0U) 528 #define SINC_EIS_SCD0_WIDTH (1U) 529 #define SINC_EIS_SCD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD0_SHIFT)) & SINC_EIS_SCD0_MASK) 530 531 #define SINC_EIS_SCD1_MASK (0x2U) 532 #define SINC_EIS_SCD1_SHIFT (1U) 533 #define SINC_EIS_SCD1_WIDTH (1U) 534 #define SINC_EIS_SCD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD1_SHIFT)) & SINC_EIS_SCD1_MASK) 535 536 #define SINC_EIS_SCD2_MASK (0x4U) 537 #define SINC_EIS_SCD2_SHIFT (2U) 538 #define SINC_EIS_SCD2_WIDTH (1U) 539 #define SINC_EIS_SCD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD2_SHIFT)) & SINC_EIS_SCD2_MASK) 540 541 #define SINC_EIS_SCD3_MASK (0x8U) 542 #define SINC_EIS_SCD3_SHIFT (3U) 543 #define SINC_EIS_SCD3_WIDTH (1U) 544 #define SINC_EIS_SCD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD3_SHIFT)) & SINC_EIS_SCD3_MASK) 545 546 #define SINC_EIS_WLMT0_MASK (0x100U) 547 #define SINC_EIS_WLMT0_SHIFT (8U) 548 #define SINC_EIS_WLMT0_WIDTH (1U) 549 #define SINC_EIS_WLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT0_SHIFT)) & SINC_EIS_WLMT0_MASK) 550 551 #define SINC_EIS_WLMT1_MASK (0x200U) 552 #define SINC_EIS_WLMT1_SHIFT (9U) 553 #define SINC_EIS_WLMT1_WIDTH (1U) 554 #define SINC_EIS_WLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT1_SHIFT)) & SINC_EIS_WLMT1_MASK) 555 556 #define SINC_EIS_WLMT2_MASK (0x400U) 557 #define SINC_EIS_WLMT2_SHIFT (10U) 558 #define SINC_EIS_WLMT2_WIDTH (1U) 559 #define SINC_EIS_WLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT2_SHIFT)) & SINC_EIS_WLMT2_MASK) 560 561 #define SINC_EIS_WLMT3_MASK (0x800U) 562 #define SINC_EIS_WLMT3_SHIFT (11U) 563 #define SINC_EIS_WLMT3_WIDTH (1U) 564 #define SINC_EIS_WLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT3_SHIFT)) & SINC_EIS_WLMT3_MASK) 565 566 #define SINC_EIS_LLMT0_MASK (0x10000U) 567 #define SINC_EIS_LLMT0_SHIFT (16U) 568 #define SINC_EIS_LLMT0_WIDTH (1U) 569 #define SINC_EIS_LLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT0_SHIFT)) & SINC_EIS_LLMT0_MASK) 570 571 #define SINC_EIS_LLMT1_MASK (0x20000U) 572 #define SINC_EIS_LLMT1_SHIFT (17U) 573 #define SINC_EIS_LLMT1_WIDTH (1U) 574 #define SINC_EIS_LLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT1_SHIFT)) & SINC_EIS_LLMT1_MASK) 575 576 #define SINC_EIS_LLMT2_MASK (0x40000U) 577 #define SINC_EIS_LLMT2_SHIFT (18U) 578 #define SINC_EIS_LLMT2_WIDTH (1U) 579 #define SINC_EIS_LLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT2_SHIFT)) & SINC_EIS_LLMT2_MASK) 580 581 #define SINC_EIS_LLMT3_MASK (0x80000U) 582 #define SINC_EIS_LLMT3_SHIFT (19U) 583 #define SINC_EIS_LLMT3_WIDTH (1U) 584 #define SINC_EIS_LLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT3_SHIFT)) & SINC_EIS_LLMT3_MASK) 585 586 #define SINC_EIS_HLMT0_MASK (0x1000000U) 587 #define SINC_EIS_HLMT0_SHIFT (24U) 588 #define SINC_EIS_HLMT0_WIDTH (1U) 589 #define SINC_EIS_HLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT0_SHIFT)) & SINC_EIS_HLMT0_MASK) 590 591 #define SINC_EIS_HLMT1_MASK (0x2000000U) 592 #define SINC_EIS_HLMT1_SHIFT (25U) 593 #define SINC_EIS_HLMT1_WIDTH (1U) 594 #define SINC_EIS_HLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT1_SHIFT)) & SINC_EIS_HLMT1_MASK) 595 596 #define SINC_EIS_HLMT2_MASK (0x4000000U) 597 #define SINC_EIS_HLMT2_SHIFT (26U) 598 #define SINC_EIS_HLMT2_WIDTH (1U) 599 #define SINC_EIS_HLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT2_SHIFT)) & SINC_EIS_HLMT2_MASK) 600 601 #define SINC_EIS_HLMT3_MASK (0x8000000U) 602 #define SINC_EIS_HLMT3_SHIFT (27U) 603 #define SINC_EIS_HLMT3_WIDTH (1U) 604 #define SINC_EIS_HLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT3_SHIFT)) & SINC_EIS_HLMT3_MASK) 605 /*! @} */ 606 607 /*! @name FIFOIS - FIFO And CAD Error Interrupt Status */ 608 /*! @{ */ 609 610 #define SINC_FIFOIS_FUNF0_MASK (0x1U) 611 #define SINC_FIFOIS_FUNF0_SHIFT (0U) 612 #define SINC_FIFOIS_FUNF0_WIDTH (1U) 613 #define SINC_FIFOIS_FUNF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF0_SHIFT)) & SINC_FIFOIS_FUNF0_MASK) 614 615 #define SINC_FIFOIS_FUNF1_MASK (0x2U) 616 #define SINC_FIFOIS_FUNF1_SHIFT (1U) 617 #define SINC_FIFOIS_FUNF1_WIDTH (1U) 618 #define SINC_FIFOIS_FUNF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF1_SHIFT)) & SINC_FIFOIS_FUNF1_MASK) 619 620 #define SINC_FIFOIS_FUNF2_MASK (0x4U) 621 #define SINC_FIFOIS_FUNF2_SHIFT (2U) 622 #define SINC_FIFOIS_FUNF2_WIDTH (1U) 623 #define SINC_FIFOIS_FUNF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF2_SHIFT)) & SINC_FIFOIS_FUNF2_MASK) 624 625 #define SINC_FIFOIS_FUNF3_MASK (0x8U) 626 #define SINC_FIFOIS_FUNF3_SHIFT (3U) 627 #define SINC_FIFOIS_FUNF3_WIDTH (1U) 628 #define SINC_FIFOIS_FUNF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF3_SHIFT)) & SINC_FIFOIS_FUNF3_MASK) 629 630 #define SINC_FIFOIS_FOVF0_MASK (0x100U) 631 #define SINC_FIFOIS_FOVF0_SHIFT (8U) 632 #define SINC_FIFOIS_FOVF0_WIDTH (1U) 633 #define SINC_FIFOIS_FOVF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF0_SHIFT)) & SINC_FIFOIS_FOVF0_MASK) 634 635 #define SINC_FIFOIS_FOVF1_MASK (0x200U) 636 #define SINC_FIFOIS_FOVF1_SHIFT (9U) 637 #define SINC_FIFOIS_FOVF1_WIDTH (1U) 638 #define SINC_FIFOIS_FOVF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF1_SHIFT)) & SINC_FIFOIS_FOVF1_MASK) 639 640 #define SINC_FIFOIS_FOVF2_MASK (0x400U) 641 #define SINC_FIFOIS_FOVF2_SHIFT (10U) 642 #define SINC_FIFOIS_FOVF2_WIDTH (1U) 643 #define SINC_FIFOIS_FOVF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF2_SHIFT)) & SINC_FIFOIS_FOVF2_MASK) 644 645 #define SINC_FIFOIS_FOVF3_MASK (0x800U) 646 #define SINC_FIFOIS_FOVF3_SHIFT (11U) 647 #define SINC_FIFOIS_FOVF3_WIDTH (1U) 648 #define SINC_FIFOIS_FOVF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF3_SHIFT)) & SINC_FIFOIS_FOVF3_MASK) 649 650 #define SINC_FIFOIS_CAD0_MASK (0x10000U) 651 #define SINC_FIFOIS_CAD0_SHIFT (16U) 652 #define SINC_FIFOIS_CAD0_WIDTH (1U) 653 #define SINC_FIFOIS_CAD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD0_SHIFT)) & SINC_FIFOIS_CAD0_MASK) 654 655 #define SINC_FIFOIS_CAD1_MASK (0x20000U) 656 #define SINC_FIFOIS_CAD1_SHIFT (17U) 657 #define SINC_FIFOIS_CAD1_WIDTH (1U) 658 #define SINC_FIFOIS_CAD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD1_SHIFT)) & SINC_FIFOIS_CAD1_MASK) 659 660 #define SINC_FIFOIS_CAD2_MASK (0x40000U) 661 #define SINC_FIFOIS_CAD2_SHIFT (18U) 662 #define SINC_FIFOIS_CAD2_WIDTH (1U) 663 #define SINC_FIFOIS_CAD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD2_SHIFT)) & SINC_FIFOIS_CAD2_MASK) 664 665 #define SINC_FIFOIS_CAD3_MASK (0x80000U) 666 #define SINC_FIFOIS_CAD3_SHIFT (19U) 667 #define SINC_FIFOIS_CAD3_WIDTH (1U) 668 #define SINC_FIFOIS_CAD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD3_SHIFT)) & SINC_FIFOIS_CAD3_MASK) 669 670 #define SINC_FIFOIS_SAT0_MASK (0x1000000U) 671 #define SINC_FIFOIS_SAT0_SHIFT (24U) 672 #define SINC_FIFOIS_SAT0_WIDTH (1U) 673 #define SINC_FIFOIS_SAT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT0_SHIFT)) & SINC_FIFOIS_SAT0_MASK) 674 675 #define SINC_FIFOIS_SAT1_MASK (0x2000000U) 676 #define SINC_FIFOIS_SAT1_SHIFT (25U) 677 #define SINC_FIFOIS_SAT1_WIDTH (1U) 678 #define SINC_FIFOIS_SAT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT1_SHIFT)) & SINC_FIFOIS_SAT1_MASK) 679 680 #define SINC_FIFOIS_SAT2_MASK (0x4000000U) 681 #define SINC_FIFOIS_SAT2_SHIFT (26U) 682 #define SINC_FIFOIS_SAT2_WIDTH (1U) 683 #define SINC_FIFOIS_SAT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT2_SHIFT)) & SINC_FIFOIS_SAT2_MASK) 684 685 #define SINC_FIFOIS_SAT3_MASK (0x8000000U) 686 #define SINC_FIFOIS_SAT3_SHIFT (27U) 687 #define SINC_FIFOIS_SAT3_WIDTH (1U) 688 #define SINC_FIFOIS_SAT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT3_SHIFT)) & SINC_FIFOIS_SAT3_MASK) 689 /*! @} */ 690 691 /*! @name SR - Status */ 692 /*! @{ */ 693 694 #define SINC_SR_CIP0_MASK (0x1U) 695 #define SINC_SR_CIP0_SHIFT (0U) 696 #define SINC_SR_CIP0_WIDTH (1U) 697 #define SINC_SR_CIP0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP0_SHIFT)) & SINC_SR_CIP0_MASK) 698 699 #define SINC_SR_CIP1_MASK (0x2U) 700 #define SINC_SR_CIP1_SHIFT (1U) 701 #define SINC_SR_CIP1_WIDTH (1U) 702 #define SINC_SR_CIP1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP1_SHIFT)) & SINC_SR_CIP1_MASK) 703 704 #define SINC_SR_CIP2_MASK (0x4U) 705 #define SINC_SR_CIP2_SHIFT (2U) 706 #define SINC_SR_CIP2_WIDTH (1U) 707 #define SINC_SR_CIP2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP2_SHIFT)) & SINC_SR_CIP2_MASK) 708 709 #define SINC_SR_CIP3_MASK (0x8U) 710 #define SINC_SR_CIP3_SHIFT (3U) 711 #define SINC_SR_CIP3_WIDTH (1U) 712 #define SINC_SR_CIP3(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP3_SHIFT)) & SINC_SR_CIP3_MASK) 713 714 #define SINC_SR_CHRDY0_MASK (0x100U) 715 #define SINC_SR_CHRDY0_SHIFT (8U) 716 #define SINC_SR_CHRDY0_WIDTH (1U) 717 #define SINC_SR_CHRDY0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY0_SHIFT)) & SINC_SR_CHRDY0_MASK) 718 719 #define SINC_SR_CHRDY1_MASK (0x200U) 720 #define SINC_SR_CHRDY1_SHIFT (9U) 721 #define SINC_SR_CHRDY1_WIDTH (1U) 722 #define SINC_SR_CHRDY1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY1_SHIFT)) & SINC_SR_CHRDY1_MASK) 723 724 #define SINC_SR_CHRDY2_MASK (0x400U) 725 #define SINC_SR_CHRDY2_SHIFT (10U) 726 #define SINC_SR_CHRDY2_WIDTH (1U) 727 #define SINC_SR_CHRDY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY2_SHIFT)) & SINC_SR_CHRDY2_MASK) 728 729 #define SINC_SR_CHRDY3_MASK (0x800U) 730 #define SINC_SR_CHRDY3_SHIFT (11U) 731 #define SINC_SR_CHRDY3_WIDTH (1U) 732 #define SINC_SR_CHRDY3(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY3_SHIFT)) & SINC_SR_CHRDY3_MASK) 733 734 #define SINC_SR_FIFOEMPTY0_MASK (0x10000U) 735 #define SINC_SR_FIFOEMPTY0_SHIFT (16U) 736 #define SINC_SR_FIFOEMPTY0_WIDTH (1U) 737 #define SINC_SR_FIFOEMPTY0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY0_SHIFT)) & SINC_SR_FIFOEMPTY0_MASK) 738 739 #define SINC_SR_FIFOEMPTY1_MASK (0x20000U) 740 #define SINC_SR_FIFOEMPTY1_SHIFT (17U) 741 #define SINC_SR_FIFOEMPTY1_WIDTH (1U) 742 #define SINC_SR_FIFOEMPTY1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY1_SHIFT)) & SINC_SR_FIFOEMPTY1_MASK) 743 744 #define SINC_SR_FIFOEMPTY2_MASK (0x40000U) 745 #define SINC_SR_FIFOEMPTY2_SHIFT (18U) 746 #define SINC_SR_FIFOEMPTY2_WIDTH (1U) 747 #define SINC_SR_FIFOEMPTY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY2_SHIFT)) & SINC_SR_FIFOEMPTY2_MASK) 748 749 #define SINC_SR_FIFOEMPTY3_MASK (0x80000U) 750 #define SINC_SR_FIFOEMPTY3_SHIFT (19U) 751 #define SINC_SR_FIFOEMPTY3_WIDTH (1U) 752 #define SINC_SR_FIFOEMPTY3(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY3_SHIFT)) & SINC_SR_FIFOEMPTY3_MASK) 753 754 #define SINC_SR_MCLKRDY0_MASK (0x1000000U) 755 #define SINC_SR_MCLKRDY0_SHIFT (24U) 756 #define SINC_SR_MCLKRDY0_WIDTH (1U) 757 #define SINC_SR_MCLKRDY0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY0_SHIFT)) & SINC_SR_MCLKRDY0_MASK) 758 759 #define SINC_SR_MCLKRDY1_MASK (0x2000000U) 760 #define SINC_SR_MCLKRDY1_SHIFT (25U) 761 #define SINC_SR_MCLKRDY1_WIDTH (1U) 762 #define SINC_SR_MCLKRDY1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY1_SHIFT)) & SINC_SR_MCLKRDY1_MASK) 763 764 #define SINC_SR_MCLKRDY2_MASK (0x4000000U) 765 #define SINC_SR_MCLKRDY2_SHIFT (26U) 766 #define SINC_SR_MCLKRDY2_WIDTH (1U) 767 #define SINC_SR_MCLKRDY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY2_SHIFT)) & SINC_SR_MCLKRDY2_MASK) 768 /*! @} */ 769 770 /*! @name CCR - Channel 0 Control..Channel 3 Control */ 771 /*! @{ */ 772 773 #define SINC_CCR_CHEN_MASK (0x1U) 774 #define SINC_CCR_CHEN_SHIFT (0U) 775 #define SINC_CCR_CHEN_WIDTH (1U) 776 #define SINC_CCR_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CHEN_SHIFT)) & SINC_CCR_CHEN_MASK) 777 778 #define SINC_CCR_PFEN_MASK (0x2U) 779 #define SINC_CCR_PFEN_SHIFT (1U) 780 #define SINC_CCR_PFEN_WIDTH (1U) 781 #define SINC_CCR_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_PFEN_SHIFT)) & SINC_CCR_PFEN_MASK) 782 783 #define SINC_CCR_DMAEN_MASK (0x8U) 784 #define SINC_CCR_DMAEN_SHIFT (3U) 785 #define SINC_CCR_DMAEN_WIDTH (1U) 786 #define SINC_CCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DMAEN_SHIFT)) & SINC_CCR_DMAEN_MASK) 787 788 #define SINC_CCR_SCDEN_MASK (0x100U) 789 #define SINC_CCR_SCDEN_SHIFT (8U) 790 #define SINC_CCR_SCDEN_WIDTH (1U) 791 #define SINC_CCR_SCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_SCDEN_SHIFT)) & SINC_CCR_SCDEN_MASK) 792 793 #define SINC_CCR_CADEN_MASK (0x200U) 794 #define SINC_CCR_CADEN_SHIFT (9U) 795 #define SINC_CCR_CADEN_WIDTH (1U) 796 #define SINC_CCR_CADEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK) 797 798 #define SINC_CCR_ZCDEN_MASK (0x1000U) 799 #define SINC_CCR_ZCDEN_SHIFT (12U) 800 #define SINC_CCR_ZCDEN_WIDTH (1U) 801 #define SINC_CCR_ZCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_ZCDEN_SHIFT)) & SINC_CCR_ZCDEN_MASK) 802 803 #define SINC_CCR_LMTEN_MASK (0x2000U) 804 #define SINC_CCR_LMTEN_SHIFT (13U) 805 #define SINC_CCR_LMTEN_WIDTH (1U) 806 #define SINC_CCR_LMTEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_LMTEN_SHIFT)) & SINC_CCR_LMTEN_MASK) 807 808 #define SINC_CCR_FIFOEN_MASK (0x4000U) 809 #define SINC_CCR_FIFOEN_SHIFT (14U) 810 #define SINC_CCR_FIFOEN_WIDTH (1U) 811 #define SINC_CCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_FIFOEN_SHIFT)) & SINC_CCR_FIFOEN_MASK) 812 813 #define SINC_CCR_DBGSEL_MASK (0xF00000U) 814 #define SINC_CCR_DBGSEL_SHIFT (20U) 815 #define SINC_CCR_DBGSEL_WIDTH (4U) 816 #define SINC_CCR_DBGSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DBGSEL_SHIFT)) & SINC_CCR_DBGSEL_MASK) 817 /*! @} */ 818 819 /*! @name CDR - Channel 0 Data Rate..Channel 3 Data Rate */ 820 /*! @{ */ 821 822 #define SINC_CDR_PFOSR_MASK (0x7FFU) 823 #define SINC_CDR_PFOSR_SHIFT (0U) 824 #define SINC_CDR_PFOSR_WIDTH (11U) 825 #define SINC_CDR_PFOSR(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFOSR_SHIFT)) & SINC_CDR_PFOSR_MASK) 826 827 #define SINC_CDR_PFORD_MASK (0x1800U) 828 #define SINC_CDR_PFORD_SHIFT (11U) 829 #define SINC_CDR_PFORD_WIDTH (2U) 830 #define SINC_CDR_PFORD(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFORD_SHIFT)) & SINC_CDR_PFORD_MASK) 831 832 #define SINC_CDR_PFCM_MASK (0xC000U) 833 #define SINC_CDR_PFCM_SHIFT (14U) 834 #define SINC_CDR_PFCM_WIDTH (2U) 835 #define SINC_CDR_PFCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFCM_SHIFT)) & SINC_CDR_PFCM_MASK) 836 /*! @} */ 837 838 /*! @name CCFR - Channel 0 Configuration..Channel 3 Configuration */ 839 /*! @{ */ 840 841 #define SINC_CCFR_PFSFT_MASK (0x1FU) 842 #define SINC_CCFR_PFSFT_SHIFT (0U) 843 #define SINC_CCFR_PFSFT_WIDTH (5U) 844 #define SINC_CCFR_PFSFT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_PFSFT_SHIFT)) & SINC_CCFR_PFSFT_MASK) 845 846 #define SINC_CCFR_RDFMT_MASK (0x40U) 847 #define SINC_CCFR_RDFMT_SHIFT (6U) 848 #define SINC_CCFR_RDFMT_WIDTH (1U) 849 #define SINC_CCFR_RDFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_RDFMT_SHIFT)) & SINC_CCFR_RDFMT_MASK) 850 851 #define SINC_CCFR_FIFOWMK_MASK (0x3C00U) 852 #define SINC_CCFR_FIFOWMK_SHIFT (10U) 853 #define SINC_CCFR_FIFOWMK_WIDTH (4U) 854 #define SINC_CCFR_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_FIFOWMK_SHIFT)) & SINC_CCFR_FIFOWMK_MASK) 855 856 #define SINC_CCFR_IBFMT_MASK (0x30000U) 857 #define SINC_CCFR_IBFMT_SHIFT (16U) 858 #define SINC_CCFR_IBFMT_WIDTH (2U) 859 #define SINC_CCFR_IBFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBFMT_SHIFT)) & SINC_CCFR_IBFMT_MASK) 860 861 #define SINC_CCFR_ICSEL_MASK (0x1C0000U) 862 #define SINC_CCFR_ICSEL_SHIFT (18U) 863 #define SINC_CCFR_ICSEL_WIDTH (3U) 864 #define SINC_CCFR_ICSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICSEL_SHIFT)) & SINC_CCFR_ICSEL_MASK) 865 866 #define SINC_CCFR_ICESEL_MASK (0xE00000U) 867 #define SINC_CCFR_ICESEL_SHIFT (21U) 868 #define SINC_CCFR_ICESEL_WIDTH (3U) 869 #define SINC_CCFR_ICESEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICESEL_SHIFT)) & SINC_CCFR_ICESEL_MASK) 870 871 #define SINC_CCFR_ITSEL_MASK (0x3000000U) 872 #define SINC_CCFR_ITSEL_SHIFT (24U) 873 #define SINC_CCFR_ITSEL_WIDTH (2U) 874 #define SINC_CCFR_ITSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITSEL_SHIFT)) & SINC_CCFR_ITSEL_MASK) 875 876 #define SINC_CCFR_IBSEL_MASK (0xC000000U) 877 #define SINC_CCFR_IBSEL_SHIFT (26U) 878 #define SINC_CCFR_IBSEL_WIDTH (2U) 879 #define SINC_CCFR_IBSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBSEL_SHIFT)) & SINC_CCFR_IBSEL_MASK) 880 881 #define SINC_CCFR_ITLVL_MASK (0x10000000U) 882 #define SINC_CCFR_ITLVL_SHIFT (28U) 883 #define SINC_CCFR_ITLVL_WIDTH (1U) 884 #define SINC_CCFR_ITLVL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITLVL_SHIFT)) & SINC_CCFR_ITLVL_MASK) 885 886 #define SINC_CCFR_ZCOP_MASK (0xC0000000U) 887 #define SINC_CCFR_ZCOP_SHIFT (30U) 888 #define SINC_CCFR_ZCOP_WIDTH (2U) 889 #define SINC_CCFR_ZCOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ZCOP_SHIFT)) & SINC_CCFR_ZCOP_MASK) 890 /*! @} */ 891 892 /*! @name CPROT - Channel 0 Protection..Channel 3 Protection */ 893 /*! @{ */ 894 895 #define SINC_CPROT_SCDLMT_MASK (0xFFU) 896 #define SINC_CPROT_SCDLMT_SHIFT (0U) 897 #define SINC_CPROT_SCDLMT_WIDTH (8U) 898 #define SINC_CPROT_SCDLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDLMT_SHIFT)) & SINC_CPROT_SCDLMT_MASK) 899 900 #define SINC_CPROT_SCDCM_MASK (0x800U) 901 #define SINC_CPROT_SCDCM_SHIFT (11U) 902 #define SINC_CPROT_SCDCM_WIDTH (1U) 903 #define SINC_CPROT_SCDCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDCM_SHIFT)) & SINC_CPROT_SCDCM_MASK) 904 905 #define SINC_CPROT_SCDOP_MASK (0x3000U) 906 #define SINC_CPROT_SCDOP_SHIFT (12U) 907 #define SINC_CPROT_SCDOP_WIDTH (2U) 908 #define SINC_CPROT_SCDOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDOP_SHIFT)) & SINC_CPROT_SCDOP_MASK) 909 910 #define SINC_CPROT_LMTOP_MASK (0xC000U) 911 #define SINC_CPROT_LMTOP_SHIFT (14U) 912 #define SINC_CPROT_LMTOP_WIDTH (2U) 913 #define SINC_CPROT_LMTOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LMTOP_SHIFT)) & SINC_CPROT_LMTOP_MASK) 914 915 #define SINC_CPROT_CADLMT_MASK (0xF0000U) 916 #define SINC_CPROT_CADLMT_SHIFT (16U) 917 #define SINC_CPROT_CADLMT_WIDTH (4U) 918 #define SINC_CPROT_CADLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADLMT_SHIFT)) & SINC_CPROT_CADLMT_MASK) 919 920 #define SINC_CPROT_CADBK_MASK (0x4000000U) 921 #define SINC_CPROT_CADBK_SHIFT (26U) 922 #define SINC_CPROT_CADBK_WIDTH (1U) 923 #define SINC_CPROT_CADBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADBK_SHIFT)) & SINC_CPROT_CADBK_MASK) 924 925 #define SINC_CPROT_SCDBK_MASK (0x8000000U) 926 #define SINC_CPROT_SCDBK_SHIFT (27U) 927 #define SINC_CPROT_SCDBK_WIDTH (1U) 928 #define SINC_CPROT_SCDBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDBK_SHIFT)) & SINC_CPROT_SCDBK_MASK) 929 930 #define SINC_CPROT_LLMTBK_MASK (0x20000000U) 931 #define SINC_CPROT_LLMTBK_SHIFT (29U) 932 #define SINC_CPROT_LLMTBK_WIDTH (1U) 933 #define SINC_CPROT_LLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LLMTBK_SHIFT)) & SINC_CPROT_LLMTBK_MASK) 934 935 #define SINC_CPROT_WLMTBK_MASK (0x40000000U) 936 #define SINC_CPROT_WLMTBK_SHIFT (30U) 937 #define SINC_CPROT_WLMTBK_WIDTH (1U) 938 #define SINC_CPROT_WLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_WLMTBK_SHIFT)) & SINC_CPROT_WLMTBK_MASK) 939 940 #define SINC_CPROT_HLMTBK_MASK (0x80000000U) 941 #define SINC_CPROT_HLMTBK_SHIFT (31U) 942 #define SINC_CPROT_HLMTBK_WIDTH (1U) 943 #define SINC_CPROT_HLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_HLMTBK_SHIFT)) & SINC_CPROT_HLMTBK_MASK) 944 /*! @} */ 945 946 /*! @name CBIAS - Channel 0 Bias..Channel 3 Bias */ 947 /*! @{ */ 948 949 #define SINC_CBIAS_BIAS_MASK (0xFFFFFF00U) 950 #define SINC_CBIAS_BIAS_SHIFT (8U) 951 #define SINC_CBIAS_BIAS_WIDTH (24U) 952 #define SINC_CBIAS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CBIAS_BIAS_SHIFT)) & SINC_CBIAS_BIAS_MASK) 953 /*! @} */ 954 955 /*! @name CLOLMT - Channel 0 Low Limit..Channel 3 Low Limit */ 956 /*! @{ */ 957 958 #define SINC_CLOLMT_LOLMT_MASK (0xFFFFFF00U) 959 #define SINC_CLOLMT_LOLMT_SHIFT (8U) 960 #define SINC_CLOLMT_LOLMT_WIDTH (24U) 961 #define SINC_CLOLMT_LOLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CLOLMT_LOLMT_SHIFT)) & SINC_CLOLMT_LOLMT_MASK) 962 /*! @} */ 963 964 /*! @name CHILMT - Channel 0 High Limit..Channel 3 High Limit */ 965 /*! @{ */ 966 967 #define SINC_CHILMT_HILMT_MASK (0xFFFFFF00U) 968 #define SINC_CHILMT_HILMT_SHIFT (8U) 969 #define SINC_CHILMT_HILMT_WIDTH (24U) 970 #define SINC_CHILMT_HILMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHILMT_HILMT_SHIFT)) & SINC_CHILMT_HILMT_MASK) 971 /*! @} */ 972 973 /*! @name CRDATA - Channel 0 Result Data..Channel 3 Result Data */ 974 /*! @{ */ 975 976 #define SINC_CRDATA_RDATA_MASK (0xFFFFFF00U) 977 #define SINC_CRDATA_RDATA_SHIFT (8U) 978 #define SINC_CRDATA_RDATA_WIDTH (24U) 979 #define SINC_CRDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CRDATA_RDATA_SHIFT)) & SINC_CRDATA_RDATA_MASK) 980 /*! @} */ 981 982 /*! @name CMPDATA - Channel 0 Multipurpose Data..Channel 3 Multipurpose Data */ 983 /*! @{ */ 984 985 #define SINC_CMPDATA_MPDATA_MASK (0xFFFFFFFFU) 986 #define SINC_CMPDATA_MPDATA_SHIFT (0U) 987 #define SINC_CMPDATA_MPDATA_WIDTH (32U) 988 #define SINC_CMPDATA_MPDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CMPDATA_MPDATA_SHIFT)) & SINC_CMPDATA_MPDATA_MASK) 989 /*! @} */ 990 991 /*! @name CACFR - Channel 0 Advanced Configuration..Channel 3 Advanced Configuration */ 992 /*! @{ */ 993 994 #define SINC_CACFR_HPFA_MASK (0xF0000U) 995 #define SINC_CACFR_HPFA_SHIFT (16U) 996 #define SINC_CACFR_HPFA_WIDTH (4U) 997 #define SINC_CACFR_HPFA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_HPFA_SHIFT)) & SINC_CACFR_HPFA_MASK) 998 999 #define SINC_CACFR_IBDLY_MASK (0xF00000U) 1000 #define SINC_CACFR_IBDLY_SHIFT (20U) 1001 #define SINC_CACFR_IBDLY_WIDTH (4U) 1002 #define SINC_CACFR_IBDLY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_IBDLY_SHIFT)) & SINC_CACFR_IBDLY_MASK) 1003 /*! @} */ 1004 1005 /*! @name CSR - Channel 0 Status..Channel 3 Status */ 1006 /*! @{ */ 1007 1008 #define SINC_CSR_FIFOAVIL_MASK (0x1FU) 1009 #define SINC_CSR_FIFOAVIL_SHIFT (0U) 1010 #define SINC_CSR_FIFOAVIL_WIDTH (5U) 1011 #define SINC_CSR_FIFOAVIL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_FIFOAVIL_SHIFT)) & SINC_CSR_FIFOAVIL_MASK) 1012 1013 #define SINC_CSR_PSRDY_MASK (0x80U) 1014 #define SINC_CSR_PSRDY_SHIFT (7U) 1015 #define SINC_CSR_PSRDY_WIDTH (1U) 1016 #define SINC_CSR_PSRDY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PSRDY_SHIFT)) & SINC_CSR_PSRDY_MASK) 1017 1018 #define SINC_CSR_PFSAT_MASK (0x100U) 1019 #define SINC_CSR_PFSAT_SHIFT (8U) 1020 #define SINC_CSR_PFSAT_WIDTH (1U) 1021 #define SINC_CSR_PFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PFSAT_SHIFT)) & SINC_CSR_PFSAT_MASK) 1022 1023 #define SINC_CSR_HPFSAT_MASK (0x200U) 1024 #define SINC_CSR_HPFSAT_SHIFT (9U) 1025 #define SINC_CSR_HPFSAT_WIDTH (1U) 1026 #define SINC_CSR_HPFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_HPFSAT_SHIFT)) & SINC_CSR_HPFSAT_MASK) 1027 1028 #define SINC_CSR_SFTSAT_MASK (0x400U) 1029 #define SINC_CSR_SFTSAT_SHIFT (10U) 1030 #define SINC_CSR_SFTSAT_WIDTH (1U) 1031 #define SINC_CSR_SFTSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SFTSAT_SHIFT)) & SINC_CSR_SFTSAT_MASK) 1032 1033 #define SINC_CSR_BIASSAT_MASK (0x800U) 1034 #define SINC_CSR_BIASSAT_SHIFT (11U) 1035 #define SINC_CSR_BIASSAT_WIDTH (1U) 1036 #define SINC_CSR_BIASSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_BIASSAT_SHIFT)) & SINC_CSR_BIASSAT_MASK) 1037 1038 #define SINC_CSR_RDRS_MASK (0x1000U) 1039 #define SINC_CSR_RDRS_SHIFT (12U) 1040 #define SINC_CSR_RDRS_WIDTH (1U) 1041 #define SINC_CSR_RDRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_RDRS_SHIFT)) & SINC_CSR_RDRS_MASK) 1042 1043 #define SINC_CSR_SRDS_MASK (0x2000U) 1044 #define SINC_CSR_SRDS_SHIFT (13U) 1045 #define SINC_CSR_SRDS_WIDTH (1U) 1046 #define SINC_CSR_SRDS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SRDS_SHIFT)) & SINC_CSR_SRDS_MASK) 1047 1048 #define SINC_CSR_DBGRS_MASK (0xC000U) 1049 #define SINC_CSR_DBGRS_SHIFT (14U) 1050 #define SINC_CSR_DBGRS_WIDTH (2U) 1051 #define SINC_CSR_DBGRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_DBGRS_SHIFT)) & SINC_CSR_DBGRS_MASK) 1052 1053 #define SINC_CSR_CNUM_MASK (0x7F0000U) 1054 #define SINC_CSR_CNUM_SHIFT (16U) 1055 #define SINC_CSR_CNUM_WIDTH (7U) 1056 #define SINC_CSR_CNUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_SHIFT)) & SINC_CSR_CNUM_MASK) 1057 1058 #define SINC_CSR_CNUM_OV_MASK (0x800000U) 1059 #define SINC_CSR_CNUM_OV_SHIFT (23U) 1060 #define SINC_CSR_CNUM_OV_WIDTH (1U) 1061 #define SINC_CSR_CNUM_OV(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_OV_SHIFT)) & SINC_CSR_CNUM_OV_MASK) 1062 /*! @} */ 1063 1064 /*! @name CDBGR - Channel 0 Debug..Channel 3 Debug */ 1065 /*! @{ */ 1066 1067 #define SINC_CDBGR_DBGDATA_MASK (0xFFFFFFFFU) 1068 #define SINC_CDBGR_DBGDATA_SHIFT (0U) 1069 #define SINC_CDBGR_DBGDATA_WIDTH (32U) 1070 #define SINC_CDBGR_DBGDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDBGR_DBGDATA_SHIFT)) & SINC_CDBGR_DBGDATA_MASK) 1071 /*! @} */ 1072 1073 /*! 1074 * @} 1075 */ /* end of group SINC_Register_Masks */ 1076 1077 /*! 1078 * @} 1079 */ /* end of group SINC_Peripheral_Access_Layer */ 1080 1081 #endif /* #if !defined(S32Z2_SINC_H_) */ 1082
