1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RXLUT.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_RXLUT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RXLUT_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RXLUT_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RXLUT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RXLUT_Peripheral_Access_Layer RXLUT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RXLUT - Size of Registers Arrays */ 72 #define RXLUT_RLSOIXR_COUNT 12u 73 #define RXLUT_RLSOFSR_COUNT 2u 74 #define RXLUT_RLICEC_COUNT 2u 75 76 /** RXLUT - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t RLCR; /**< RXLUT Configuration, offset: 0x0 */ 79 __IO uint32_t RLSR; /**< RXLUT Status, offset: 0x4 */ 80 __IO uint32_t RLSRIER; /**< RXLUT Search Result Interrupt Enable, offset: 0x8 */ 81 __I uint32_t RLSRSR; /**< RXLUT Search Result Status, offset: 0xC */ 82 __IO uint32_t RLFIMER; /**< RXLUT Frame ID End, offset: 0x10 */ 83 __IO uint32_t RLFISR; /**< RXLUT Frame ID Start, offset: 0x14 */ 84 __IO uint32_t RLCIXR; /**< RXLUT Channel ID AND Index, offset: 0x18 */ 85 __IO uint32_t RLADRCR; /**< RXLUT Address and Command, offset: 0x1C */ 86 __I uint32_t RLFIMESR; /**< RXLUT Frame ID End Status, offset: 0x20 */ 87 __I uint32_t RLFISSR; /**< RXLUT Frame ID Start Status, offset: 0x24 */ 88 __I uint32_t RLCIXSR; /**< RXLUT Channel ID AND Index Status, offset: 0x28 */ 89 __I uint32_t RLADRSR; /**< RXLUT Address Status, offset: 0x2C */ 90 uint8_t RESERVED_0[16]; 91 __IO uint32_t RLSICR; /**< RXLUT Search Input Command, offset: 0x40 */ 92 __IO uint32_t RLSICFIR; /**< RXLUT Search Input Command Frame ID, offset: 0x44 */ 93 struct RXLUT_RLSOIXR { /* offset: 0x48, array step: 0x8 */ 94 __I uint32_t RLSOIXR; /**< RXLUT Search Output, array offset: 0x48, array step: 0x8 */ 95 __I uint32_t RLSOADR; /**< RXLUT Search Output Address, array offset: 0x4C, array step: 0x8 */ 96 } RLSOIXR[RXLUT_RLSOIXR_COUNT]; 97 uint8_t RESERVED_1[168]; 98 __I uint32_t RLSICFSR; /**< RXLUT Search Input Command FIFO Status, offset: 0x150 */ 99 __I uint32_t RLSOFSR[RXLUT_RLSOFSR_COUNT]; /**< RXLUT Search Output FIFO Status, array offset: 0x154, array step: 0x4 */ 100 __I uint32_t RLICEC[RXLUT_RLICEC_COUNT]; /**< RXLUT Input Command Entry Counter, array offset: 0x15C, array step: 0x4 */ 101 __IO uint32_t RLER; /**< RXLUT Error, offset: 0x164 */ 102 __IO uint32_t RLOOR; /**< RXLUT Output Overflow, offset: 0x168 */ 103 } RXLUT_Type, *RXLUT_MemMapPtr; 104 105 /** Number of instances of the RXLUT module. */ 106 #define RXLUT_INSTANCE_COUNT (1u) 107 108 /* RXLUT - Peripheral instance base addresses */ 109 /** Peripheral CE_RXLUT base address */ 110 #define IP_CE_RXLUT_BASE (0x4488C000u) 111 /** Peripheral CE_RXLUT base pointer */ 112 #define IP_CE_RXLUT ((RXLUT_Type *)IP_CE_RXLUT_BASE) 113 /** Array initializer of RXLUT peripheral base addresses */ 114 #define IP_RXLUT_BASE_ADDRS { IP_CE_RXLUT_BASE } 115 /** Array initializer of RXLUT peripheral base pointers */ 116 #define IP_RXLUT_BASE_PTRS { IP_CE_RXLUT } 117 118 /* ---------------------------------------------------------------------------- 119 -- RXLUT Register Masks 120 ---------------------------------------------------------------------------- */ 121 122 /*! 123 * @addtogroup RXLUT_Register_Masks RXLUT Register Masks 124 * @{ 125 */ 126 127 /*! @name RLCR - RXLUT Configuration */ 128 /*! @{ */ 129 130 #define RXLUT_RLCR_RXLEN_MASK (0x1U) 131 #define RXLUT_RLCR_RXLEN_SHIFT (0U) 132 #define RXLUT_RLCR_RXLEN_WIDTH (1U) 133 #define RXLUT_RLCR_RXLEN(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_RXLEN_SHIFT)) & RXLUT_RLCR_RXLEN_MASK) 134 135 #define RXLUT_RLCR_SRCH_EN_MASK (0x2U) 136 #define RXLUT_RLCR_SRCH_EN_SHIFT (1U) 137 #define RXLUT_RLCR_SRCH_EN_WIDTH (1U) 138 #define RXLUT_RLCR_SRCH_EN(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_SRCH_EN_SHIFT)) & RXLUT_RLCR_SRCH_EN_MASK) 139 140 #define RXLUT_RLCR_PS_EN_MASK (0x4U) 141 #define RXLUT_RLCR_PS_EN_SHIFT (2U) 142 #define RXLUT_RLCR_PS_EN_WIDTH (1U) 143 #define RXLUT_RLCR_PS_EN(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_PS_EN_SHIFT)) & RXLUT_RLCR_PS_EN_MASK) 144 145 #define RXLUT_RLCR_SOVR_MASK (0x8U) 146 #define RXLUT_RLCR_SOVR_SHIFT (3U) 147 #define RXLUT_RLCR_SOVR_WIDTH (1U) 148 #define RXLUT_RLCR_SOVR(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_SOVR_SHIFT)) & RXLUT_RLCR_SOVR_MASK) 149 150 #define RXLUT_RLCR_FLUSH_MASK (0x10U) 151 #define RXLUT_RLCR_FLUSH_SHIFT (4U) 152 #define RXLUT_RLCR_FLUSH_WIDTH (1U) 153 #define RXLUT_RLCR_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_FLUSH_SHIFT)) & RXLUT_RLCR_FLUSH_MASK) 154 155 #define RXLUT_RLCR_ECC_EN_MASK (0x20U) 156 #define RXLUT_RLCR_ECC_EN_SHIFT (5U) 157 #define RXLUT_RLCR_ECC_EN_WIDTH (1U) 158 #define RXLUT_RLCR_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_ECC_EN_SHIFT)) & RXLUT_RLCR_ECC_EN_MASK) 159 160 #define RXLUT_RLCR_FID_RAR_EN_MASK (0x40U) 161 #define RXLUT_RLCR_FID_RAR_EN_SHIFT (6U) 162 #define RXLUT_RLCR_FID_RAR_EN_WIDTH (1U) 163 #define RXLUT_RLCR_FID_RAR_EN(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCR_FID_RAR_EN_SHIFT)) & RXLUT_RLCR_FID_RAR_EN_MASK) 164 /*! @} */ 165 166 /*! @name RLSR - RXLUT Status */ 167 /*! @{ */ 168 169 #define RXLUT_RLSR_BUSY_MASK (0x1U) 170 #define RXLUT_RLSR_BUSY_SHIFT (0U) 171 #define RXLUT_RLSR_BUSY_WIDTH (1U) 172 #define RXLUT_RLSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSR_BUSY_SHIFT)) & RXLUT_RLSR_BUSY_MASK) 173 174 #define RXLUT_RLSR_FLUSH_MASK (0x2U) 175 #define RXLUT_RLSR_FLUSH_SHIFT (1U) 176 #define RXLUT_RLSR_FLUSH_WIDTH (1U) 177 #define RXLUT_RLSR_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSR_FLUSH_SHIFT)) & RXLUT_RLSR_FLUSH_MASK) 178 179 #define RXLUT_RLSR_PENDS_MASK (0x4U) 180 #define RXLUT_RLSR_PENDS_SHIFT (2U) 181 #define RXLUT_RLSR_PENDS_WIDTH (1U) 182 #define RXLUT_RLSR_PENDS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSR_PENDS_SHIFT)) & RXLUT_RLSR_PENDS_MASK) 183 184 #define RXLUT_RLSR_MS_MASK (0x8U) 185 #define RXLUT_RLSR_MS_SHIFT (3U) 186 #define RXLUT_RLSR_MS_WIDTH (1U) 187 #define RXLUT_RLSR_MS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSR_MS_SHIFT)) & RXLUT_RLSR_MS_MASK) 188 189 #define RXLUT_RLSR_CIE_MASK (0x10U) 190 #define RXLUT_RLSR_CIE_SHIFT (4U) 191 #define RXLUT_RLSR_CIE_WIDTH (1U) 192 #define RXLUT_RLSR_CIE(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSR_CIE_SHIFT)) & RXLUT_RLSR_CIE_MASK) 193 /*! @} */ 194 195 /*! @name RLSRIER - RXLUT Search Result Interrupt Enable */ 196 /*! @{ */ 197 198 #define RXLUT_RLSRIER_AVLIE_MASK (0xFFFU) 199 #define RXLUT_RLSRIER_AVLIE_SHIFT (0U) 200 #define RXLUT_RLSRIER_AVLIE_WIDTH (12U) 201 #define RXLUT_RLSRIER_AVLIE(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSRIER_AVLIE_SHIFT)) & RXLUT_RLSRIER_AVLIE_MASK) 202 203 #define RXLUT_RLSRIER_PS_AVLIE_MASK (0x10000000U) 204 #define RXLUT_RLSRIER_PS_AVLIE_SHIFT (28U) 205 #define RXLUT_RLSRIER_PS_AVLIE_WIDTH (1U) 206 #define RXLUT_RLSRIER_PS_AVLIE(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSRIER_PS_AVLIE_SHIFT)) & RXLUT_RLSRIER_PS_AVLIE_MASK) 207 /*! @} */ 208 209 /*! @name RLSRSR - RXLUT Search Result Status */ 210 /*! @{ */ 211 212 #define RXLUT_RLSRSR_AVL_MASK (0xFFFU) 213 #define RXLUT_RLSRSR_AVL_SHIFT (0U) 214 #define RXLUT_RLSRSR_AVL_WIDTH (12U) 215 #define RXLUT_RLSRSR_AVL(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSRSR_AVL_SHIFT)) & RXLUT_RLSRSR_AVL_MASK) 216 217 #define RXLUT_RLSRSR_PS_AVL_MASK (0x10000000U) 218 #define RXLUT_RLSRSR_PS_AVL_SHIFT (28U) 219 #define RXLUT_RLSRSR_PS_AVL_WIDTH (1U) 220 #define RXLUT_RLSRSR_PS_AVL(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSRSR_PS_AVL_SHIFT)) & RXLUT_RLSRSR_PS_AVL_MASK) 221 /*! @} */ 222 223 /*! @name RLFIMER - RXLUT Frame ID End */ 224 /*! @{ */ 225 226 #define RXLUT_RLFIMER_FIME_MASK (0xFFFFFFFFU) 227 #define RXLUT_RLFIMER_FIME_SHIFT (0U) 228 #define RXLUT_RLFIMER_FIME_WIDTH (32U) 229 #define RXLUT_RLFIMER_FIME(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLFIMER_FIME_SHIFT)) & RXLUT_RLFIMER_FIME_MASK) 230 /*! @} */ 231 232 /*! @name RLFISR - RXLUT Frame ID Start */ 233 /*! @{ */ 234 235 #define RXLUT_RLFISR_FIS_MASK (0xFFFFFFFFU) 236 #define RXLUT_RLFISR_FIS_SHIFT (0U) 237 #define RXLUT_RLFISR_FIS_WIDTH (32U) 238 #define RXLUT_RLFISR_FIS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLFISR_FIS_SHIFT)) & RXLUT_RLFISR_FIS_MASK) 239 /*! @} */ 240 241 /*! @name RLCIXR - RXLUT Channel ID AND Index */ 242 /*! @{ */ 243 244 #define RXLUT_RLCIXR_SRCH_MASK (0x1U) 245 #define RXLUT_RLCIXR_SRCH_SHIFT (0U) 246 #define RXLUT_RLCIXR_SRCH_WIDTH (1U) 247 #define RXLUT_RLCIXR_SRCH(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXR_SRCH_SHIFT)) & RXLUT_RLCIXR_SRCH_MASK) 248 249 #define RXLUT_RLCIXR_ENABLE_MASK (0x2U) 250 #define RXLUT_RLCIXR_ENABLE_SHIFT (1U) 251 #define RXLUT_RLCIXR_ENABLE_WIDTH (1U) 252 #define RXLUT_RLCIXR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXR_ENABLE_SHIFT)) & RXLUT_RLCIXR_ENABLE_MASK) 253 254 #define RXLUT_RLCIXR_CID_MASK (0xFCU) 255 #define RXLUT_RLCIXR_CID_SHIFT (2U) 256 #define RXLUT_RLCIXR_CID_WIDTH (6U) 257 #define RXLUT_RLCIXR_CID(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXR_CID_SHIFT)) & RXLUT_RLCIXR_CID_MASK) 258 259 #define RXLUT_RLCIXR_CTRL_MASK (0x300U) 260 #define RXLUT_RLCIXR_CTRL_SHIFT (8U) 261 #define RXLUT_RLCIXR_CTRL_WIDTH (2U) 262 #define RXLUT_RLCIXR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXR_CTRL_SHIFT)) & RXLUT_RLCIXR_CTRL_MASK) 263 264 #define RXLUT_RLCIXR_INDX_MASK (0xFFFF0000U) 265 #define RXLUT_RLCIXR_INDX_SHIFT (16U) 266 #define RXLUT_RLCIXR_INDX_WIDTH (16U) 267 #define RXLUT_RLCIXR_INDX(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXR_INDX_SHIFT)) & RXLUT_RLCIXR_INDX_MASK) 268 /*! @} */ 269 270 /*! @name RLADRCR - RXLUT Address and Command */ 271 /*! @{ */ 272 273 #define RXLUT_RLADRCR_ADDR_MASK (0xFFFFU) 274 #define RXLUT_RLADRCR_ADDR_SHIFT (0U) 275 #define RXLUT_RLADRCR_ADDR_WIDTH (16U) 276 #define RXLUT_RLADRCR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLADRCR_ADDR_SHIFT)) & RXLUT_RLADRCR_ADDR_MASK) 277 278 #define RXLUT_RLADRCR_CMD_MASK (0x10000U) 279 #define RXLUT_RLADRCR_CMD_SHIFT (16U) 280 #define RXLUT_RLADRCR_CMD_WIDTH (1U) 281 #define RXLUT_RLADRCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLADRCR_CMD_SHIFT)) & RXLUT_RLADRCR_CMD_MASK) 282 /*! @} */ 283 284 /*! @name RLFIMESR - RXLUT Frame ID End Status */ 285 /*! @{ */ 286 287 #define RXLUT_RLFIMESR_FIMES_MASK (0xFFFFFFFFU) 288 #define RXLUT_RLFIMESR_FIMES_SHIFT (0U) 289 #define RXLUT_RLFIMESR_FIMES_WIDTH (32U) 290 #define RXLUT_RLFIMESR_FIMES(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLFIMESR_FIMES_SHIFT)) & RXLUT_RLFIMESR_FIMES_MASK) 291 /*! @} */ 292 293 /*! @name RLFISSR - RXLUT Frame ID Start Status */ 294 /*! @{ */ 295 296 #define RXLUT_RLFISSR_FISS_MASK (0xFFFFFFFFU) 297 #define RXLUT_RLFISSR_FISS_SHIFT (0U) 298 #define RXLUT_RLFISSR_FISS_WIDTH (32U) 299 #define RXLUT_RLFISSR_FISS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLFISSR_FISS_SHIFT)) & RXLUT_RLFISSR_FISS_MASK) 300 /*! @} */ 301 302 /*! @name RLCIXSR - RXLUT Channel ID AND Index Status */ 303 /*! @{ */ 304 305 #define RXLUT_RLCIXSR_ENABLE_MASK (0x2U) 306 #define RXLUT_RLCIXSR_ENABLE_SHIFT (1U) 307 #define RXLUT_RLCIXSR_ENABLE_WIDTH (1U) 308 #define RXLUT_RLCIXSR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXSR_ENABLE_SHIFT)) & RXLUT_RLCIXSR_ENABLE_MASK) 309 310 #define RXLUT_RLCIXSR_CIDS_MASK (0xFCU) 311 #define RXLUT_RLCIXSR_CIDS_SHIFT (2U) 312 #define RXLUT_RLCIXSR_CIDS_WIDTH (6U) 313 #define RXLUT_RLCIXSR_CIDS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXSR_CIDS_SHIFT)) & RXLUT_RLCIXSR_CIDS_MASK) 314 315 #define RXLUT_RLCIXSR_CTRLS_MASK (0x300U) 316 #define RXLUT_RLCIXSR_CTRLS_SHIFT (8U) 317 #define RXLUT_RLCIXSR_CTRLS_WIDTH (2U) 318 #define RXLUT_RLCIXSR_CTRLS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXSR_CTRLS_SHIFT)) & RXLUT_RLCIXSR_CTRLS_MASK) 319 320 #define RXLUT_RLCIXSR_INDXS_MASK (0xFFFF0000U) 321 #define RXLUT_RLCIXSR_INDXS_SHIFT (16U) 322 #define RXLUT_RLCIXSR_INDXS_WIDTH (16U) 323 #define RXLUT_RLCIXSR_INDXS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLCIXSR_INDXS_SHIFT)) & RXLUT_RLCIXSR_INDXS_MASK) 324 /*! @} */ 325 326 /*! @name RLADRSR - RXLUT Address Status */ 327 /*! @{ */ 328 329 #define RXLUT_RLADRSR_ADDRS_MASK (0xFFFFU) 330 #define RXLUT_RLADRSR_ADDRS_SHIFT (0U) 331 #define RXLUT_RLADRSR_ADDRS_WIDTH (16U) 332 #define RXLUT_RLADRSR_ADDRS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLADRSR_ADDRS_SHIFT)) & RXLUT_RLADRSR_ADDRS_MASK) 333 /*! @} */ 334 335 /*! @name RLSICR - RXLUT Search Input Command */ 336 /*! @{ */ 337 338 #define RXLUT_RLSICR_CID_MASK (0x3FU) 339 #define RXLUT_RLSICR_CID_SHIFT (0U) 340 #define RXLUT_RLSICR_CID_WIDTH (6U) 341 #define RXLUT_RLSICR_CID(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSICR_CID_SHIFT)) & RXLUT_RLSICR_CID_MASK) 342 343 #define RXLUT_RLSICR_SYNC_ID_MASK (0x3FFF0000U) 344 #define RXLUT_RLSICR_SYNC_ID_SHIFT (16U) 345 #define RXLUT_RLSICR_SYNC_ID_WIDTH (14U) 346 #define RXLUT_RLSICR_SYNC_ID(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSICR_SYNC_ID_SHIFT)) & RXLUT_RLSICR_SYNC_ID_MASK) 347 /*! @} */ 348 349 /*! @name RLSICFIR - RXLUT Search Input Command Frame ID */ 350 /*! @{ */ 351 352 #define RXLUT_RLSICFIR_FID_MASK (0xFFFFFFFFU) 353 #define RXLUT_RLSICFIR_FID_SHIFT (0U) 354 #define RXLUT_RLSICFIR_FID_WIDTH (32U) 355 #define RXLUT_RLSICFIR_FID(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSICFIR_FID_SHIFT)) & RXLUT_RLSICFIR_FID_MASK) 356 /*! @} */ 357 358 /*! @name RLSOIXR - RXLUT Search Output */ 359 /*! @{ */ 360 361 #define RXLUT_RLSOIXR_MS_MASK (0x1U) 362 #define RXLUT_RLSOIXR_MS_SHIFT (0U) 363 #define RXLUT_RLSOIXR_MS_WIDTH (1U) 364 #define RXLUT_RLSOIXR_MS(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOIXR_MS_SHIFT)) & RXLUT_RLSOIXR_MS_MASK) 365 366 #define RXLUT_RLSOIXR_ENABLE_MASK (0x2U) 367 #define RXLUT_RLSOIXR_ENABLE_SHIFT (1U) 368 #define RXLUT_RLSOIXR_ENABLE_WIDTH (1U) 369 #define RXLUT_RLSOIXR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOIXR_ENABLE_SHIFT)) & RXLUT_RLSOIXR_ENABLE_MASK) 370 371 #define RXLUT_RLSOIXR_SYNC_ID_MASK (0xFFFCU) 372 #define RXLUT_RLSOIXR_SYNC_ID_SHIFT (2U) 373 #define RXLUT_RLSOIXR_SYNC_ID_WIDTH (14U) 374 #define RXLUT_RLSOIXR_SYNC_ID(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOIXR_SYNC_ID_SHIFT)) & RXLUT_RLSOIXR_SYNC_ID_MASK) 375 376 #define RXLUT_RLSOIXR_IDX_MASK (0xFFFF0000U) 377 #define RXLUT_RLSOIXR_IDX_SHIFT (16U) 378 #define RXLUT_RLSOIXR_IDX_WIDTH (16U) 379 #define RXLUT_RLSOIXR_IDX(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOIXR_IDX_SHIFT)) & RXLUT_RLSOIXR_IDX_MASK) 380 /*! @} */ 381 382 /*! @name RLSOADR - RXLUT Search Output Address */ 383 /*! @{ */ 384 385 #define RXLUT_RLSOADR_ADR_MASK (0xFFFFU) 386 #define RXLUT_RLSOADR_ADR_SHIFT (0U) 387 #define RXLUT_RLSOADR_ADR_WIDTH (16U) 388 #define RXLUT_RLSOADR_ADR(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOADR_ADR_SHIFT)) & RXLUT_RLSOADR_ADR_MASK) 389 /*! @} */ 390 391 /*! @name RLSICFSR - RXLUT Search Input Command FIFO Status */ 392 /*! @{ */ 393 394 #define RXLUT_RLSICFSR_EMPTY_MASK (0x1U) 395 #define RXLUT_RLSICFSR_EMPTY_SHIFT (0U) 396 #define RXLUT_RLSICFSR_EMPTY_WIDTH (1U) 397 #define RXLUT_RLSICFSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSICFSR_EMPTY_SHIFT)) & RXLUT_RLSICFSR_EMPTY_MASK) 398 399 #define RXLUT_RLSICFSR_FULL_MASK (0x2U) 400 #define RXLUT_RLSICFSR_FULL_SHIFT (1U) 401 #define RXLUT_RLSICFSR_FULL_WIDTH (1U) 402 #define RXLUT_RLSICFSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSICFSR_FULL_SHIFT)) & RXLUT_RLSICFSR_FULL_MASK) 403 /*! @} */ 404 405 /*! @name RLSOFSR - RXLUT Search Output FIFO Status */ 406 /*! @{ */ 407 408 #define RXLUT_RLSOFSR_EMPTY0_MASK (0x1U) 409 #define RXLUT_RLSOFSR_EMPTY0_SHIFT (0U) 410 #define RXLUT_RLSOFSR_EMPTY0_WIDTH (1U) 411 #define RXLUT_RLSOFSR_EMPTY0(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY0_SHIFT)) & RXLUT_RLSOFSR_EMPTY0_MASK) 412 413 #define RXLUT_RLSOFSR_FULL0_MASK (0x2U) 414 #define RXLUT_RLSOFSR_FULL0_SHIFT (1U) 415 #define RXLUT_RLSOFSR_FULL0_WIDTH (1U) 416 #define RXLUT_RLSOFSR_FULL0(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL0_SHIFT)) & RXLUT_RLSOFSR_FULL0_MASK) 417 418 #define RXLUT_RLSOFSR_EMPTY1_MASK (0x10U) 419 #define RXLUT_RLSOFSR_EMPTY1_SHIFT (4U) 420 #define RXLUT_RLSOFSR_EMPTY1_WIDTH (1U) 421 #define RXLUT_RLSOFSR_EMPTY1(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY1_SHIFT)) & RXLUT_RLSOFSR_EMPTY1_MASK) 422 423 #define RXLUT_RLSOFSR_FULL1_MASK (0x20U) 424 #define RXLUT_RLSOFSR_FULL1_SHIFT (5U) 425 #define RXLUT_RLSOFSR_FULL1_WIDTH (1U) 426 #define RXLUT_RLSOFSR_FULL1(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL1_SHIFT)) & RXLUT_RLSOFSR_FULL1_MASK) 427 428 #define RXLUT_RLSOFSR_EMPTY2_MASK (0x100U) 429 #define RXLUT_RLSOFSR_EMPTY2_SHIFT (8U) 430 #define RXLUT_RLSOFSR_EMPTY2_WIDTH (1U) 431 #define RXLUT_RLSOFSR_EMPTY2(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY2_SHIFT)) & RXLUT_RLSOFSR_EMPTY2_MASK) 432 433 #define RXLUT_RLSOFSR_FULL2_MASK (0x200U) 434 #define RXLUT_RLSOFSR_FULL2_SHIFT (9U) 435 #define RXLUT_RLSOFSR_FULL2_WIDTH (1U) 436 #define RXLUT_RLSOFSR_FULL2(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL2_SHIFT)) & RXLUT_RLSOFSR_FULL2_MASK) 437 438 #define RXLUT_RLSOFSR_EMPTY3_MASK (0x1000U) 439 #define RXLUT_RLSOFSR_EMPTY3_SHIFT (12U) 440 #define RXLUT_RLSOFSR_EMPTY3_WIDTH (1U) 441 #define RXLUT_RLSOFSR_EMPTY3(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY3_SHIFT)) & RXLUT_RLSOFSR_EMPTY3_MASK) 442 443 #define RXLUT_RLSOFSR_FULL3_MASK (0x2000U) 444 #define RXLUT_RLSOFSR_FULL3_SHIFT (13U) 445 #define RXLUT_RLSOFSR_FULL3_WIDTH (1U) 446 #define RXLUT_RLSOFSR_FULL3(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL3_SHIFT)) & RXLUT_RLSOFSR_FULL3_MASK) 447 448 #define RXLUT_RLSOFSR_EMPTY4_MASK (0x10000U) 449 #define RXLUT_RLSOFSR_EMPTY4_SHIFT (16U) 450 #define RXLUT_RLSOFSR_EMPTY4_WIDTH (1U) 451 #define RXLUT_RLSOFSR_EMPTY4(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY4_SHIFT)) & RXLUT_RLSOFSR_EMPTY4_MASK) 452 453 #define RXLUT_RLSOFSR_FULL4_MASK (0x20000U) 454 #define RXLUT_RLSOFSR_FULL4_SHIFT (17U) 455 #define RXLUT_RLSOFSR_FULL4_WIDTH (1U) 456 #define RXLUT_RLSOFSR_FULL4(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL4_SHIFT)) & RXLUT_RLSOFSR_FULL4_MASK) 457 458 #define RXLUT_RLSOFSR_EMPTY5_MASK (0x100000U) 459 #define RXLUT_RLSOFSR_EMPTY5_SHIFT (20U) 460 #define RXLUT_RLSOFSR_EMPTY5_WIDTH (1U) 461 #define RXLUT_RLSOFSR_EMPTY5(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY5_SHIFT)) & RXLUT_RLSOFSR_EMPTY5_MASK) 462 463 #define RXLUT_RLSOFSR_FULL5_MASK (0x200000U) 464 #define RXLUT_RLSOFSR_FULL5_SHIFT (21U) 465 #define RXLUT_RLSOFSR_FULL5_WIDTH (1U) 466 #define RXLUT_RLSOFSR_FULL5(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL5_SHIFT)) & RXLUT_RLSOFSR_FULL5_MASK) 467 468 #define RXLUT_RLSOFSR_EMPTY6_MASK (0x1000000U) 469 #define RXLUT_RLSOFSR_EMPTY6_SHIFT (24U) 470 #define RXLUT_RLSOFSR_EMPTY6_WIDTH (1U) 471 #define RXLUT_RLSOFSR_EMPTY6(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY6_SHIFT)) & RXLUT_RLSOFSR_EMPTY6_MASK) 472 473 #define RXLUT_RLSOFSR_FULL6_MASK (0x2000000U) 474 #define RXLUT_RLSOFSR_FULL6_SHIFT (25U) 475 #define RXLUT_RLSOFSR_FULL6_WIDTH (1U) 476 #define RXLUT_RLSOFSR_FULL6(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL6_SHIFT)) & RXLUT_RLSOFSR_FULL6_MASK) 477 478 #define RXLUT_RLSOFSR_EMPTY7_MASK (0x10000000U) 479 #define RXLUT_RLSOFSR_EMPTY7_SHIFT (28U) 480 #define RXLUT_RLSOFSR_EMPTY7_WIDTH (1U) 481 #define RXLUT_RLSOFSR_EMPTY7(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY7_SHIFT)) & RXLUT_RLSOFSR_EMPTY7_MASK) 482 483 #define RXLUT_RLSOFSR_FULL7_MASK (0x20000000U) 484 #define RXLUT_RLSOFSR_FULL7_SHIFT (29U) 485 #define RXLUT_RLSOFSR_FULL7_WIDTH (1U) 486 #define RXLUT_RLSOFSR_FULL7(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL7_SHIFT)) & RXLUT_RLSOFSR_FULL7_MASK) 487 488 #define RXLUT_RLSOFSR_EMPTY8_MASK (0x1U) 489 #define RXLUT_RLSOFSR_EMPTY8_SHIFT (0U) 490 #define RXLUT_RLSOFSR_EMPTY8_WIDTH (1U) 491 #define RXLUT_RLSOFSR_EMPTY8(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY8_SHIFT)) & RXLUT_RLSOFSR_EMPTY8_MASK) 492 493 #define RXLUT_RLSOFSR_FULL8_MASK (0x2U) 494 #define RXLUT_RLSOFSR_FULL8_SHIFT (1U) 495 #define RXLUT_RLSOFSR_FULL8_WIDTH (1U) 496 #define RXLUT_RLSOFSR_FULL8(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL8_SHIFT)) & RXLUT_RLSOFSR_FULL8_MASK) 497 498 #define RXLUT_RLSOFSR_EMPTY9_MASK (0x10U) 499 #define RXLUT_RLSOFSR_EMPTY9_SHIFT (4U) 500 #define RXLUT_RLSOFSR_EMPTY9_WIDTH (1U) 501 #define RXLUT_RLSOFSR_EMPTY9(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY9_SHIFT)) & RXLUT_RLSOFSR_EMPTY9_MASK) 502 503 #define RXLUT_RLSOFSR_FULL9_MASK (0x20U) 504 #define RXLUT_RLSOFSR_FULL9_SHIFT (5U) 505 #define RXLUT_RLSOFSR_FULL9_WIDTH (1U) 506 #define RXLUT_RLSOFSR_FULL9(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL9_SHIFT)) & RXLUT_RLSOFSR_FULL9_MASK) 507 508 #define RXLUT_RLSOFSR_EMPTY10_MASK (0x100U) 509 #define RXLUT_RLSOFSR_EMPTY10_SHIFT (8U) 510 #define RXLUT_RLSOFSR_EMPTY10_WIDTH (1U) 511 #define RXLUT_RLSOFSR_EMPTY10(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY10_SHIFT)) & RXLUT_RLSOFSR_EMPTY10_MASK) 512 513 #define RXLUT_RLSOFSR_FULL10_MASK (0x200U) 514 #define RXLUT_RLSOFSR_FULL10_SHIFT (9U) 515 #define RXLUT_RLSOFSR_FULL10_WIDTH (1U) 516 #define RXLUT_RLSOFSR_FULL10(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL10_SHIFT)) & RXLUT_RLSOFSR_FULL10_MASK) 517 518 #define RXLUT_RLSOFSR_EMPTY11_MASK (0x1000U) 519 #define RXLUT_RLSOFSR_EMPTY11_SHIFT (12U) 520 #define RXLUT_RLSOFSR_EMPTY11_WIDTH (1U) 521 #define RXLUT_RLSOFSR_EMPTY11(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_EMPTY11_SHIFT)) & RXLUT_RLSOFSR_EMPTY11_MASK) 522 523 #define RXLUT_RLSOFSR_FULL11_MASK (0x2000U) 524 #define RXLUT_RLSOFSR_FULL11_SHIFT (13U) 525 #define RXLUT_RLSOFSR_FULL11_WIDTH (1U) 526 #define RXLUT_RLSOFSR_FULL11(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLSOFSR_FULL11_SHIFT)) & RXLUT_RLSOFSR_FULL11_MASK) 527 /*! @} */ 528 529 /*! @name RLICEC - RXLUT Input Command Entry Counter */ 530 /*! @{ */ 531 532 #define RXLUT_RLICEC_CNTR0_MASK (0xFU) 533 #define RXLUT_RLICEC_CNTR0_SHIFT (0U) 534 #define RXLUT_RLICEC_CNTR0_WIDTH (4U) 535 #define RXLUT_RLICEC_CNTR0(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR0_SHIFT)) & RXLUT_RLICEC_CNTR0_MASK) 536 537 #define RXLUT_RLICEC_CNTR1_MASK (0xF0U) 538 #define RXLUT_RLICEC_CNTR1_SHIFT (4U) 539 #define RXLUT_RLICEC_CNTR1_WIDTH (4U) 540 #define RXLUT_RLICEC_CNTR1(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR1_SHIFT)) & RXLUT_RLICEC_CNTR1_MASK) 541 542 #define RXLUT_RLICEC_CNTR2_MASK (0xF00U) 543 #define RXLUT_RLICEC_CNTR2_SHIFT (8U) 544 #define RXLUT_RLICEC_CNTR2_WIDTH (4U) 545 #define RXLUT_RLICEC_CNTR2(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR2_SHIFT)) & RXLUT_RLICEC_CNTR2_MASK) 546 547 #define RXLUT_RLICEC_CNTR3_MASK (0xF000U) 548 #define RXLUT_RLICEC_CNTR3_SHIFT (12U) 549 #define RXLUT_RLICEC_CNTR3_WIDTH (4U) 550 #define RXLUT_RLICEC_CNTR3(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR3_SHIFT)) & RXLUT_RLICEC_CNTR3_MASK) 551 552 #define RXLUT_RLICEC_CNTR4_MASK (0xF0000U) 553 #define RXLUT_RLICEC_CNTR4_SHIFT (16U) 554 #define RXLUT_RLICEC_CNTR4_WIDTH (4U) 555 #define RXLUT_RLICEC_CNTR4(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR4_SHIFT)) & RXLUT_RLICEC_CNTR4_MASK) 556 557 #define RXLUT_RLICEC_CNTR5_MASK (0xF00000U) 558 #define RXLUT_RLICEC_CNTR5_SHIFT (20U) 559 #define RXLUT_RLICEC_CNTR5_WIDTH (4U) 560 #define RXLUT_RLICEC_CNTR5(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR5_SHIFT)) & RXLUT_RLICEC_CNTR5_MASK) 561 562 #define RXLUT_RLICEC_CNTR6_MASK (0xF000000U) 563 #define RXLUT_RLICEC_CNTR6_SHIFT (24U) 564 #define RXLUT_RLICEC_CNTR6_WIDTH (4U) 565 #define RXLUT_RLICEC_CNTR6(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR6_SHIFT)) & RXLUT_RLICEC_CNTR6_MASK) 566 567 #define RXLUT_RLICEC_CNTR7_MASK (0xF0000000U) 568 #define RXLUT_RLICEC_CNTR7_SHIFT (28U) 569 #define RXLUT_RLICEC_CNTR7_WIDTH (4U) 570 #define RXLUT_RLICEC_CNTR7(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR7_SHIFT)) & RXLUT_RLICEC_CNTR7_MASK) 571 572 #define RXLUT_RLICEC_CNTR8_MASK (0xFU) 573 #define RXLUT_RLICEC_CNTR8_SHIFT (0U) 574 #define RXLUT_RLICEC_CNTR8_WIDTH (4U) 575 #define RXLUT_RLICEC_CNTR8(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR8_SHIFT)) & RXLUT_RLICEC_CNTR8_MASK) 576 577 #define RXLUT_RLICEC_CNTR9_MASK (0xF0U) 578 #define RXLUT_RLICEC_CNTR9_SHIFT (4U) 579 #define RXLUT_RLICEC_CNTR9_WIDTH (4U) 580 #define RXLUT_RLICEC_CNTR9(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR9_SHIFT)) & RXLUT_RLICEC_CNTR9_MASK) 581 582 #define RXLUT_RLICEC_CNTR10_MASK (0xF00U) 583 #define RXLUT_RLICEC_CNTR10_SHIFT (8U) 584 #define RXLUT_RLICEC_CNTR10_WIDTH (4U) 585 #define RXLUT_RLICEC_CNTR10(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR10_SHIFT)) & RXLUT_RLICEC_CNTR10_MASK) 586 587 #define RXLUT_RLICEC_CNTR11_MASK (0xF000U) 588 #define RXLUT_RLICEC_CNTR11_SHIFT (12U) 589 #define RXLUT_RLICEC_CNTR11_WIDTH (4U) 590 #define RXLUT_RLICEC_CNTR11(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLICEC_CNTR11_SHIFT)) & RXLUT_RLICEC_CNTR11_MASK) 591 /*! @} */ 592 593 /*! @name RLER - RXLUT Error */ 594 /*! @{ */ 595 596 #define RXLUT_RLER_SBIT_MASK (0x1U) 597 #define RXLUT_RLER_SBIT_SHIFT (0U) 598 #define RXLUT_RLER_SBIT_WIDTH (1U) 599 #define RXLUT_RLER_SBIT(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLER_SBIT_SHIFT)) & RXLUT_RLER_SBIT_MASK) 600 601 #define RXLUT_RLER_MBIT_MASK (0x10000U) 602 #define RXLUT_RLER_MBIT_SHIFT (16U) 603 #define RXLUT_RLER_MBIT_WIDTH (1U) 604 #define RXLUT_RLER_MBIT(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLER_MBIT_SHIFT)) & RXLUT_RLER_MBIT_MASK) 605 /*! @} */ 606 607 /*! @name RLOOR - RXLUT Output Overflow */ 608 /*! @{ */ 609 610 #define RXLUT_RLOOR_LOR_MASK (0xFFFU) 611 #define RXLUT_RLOOR_LOR_SHIFT (0U) 612 #define RXLUT_RLOOR_LOR_WIDTH (12U) 613 #define RXLUT_RLOOR_LOR(x) (((uint32_t)(((uint32_t)(x)) << RXLUT_RLOOR_LOR_SHIFT)) & RXLUT_RLOOR_LOR_MASK) 614 /*! @} */ 615 616 /*! 617 * @} 618 */ /* end of group RXLUT_Register_Masks */ 619 620 /*! 621 * @} 622 */ /* end of group RXLUT_Peripheral_Access_Layer */ 623 624 #endif /* #if !defined(S32Z2_RXLUT_H_) */ 625
