1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ROUND_ROBIN_ARBITER.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ROUND_ROBIN_ARBITER 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ROUND_ROBIN_ARBITER_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ROUND_ROBIN_ARBITER_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ROUND_ROBIN_ARBITER Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ROUND_ROBIN_ARBITER_Peripheral_Access_Layer ROUND_ROBIN_ARBITER Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ROUND_ROBIN_ARBITER - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t RRA_SLT_LO; /**< RRA Slot LO Register, offset: 0x0 */ 74 __IO uint32_t RRA_SLT_HI; /**< RRA Slot HI Register, offset: 0x4 */ 75 __IO uint32_t RRA_SLT_PRI; /**< RRA Slot Priority Register, offset: 0x8 */ 76 __IO uint32_t RRA_WEIGHT_LO; /**< RRA Weight LO Register, offset: 0xC */ 77 __IO uint32_t RRA_WEIGHT_HI; /**< RRA Weight HI Register, offset: 0x10 */ 78 } ROUND_ROBIN_ARBITER_Type, *ROUND_ROBIN_ARBITER_MemMapPtr; 79 80 /** Number of instances of the ROUND_ROBIN_ARBITER module. */ 81 #define ROUND_ROBIN_ARBITER_INSTANCE_COUNT (1u) 82 83 /* ROUND_ROBIN_ARBITER - Peripheral instance base addresses */ 84 /** Peripheral CEVA_SPF2__ROUND_ROBIN_ARBITER base address */ 85 #define IP_CEVA_SPF2__ROUND_ROBIN_ARBITER_BASE (0x24400FA0u) 86 /** Peripheral CEVA_SPF2__ROUND_ROBIN_ARBITER base pointer */ 87 #define IP_CEVA_SPF2__ROUND_ROBIN_ARBITER ((ROUND_ROBIN_ARBITER_Type *)IP_CEVA_SPF2__ROUND_ROBIN_ARBITER_BASE) 88 /** Array initializer of ROUND_ROBIN_ARBITER peripheral base addresses */ 89 #define IP_ROUND_ROBIN_ARBITER_BASE_ADDRS { IP_CEVA_SPF2__ROUND_ROBIN_ARBITER_BASE } 90 /** Array initializer of ROUND_ROBIN_ARBITER peripheral base pointers */ 91 #define IP_ROUND_ROBIN_ARBITER_BASE_PTRS { IP_CEVA_SPF2__ROUND_ROBIN_ARBITER } 92 93 /* ---------------------------------------------------------------------------- 94 -- ROUND_ROBIN_ARBITER Register Masks 95 ---------------------------------------------------------------------------- */ 96 97 /*! 98 * @addtogroup ROUND_ROBIN_ARBITER_Register_Masks ROUND_ROBIN_ARBITER Register Masks 99 * @{ 100 */ 101 102 /*! @name RRA_SLT_LO - RRA Slot LO Register */ 103 /*! @{ */ 104 105 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT0_REQM_MASK (0xFU) 106 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT0_REQM_SHIFT (0U) 107 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT0_REQM_WIDTH (4U) 108 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT0_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT0_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT0_REQM_MASK) 109 110 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT1_REQM_MASK (0xF0U) 111 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT1_REQM_SHIFT (4U) 112 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT1_REQM_WIDTH (4U) 113 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT1_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT1_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT1_REQM_MASK) 114 115 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT2_REQM_MASK (0xF00U) 116 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT2_REQM_SHIFT (8U) 117 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT2_REQM_WIDTH (4U) 118 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT2_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT2_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT2_REQM_MASK) 119 120 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT3_REQM_MASK (0xF000U) 121 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT3_REQM_SHIFT (12U) 122 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT3_REQM_WIDTH (4U) 123 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT3_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT3_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT3_REQM_MASK) 124 125 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT4_REQM_MASK (0xF0000U) 126 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT4_REQM_SHIFT (16U) 127 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT4_REQM_WIDTH (4U) 128 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT4_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT4_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT4_REQM_MASK) 129 130 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT5_REQM_MASK (0xF00000U) 131 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT5_REQM_SHIFT (20U) 132 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT5_REQM_WIDTH (4U) 133 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT5_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT5_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT5_REQM_MASK) 134 135 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT6_REQM_MASK (0xF000000U) 136 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT6_REQM_SHIFT (24U) 137 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT6_REQM_WIDTH (4U) 138 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT6_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT6_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT6_REQM_MASK) 139 140 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT7_REQM_MASK (0xF0000000U) 141 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT7_REQM_SHIFT (28U) 142 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT7_REQM_WIDTH (4U) 143 #define ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT7_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT7_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_LO_SLOT7_REQM_MASK) 144 /*! @} */ 145 146 /*! @name RRA_SLT_HI - RRA Slot HI Register */ 147 /*! @{ */ 148 149 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT8_REQM_MASK (0xFU) 150 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT8_REQM_SHIFT (0U) 151 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT8_REQM_WIDTH (4U) 152 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT8_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT8_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT8_REQM_MASK) 153 154 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT9_REQM_MASK (0xF0U) 155 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT9_REQM_SHIFT (4U) 156 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT9_REQM_WIDTH (4U) 157 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT9_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT9_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT9_REQM_MASK) 158 159 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT10_REQM_MASK (0xF00U) 160 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT10_REQM_SHIFT (8U) 161 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT10_REQM_WIDTH (4U) 162 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT10_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT10_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT10_REQM_MASK) 163 164 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT11_REQM_MASK (0xF000U) 165 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT11_REQM_SHIFT (12U) 166 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT11_REQM_WIDTH (4U) 167 #define ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT11_REQM(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT11_REQM_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_HI_SLOT11_REQM_MASK) 168 /*! @} */ 169 170 /*! @name RRA_SLT_PRI - RRA Slot Priority Register */ 171 /*! @{ */ 172 173 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION1_FIRST_SLOT_MASK (0xFU) 174 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION1_FIRST_SLOT_SHIFT (0U) 175 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION1_FIRST_SLOT_WIDTH (4U) 176 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION1_FIRST_SLOT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION1_FIRST_SLOT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION1_FIRST_SLOT_MASK) 177 178 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION2_FIRST_SLOT_MASK (0xF0U) 179 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION2_FIRST_SLOT_SHIFT (4U) 180 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION2_FIRST_SLOT_WIDTH (4U) 181 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION2_FIRST_SLOT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION2_FIRST_SLOT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION2_FIRST_SLOT_MASK) 182 183 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION3_FIRST_SLOT_MASK (0xF00U) 184 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION3_FIRST_SLOT_SHIFT (8U) 185 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION3_FIRST_SLOT_WIDTH (4U) 186 #define ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION3_FIRST_SLOT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION3_FIRST_SLOT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_SLT_PRI_RRA_RGION3_FIRST_SLOT_MASK) 187 /*! @} */ 188 189 /*! @name RRA_WEIGHT_LO - RRA Weight LO Register */ 190 /*! @{ */ 191 192 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_DDMA_RD_WEIGHT_MASK (0x7U) 193 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_DDMA_RD_WEIGHT_SHIFT (0U) 194 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_DDMA_RD_WEIGHT_WIDTH (3U) 195 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_DDMA_RD_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_DDMA_RD_WEIGHT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_DDMA_RD_WEIGHT_MASK) 196 197 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_EDAP_RD_WEIGHT_MASK (0x70U) 198 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_EDAP_RD_WEIGHT_SHIFT (4U) 199 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_EDAP_RD_WEIGHT_WIDTH (3U) 200 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_EDAP_RD_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_EDAP_RD_WEIGHT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_EDAP_RD_WEIGHT_MASK) 201 202 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_QMAN_WEIGHT_MASK (0x700U) 203 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_QMAN_WEIGHT_SHIFT (8U) 204 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_QMAN_WEIGHT_WIDTH (3U) 205 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_QMAN_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_QMAN_WEIGHT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_WEIGHT_LO_QMAN_WEIGHT_MASK) 206 /*! @} */ 207 208 /*! @name RRA_WEIGHT_HI - RRA Weight HI Register */ 209 /*! @{ */ 210 211 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_DDMA_WR_WEIGHT_MASK (0x70U) 212 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_DDMA_WR_WEIGHT_SHIFT (4U) 213 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_DDMA_WR_WEIGHT_WIDTH (3U) 214 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_DDMA_WR_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_DDMA_WR_WEIGHT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_DDMA_WR_WEIGHT_MASK) 215 216 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_EDAP_WR_WEIGHT_MASK (0x7000U) 217 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_EDAP_WR_WEIGHT_SHIFT (12U) 218 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_EDAP_WR_WEIGHT_WIDTH (3U) 219 #define ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_EDAP_WR_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_EDAP_WR_WEIGHT_SHIFT)) & ROUND_ROBIN_ARBITER_RRA_WEIGHT_HI_EDAP_WR_WEIGHT_MASK) 220 /*! @} */ 221 222 /*! 223 * @} 224 */ /* end of group ROUND_ROBIN_ARBITER_Register_Masks */ 225 226 /*! 227 * @} 228 */ /* end of group ROUND_ROBIN_ARBITER_Peripheral_Access_Layer */ 229 230 #endif /* #if !defined(S32Z2_ROUND_ROBIN_ARBITER_H_) */ 231
