1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RDC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_RDC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RDC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RDC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RDC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RDC - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[4]; 74 __IO uint32_t RD1_CTRL_REG; /**< Software Reset Domain Control, offset: 0x4 */ 75 uint8_t RESERVED_1[124]; 76 __I uint32_t RD1_STAT_REG; /**< Software Reset Domain Status, offset: 0x84 */ 77 } RDC_Type, *RDC_MemMapPtr; 78 79 /** Number of instances of the RDC module. */ 80 #define RDC_INSTANCE_COUNT (2u) 81 82 /* RDC - Peripheral instance base addresses */ 83 /** Peripheral RDC_0 base address */ 84 #define IP_RDC_0_BASE (0x41890000u) 85 /** Peripheral RDC_0 base pointer */ 86 #define IP_RDC_0 ((RDC_Type *)IP_RDC_0_BASE) 87 /** Peripheral RDC_1 base address */ 88 #define IP_RDC_1_BASE (0x418A0000u) 89 /** Peripheral RDC_1 base pointer */ 90 #define IP_RDC_1 ((RDC_Type *)IP_RDC_1_BASE) 91 /** Array initializer of RDC peripheral base addresses */ 92 #define IP_RDC_BASE_ADDRS { IP_RDC_0_BASE, IP_RDC_1_BASE } 93 /** Array initializer of RDC peripheral base pointers */ 94 #define IP_RDC_BASE_PTRS { IP_RDC_0, IP_RDC_1 } 95 96 /* ---------------------------------------------------------------------------- 97 -- RDC Register Masks 98 ---------------------------------------------------------------------------- */ 99 100 /*! 101 * @addtogroup RDC_Register_Masks RDC Register Masks 102 * @{ 103 */ 104 105 /*! @name RD1_CTRL_REG - Software Reset Domain Control */ 106 /*! @{ */ 107 108 #define RDC_RD1_CTRL_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_MASK (0x8U) 109 #define RDC_RD1_CTRL_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_SHIFT (3U) 110 #define RDC_RD1_CTRL_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_WIDTH (1U) 111 #define RDC_RD1_CTRL_REG_RD1_INTERCONNECT_INTERFACE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << RDC_RD1_CTRL_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_SHIFT)) & RDC_RD1_CTRL_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_MASK) 112 113 #define RDC_RD1_CTRL_REG_RD1_CTRL_UNLOCK_MASK (0x80000000U) 114 #define RDC_RD1_CTRL_REG_RD1_CTRL_UNLOCK_SHIFT (31U) 115 #define RDC_RD1_CTRL_REG_RD1_CTRL_UNLOCK_WIDTH (1U) 116 #define RDC_RD1_CTRL_REG_RD1_CTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_RD1_CTRL_REG_RD1_CTRL_UNLOCK_SHIFT)) & RDC_RD1_CTRL_REG_RD1_CTRL_UNLOCK_MASK) 117 /*! @} */ 118 119 /*! @name RD1_STAT_REG - Software Reset Domain Status */ 120 /*! @{ */ 121 122 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT_MASK (0x8U) 123 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT_SHIFT (3U) 124 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT_WIDTH (1U) 125 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT_SHIFT)) & RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT_MASK) 126 127 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_STAT_MASK (0x10U) 128 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_STAT_SHIFT (4U) 129 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_STAT_WIDTH (1U) 130 #define RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_STAT(x) (((uint32_t)(((uint32_t)(x)) << RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_STAT_SHIFT)) & RDC_RD1_STAT_REG_RD1_INTERCONNECT_INTERFACE_DISABLE_STAT_MASK) 131 /*! @} */ 132 133 /*! 134 * @} 135 */ /* end of group RDC_Register_Masks */ 136 137 /*! 138 * @} 139 */ /* end of group RDC_Peripheral_Access_Layer */ 140 141 #endif /* #if !defined(S32Z2_RDC_H_) */ 142
