1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_PMSS_SAFETY.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_PMSS_SAFETY 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_PMSS_SAFETY_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_PMSS_SAFETY_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PMSS_SAFETY Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PMSS_SAFETY_Peripheral_Access_Layer PMSS_SAFETY Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PMSS_SAFETY - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t P_UCSERR; /**< PMSS UCS ERR Register, offset: 0x0 */ 74 uint8_t RESERVED_0[4]; 75 __IO uint32_t P_CSERR; /**< PMSS CS ERR Register, offset: 0x8 */ 76 uint8_t RESERVED_1[4]; 77 __O uint32_t P_UCSERR_S; /**< PMSS UCS ERR Shadow Register, offset: 0x10 */ 78 __O uint32_t P_CSERR_S; /**< PMSS CE ERR Shadow Register, offset: 0x14 */ 79 uint8_t RESERVED_2[4]; 80 __IO uint32_t P_CSERR_M; /**< PMSS CS ERR Mask Register, offset: 0x1C */ 81 uint8_t RESERVED_3[16]; 82 __IO uint32_t P_ECC_TCFG; /**< PMSS ECC TCFG Register, offset: 0x30 */ 83 __IO uint32_t P_ECC_TCFG_2; /**< PMSS ECC TCFG 2 Register, offset: 0x34 */ 84 uint8_t RESERVED_4[8]; 85 __IO uint32_t P_CTECC_TCFG; /**< PMSS CT ECC TCFG Register, offset: 0x40 */ 86 uint8_t RESERVED_5[12]; 87 __IO uint32_t P_BTBECC_TCFG; /**< PMSS BTB ECC TCFG Register, offset: 0x50 */ 88 uint8_t RESERVED_6[28]; 89 __I uint32_t P_UCSERR_CNT; /**< PMSS UCSERR CNT Register, offset: 0x70 */ 90 __I uint32_t P_CSERR_CNT; /**< PMSS CSERR CNT Register, offset: 0x74 */ 91 __IO uint32_t P_LPCS; /**< PMSS LPCS Register, offset: 0x78 */ 92 } PMSS_SAFETY_Type, *PMSS_SAFETY_MemMapPtr; 93 94 /** Number of instances of the PMSS_SAFETY module. */ 95 #define PMSS_SAFETY_INSTANCE_COUNT (1u) 96 97 /* PMSS_SAFETY - Peripheral instance base addresses */ 98 /** Peripheral CEVA_SPF2__PMSS_SAFETY base address */ 99 #define IP_CEVA_SPF2__PMSS_SAFETY_BASE (0x24400580u) 100 /** Peripheral CEVA_SPF2__PMSS_SAFETY base pointer */ 101 #define IP_CEVA_SPF2__PMSS_SAFETY ((PMSS_SAFETY_Type *)IP_CEVA_SPF2__PMSS_SAFETY_BASE) 102 /** Array initializer of PMSS_SAFETY peripheral base addresses */ 103 #define IP_PMSS_SAFETY_BASE_ADDRS { IP_CEVA_SPF2__PMSS_SAFETY_BASE } 104 /** Array initializer of PMSS_SAFETY peripheral base pointers */ 105 #define IP_PMSS_SAFETY_BASE_PTRS { IP_CEVA_SPF2__PMSS_SAFETY } 106 107 /* ---------------------------------------------------------------------------- 108 -- PMSS_SAFETY Register Masks 109 ---------------------------------------------------------------------------- */ 110 111 /*! 112 * @addtogroup PMSS_SAFETY_Register_Masks PMSS_SAFETY Register Masks 113 * @{ 114 */ 115 116 /*! @name P_UCSERR - PMSS UCS ERR Register */ 117 /*! @{ */ 118 119 #define PMSS_SAFETY_P_UCSERR_P_UCSERR_MASK (0x1U) 120 #define PMSS_SAFETY_P_UCSERR_P_UCSERR_SHIFT (0U) 121 #define PMSS_SAFETY_P_UCSERR_P_UCSERR_WIDTH (1U) 122 #define PMSS_SAFETY_P_UCSERR_P_UCSERR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_P_UCSERR_SHIFT)) & PMSS_SAFETY_P_UCSERR_P_UCSERR_MASK) 123 124 #define PMSS_SAFETY_P_UCSERR_P_CORE_PERR_MASK (0x20U) 125 #define PMSS_SAFETY_P_UCSERR_P_CORE_PERR_SHIFT (5U) 126 #define PMSS_SAFETY_P_UCSERR_P_CORE_PERR_WIDTH (1U) 127 #define PMSS_SAFETY_P_UCSERR_P_CORE_PERR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_P_CORE_PERR_SHIFT)) & PMSS_SAFETY_P_UCSERR_P_CORE_PERR_MASK) 128 129 #define PMSS_SAFETY_P_UCSERR_P_MSS_PERR_MASK (0x40U) 130 #define PMSS_SAFETY_P_UCSERR_P_MSS_PERR_SHIFT (6U) 131 #define PMSS_SAFETY_P_UCSERR_P_MSS_PERR_WIDTH (1U) 132 #define PMSS_SAFETY_P_UCSERR_P_MSS_PERR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_P_MSS_PERR_SHIFT)) & PMSS_SAFETY_P_UCSERR_P_MSS_PERR_MASK) 133 134 #define PMSS_SAFETY_P_UCSERR_P_UCECNTEV_MASK (0x10000U) 135 #define PMSS_SAFETY_P_UCSERR_P_UCECNTEV_SHIFT (16U) 136 #define PMSS_SAFETY_P_UCSERR_P_UCECNTEV_WIDTH (1U) 137 #define PMSS_SAFETY_P_UCSERR_P_UCECNTEV(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_P_UCECNTEV_SHIFT)) & PMSS_SAFETY_P_UCSERR_P_UCECNTEV_MASK) 138 139 #define PMSS_SAFETY_P_UCSERR_P_UCECNTOV_MASK (0x20000U) 140 #define PMSS_SAFETY_P_UCSERR_P_UCECNTOV_SHIFT (17U) 141 #define PMSS_SAFETY_P_UCSERR_P_UCECNTOV_WIDTH (1U) 142 #define PMSS_SAFETY_P_UCSERR_P_UCECNTOV(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_P_UCECNTOV_SHIFT)) & PMSS_SAFETY_P_UCSERR_P_UCECNTOV_MASK) 143 /*! @} */ 144 145 /*! @name P_CSERR - PMSS CS ERR Register */ 146 /*! @{ */ 147 148 #define PMSS_SAFETY_P_CSERR_P_CSERR_MASK (0x1U) 149 #define PMSS_SAFETY_P_CSERR_P_CSERR_SHIFT (0U) 150 #define PMSS_SAFETY_P_CSERR_P_CSERR_WIDTH (1U) 151 #define PMSS_SAFETY_P_CSERR_P_CSERR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_P_CSERR_SHIFT)) & PMSS_SAFETY_P_CSERR_P_CSERR_MASK) 152 153 #define PMSS_SAFETY_P_CSERR_P_ECC_COR_MASK (0x2U) 154 #define PMSS_SAFETY_P_CSERR_P_ECC_COR_SHIFT (1U) 155 #define PMSS_SAFETY_P_CSERR_P_ECC_COR_WIDTH (1U) 156 #define PMSS_SAFETY_P_CSERR_P_ECC_COR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_P_ECC_COR_SHIFT)) & PMSS_SAFETY_P_CSERR_P_ECC_COR_MASK) 157 158 #define PMSS_SAFETY_P_CSERR_P_CTECC_COR_MASK (0x4U) 159 #define PMSS_SAFETY_P_CSERR_P_CTECC_COR_SHIFT (2U) 160 #define PMSS_SAFETY_P_CSERR_P_CTECC_COR_WIDTH (1U) 161 #define PMSS_SAFETY_P_CSERR_P_CTECC_COR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_P_CTECC_COR_SHIFT)) & PMSS_SAFETY_P_CSERR_P_CTECC_COR_MASK) 162 163 #define PMSS_SAFETY_P_CSERR_P_BTBECC_COR_MASK (0x8U) 164 #define PMSS_SAFETY_P_CSERR_P_BTBECC_COR_SHIFT (3U) 165 #define PMSS_SAFETY_P_CSERR_P_BTBECC_COR_WIDTH (1U) 166 #define PMSS_SAFETY_P_CSERR_P_BTBECC_COR(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_P_BTBECC_COR_SHIFT)) & PMSS_SAFETY_P_CSERR_P_BTBECC_COR_MASK) 167 168 #define PMSS_SAFETY_P_CSERR_P_CECNTEV_MASK (0x10000U) 169 #define PMSS_SAFETY_P_CSERR_P_CECNTEV_SHIFT (16U) 170 #define PMSS_SAFETY_P_CSERR_P_CECNTEV_WIDTH (1U) 171 #define PMSS_SAFETY_P_CSERR_P_CECNTEV(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_P_CECNTEV_SHIFT)) & PMSS_SAFETY_P_CSERR_P_CECNTEV_MASK) 172 173 #define PMSS_SAFETY_P_CSERR_P_CECNTOV_MASK (0x20000U) 174 #define PMSS_SAFETY_P_CSERR_P_CECNTOV_SHIFT (17U) 175 #define PMSS_SAFETY_P_CSERR_P_CECNTOV_WIDTH (1U) 176 #define PMSS_SAFETY_P_CSERR_P_CECNTOV(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_P_CECNTOV_SHIFT)) & PMSS_SAFETY_P_CSERR_P_CECNTOV_MASK) 177 /*! @} */ 178 179 /*! @name P_UCSERR_S - PMSS UCS ERR Shadow Register */ 180 /*! @{ */ 181 182 #define PMSS_SAFETY_P_UCSERR_S_P_CORE_PERR_S_MASK (0x20U) 183 #define PMSS_SAFETY_P_UCSERR_S_P_CORE_PERR_S_SHIFT (5U) 184 #define PMSS_SAFETY_P_UCSERR_S_P_CORE_PERR_S_WIDTH (1U) 185 #define PMSS_SAFETY_P_UCSERR_S_P_CORE_PERR_S(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_S_P_CORE_PERR_S_SHIFT)) & PMSS_SAFETY_P_UCSERR_S_P_CORE_PERR_S_MASK) 186 187 #define PMSS_SAFETY_P_UCSERR_S_P_MSS_PERR_S_MASK (0x40U) 188 #define PMSS_SAFETY_P_UCSERR_S_P_MSS_PERR_S_SHIFT (6U) 189 #define PMSS_SAFETY_P_UCSERR_S_P_MSS_PERR_S_WIDTH (1U) 190 #define PMSS_SAFETY_P_UCSERR_S_P_MSS_PERR_S(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_S_P_MSS_PERR_S_SHIFT)) & PMSS_SAFETY_P_UCSERR_S_P_MSS_PERR_S_MASK) 191 /*! @} */ 192 193 /*! @name P_CSERR_S - PMSS CE ERR Shadow Register */ 194 /*! @{ */ 195 196 #define PMSS_SAFETY_P_CSERR_S_P_ECC_COR_S_MASK (0x2U) 197 #define PMSS_SAFETY_P_CSERR_S_P_ECC_COR_S_SHIFT (1U) 198 #define PMSS_SAFETY_P_CSERR_S_P_ECC_COR_S_WIDTH (1U) 199 #define PMSS_SAFETY_P_CSERR_S_P_ECC_COR_S(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_S_P_ECC_COR_S_SHIFT)) & PMSS_SAFETY_P_CSERR_S_P_ECC_COR_S_MASK) 200 201 #define PMSS_SAFETY_P_CSERR_S_P_CTECC_COR_S_MASK (0x4U) 202 #define PMSS_SAFETY_P_CSERR_S_P_CTECC_COR_S_SHIFT (2U) 203 #define PMSS_SAFETY_P_CSERR_S_P_CTECC_COR_S_WIDTH (1U) 204 #define PMSS_SAFETY_P_CSERR_S_P_CTECC_COR_S(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_S_P_CTECC_COR_S_SHIFT)) & PMSS_SAFETY_P_CSERR_S_P_CTECC_COR_S_MASK) 205 206 #define PMSS_SAFETY_P_CSERR_S_P_BTBECC_COR_S_MASK (0x8U) 207 #define PMSS_SAFETY_P_CSERR_S_P_BTBECC_COR_S_SHIFT (3U) 208 #define PMSS_SAFETY_P_CSERR_S_P_BTBECC_COR_S_WIDTH (1U) 209 #define PMSS_SAFETY_P_CSERR_S_P_BTBECC_COR_S(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_S_P_BTBECC_COR_S_SHIFT)) & PMSS_SAFETY_P_CSERR_S_P_BTBECC_COR_S_MASK) 210 /*! @} */ 211 212 /*! @name P_CSERR_M - PMSS CS ERR Mask Register */ 213 /*! @{ */ 214 215 #define PMSS_SAFETY_P_CSERR_M_P_CSERR_M_MASK (0x1U) 216 #define PMSS_SAFETY_P_CSERR_M_P_CSERR_M_SHIFT (0U) 217 #define PMSS_SAFETY_P_CSERR_M_P_CSERR_M_WIDTH (1U) 218 #define PMSS_SAFETY_P_CSERR_M_P_CSERR_M(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_M_P_CSERR_M_SHIFT)) & PMSS_SAFETY_P_CSERR_M_P_CSERR_M_MASK) 219 220 #define PMSS_SAFETY_P_CSERR_M_P_ECC_COR_M_MASK (0x2U) 221 #define PMSS_SAFETY_P_CSERR_M_P_ECC_COR_M_SHIFT (1U) 222 #define PMSS_SAFETY_P_CSERR_M_P_ECC_COR_M_WIDTH (1U) 223 #define PMSS_SAFETY_P_CSERR_M_P_ECC_COR_M(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_M_P_ECC_COR_M_SHIFT)) & PMSS_SAFETY_P_CSERR_M_P_ECC_COR_M_MASK) 224 225 #define PMSS_SAFETY_P_CSERR_M_P_CTECC_COR_M_MASK (0x4U) 226 #define PMSS_SAFETY_P_CSERR_M_P_CTECC_COR_M_SHIFT (2U) 227 #define PMSS_SAFETY_P_CSERR_M_P_CTECC_COR_M_WIDTH (1U) 228 #define PMSS_SAFETY_P_CSERR_M_P_CTECC_COR_M(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_M_P_CTECC_COR_M_SHIFT)) & PMSS_SAFETY_P_CSERR_M_P_CTECC_COR_M_MASK) 229 230 #define PMSS_SAFETY_P_CSERR_M_P_BTBECC_COR_M_MASK (0x8U) 231 #define PMSS_SAFETY_P_CSERR_M_P_BTBECC_COR_M_SHIFT (3U) 232 #define PMSS_SAFETY_P_CSERR_M_P_BTBECC_COR_M_WIDTH (1U) 233 #define PMSS_SAFETY_P_CSERR_M_P_BTBECC_COR_M(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_M_P_BTBECC_COR_M_SHIFT)) & PMSS_SAFETY_P_CSERR_M_P_BTBECC_COR_M_MASK) 234 /*! @} */ 235 236 /*! @name P_ECC_TCFG - PMSS ECC TCFG Register */ 237 /*! @{ */ 238 239 #define PMSS_SAFETY_P_ECC_TCFG_P_FLIPCFG_MASK (0xFFFFFFFFU) 240 #define PMSS_SAFETY_P_ECC_TCFG_P_FLIPCFG_SHIFT (0U) 241 #define PMSS_SAFETY_P_ECC_TCFG_P_FLIPCFG_WIDTH (32U) 242 #define PMSS_SAFETY_P_ECC_TCFG_P_FLIPCFG(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_ECC_TCFG_P_FLIPCFG_SHIFT)) & PMSS_SAFETY_P_ECC_TCFG_P_FLIPCFG_MASK) 243 /*! @} */ 244 245 /*! @name P_ECC_TCFG_2 - PMSS ECC TCFG 2 Register */ 246 /*! @{ */ 247 248 #define PMSS_SAFETY_P_ECC_TCFG_2_P_FLIPCFGE_MASK (0x7FU) 249 #define PMSS_SAFETY_P_ECC_TCFG_2_P_FLIPCFGE_SHIFT (0U) 250 #define PMSS_SAFETY_P_ECC_TCFG_2_P_FLIPCFGE_WIDTH (7U) 251 #define PMSS_SAFETY_P_ECC_TCFG_2_P_FLIPCFGE(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_ECC_TCFG_2_P_FLIPCFGE_SHIFT)) & PMSS_SAFETY_P_ECC_TCFG_2_P_FLIPCFGE_MASK) 252 253 #define PMSS_SAFETY_P_ECC_TCFG_2_P_TRIG_MASK (0x80000000U) 254 #define PMSS_SAFETY_P_ECC_TCFG_2_P_TRIG_SHIFT (31U) 255 #define PMSS_SAFETY_P_ECC_TCFG_2_P_TRIG_WIDTH (1U) 256 #define PMSS_SAFETY_P_ECC_TCFG_2_P_TRIG(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_ECC_TCFG_2_P_TRIG_SHIFT)) & PMSS_SAFETY_P_ECC_TCFG_2_P_TRIG_MASK) 257 /*! @} */ 258 259 /*! @name P_CTECC_TCFG - PMSS CT ECC TCFG Register */ 260 /*! @{ */ 261 262 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFG_MASK (0x7FFU) 263 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFG_SHIFT (0U) 264 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFG_WIDTH (11U) 265 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFG(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFG_SHIFT)) & PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFG_MASK) 266 267 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFGE_MASK (0x7800U) 268 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFGE_SHIFT (11U) 269 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFGE_WIDTH (4U) 270 #define PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFGE(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFGE_SHIFT)) & PMSS_SAFETY_P_CTECC_TCFG_PT_FLIPCFGE_MASK) 271 272 #define PMSS_SAFETY_P_CTECC_TCFG_PT_TRIG_MASK (0x80000000U) 273 #define PMSS_SAFETY_P_CTECC_TCFG_PT_TRIG_SHIFT (31U) 274 #define PMSS_SAFETY_P_CTECC_TCFG_PT_TRIG_WIDTH (1U) 275 #define PMSS_SAFETY_P_CTECC_TCFG_PT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CTECC_TCFG_PT_TRIG_SHIFT)) & PMSS_SAFETY_P_CTECC_TCFG_PT_TRIG_MASK) 276 /*! @} */ 277 278 /*! @name P_BTBECC_TCFG - PMSS BTB ECC TCFG Register */ 279 /*! @{ */ 280 281 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFG_MASK (0x7FFU) 282 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFG_SHIFT (0U) 283 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFG_WIDTH (11U) 284 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFG(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFG_SHIFT)) & PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFG_MASK) 285 286 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFGE_MASK (0x7800U) 287 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFGE_SHIFT (11U) 288 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFGE_WIDTH (4U) 289 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFGE(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFGE_SHIFT)) & PMSS_SAFETY_P_BTBECC_TCFG_PB_FLIPCFGE_MASK) 290 291 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_TRIG_MASK (0x80000000U) 292 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_TRIG_SHIFT (31U) 293 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_TRIG_WIDTH (1U) 294 #define PMSS_SAFETY_P_BTBECC_TCFG_PB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_BTBECC_TCFG_PB_TRIG_SHIFT)) & PMSS_SAFETY_P_BTBECC_TCFG_PB_TRIG_MASK) 295 /*! @} */ 296 297 /*! @name P_UCSERR_CNT - PMSS UCSERR CNT Register */ 298 /*! @{ */ 299 300 #define PMSS_SAFETY_P_UCSERR_CNT_P_UCSERR_CNT_V_MASK (0xFFFFU) 301 #define PMSS_SAFETY_P_UCSERR_CNT_P_UCSERR_CNT_V_SHIFT (0U) 302 #define PMSS_SAFETY_P_UCSERR_CNT_P_UCSERR_CNT_V_WIDTH (16U) 303 #define PMSS_SAFETY_P_UCSERR_CNT_P_UCSERR_CNT_V(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_UCSERR_CNT_P_UCSERR_CNT_V_SHIFT)) & PMSS_SAFETY_P_UCSERR_CNT_P_UCSERR_CNT_V_MASK) 304 /*! @} */ 305 306 /*! @name P_CSERR_CNT - PMSS CSERR CNT Register */ 307 /*! @{ */ 308 309 #define PMSS_SAFETY_P_CSERR_CNT_P_CSERR_CNT_V_MASK (0xFFFFU) 310 #define PMSS_SAFETY_P_CSERR_CNT_P_CSERR_CNT_V_SHIFT (0U) 311 #define PMSS_SAFETY_P_CSERR_CNT_P_CSERR_CNT_V_WIDTH (16U) 312 #define PMSS_SAFETY_P_CSERR_CNT_P_CSERR_CNT_V(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_CSERR_CNT_P_CSERR_CNT_V_SHIFT)) & PMSS_SAFETY_P_CSERR_CNT_P_CSERR_CNT_V_MASK) 313 /*! @} */ 314 315 /*! @name P_LPCS - PMSS LPCS Register */ 316 /*! @{ */ 317 318 #define PMSS_SAFETY_P_LPCS_TS_MASK (0x1U) 319 #define PMSS_SAFETY_P_LPCS_TS_SHIFT (0U) 320 #define PMSS_SAFETY_P_LPCS_TS_WIDTH (1U) 321 #define PMSS_SAFETY_P_LPCS_TS(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_LPCS_TS_SHIFT)) & PMSS_SAFETY_P_LPCS_TS_MASK) 322 323 #define PMSS_SAFETY_P_LPCS_WSEL_MASK (0x30U) 324 #define PMSS_SAFETY_P_LPCS_WSEL_SHIFT (4U) 325 #define PMSS_SAFETY_P_LPCS_WSEL_WIDTH (2U) 326 #define PMSS_SAFETY_P_LPCS_WSEL(x) (((uint32_t)(((uint32_t)(x)) << PMSS_SAFETY_P_LPCS_WSEL_SHIFT)) & PMSS_SAFETY_P_LPCS_WSEL_MASK) 327 /*! @} */ 328 329 /*! 330 * @} 331 */ /* end of group PMSS_SAFETY_Register_Masks */ 332 333 /*! 334 * @} 335 */ /* end of group PMSS_SAFETY_Peripheral_Access_Layer */ 336 337 #endif /* #if !defined(S32Z2_PMSS_SAFETY_H_) */ 338
