1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DMSS_SAFETY.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DMSS_SAFETY 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DMSS_SAFETY_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DMSS_SAFETY_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMSS_SAFETY Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMSS_SAFETY_Peripheral_Access_Layer DMSS_SAFETY Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMSS_SAFETY - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t D_UCSERR; /**< DMSS UCS ERR Register, offset: 0x0 */ 74 uint8_t RESERVED_0[4]; 75 __IO uint32_t D_CSERR; /**< DMSS CS ERR Register, offset: 0x8 */ 76 uint8_t RESERVED_1[4]; 77 __O uint32_t D_UCSERR_S; /**< DMSS UCS ERR Shadow Register, offset: 0x10 */ 78 __O uint32_t D_CSERR_S; /**< DMSS CS ERR Shadow Register, offset: 0x14 */ 79 uint8_t RESERVED_2[4]; 80 __IO uint32_t D_CSERR_M; /**< DMSS CS ERR Mask Register, offset: 0x1C */ 81 __IO uint32_t D_ECC_TCFG; /**< DMSS ECC TCFG Register, offset: 0x20 */ 82 __IO uint32_t D_ECC_TCFG_2; /**< DMSS ECC TCFG 2 Register, offset: 0x24 */ 83 uint8_t RESERVED_3[8]; 84 __IO uint32_t D_SFT_SCPD_0; /**< DMSS SFT SCPD 0 Register, offset: 0x30 */ 85 __IO uint32_t D_SFT_SCPD_1; /**< DMSS SFT SCPD 1 Register, offset: 0x34 */ 86 __IO uint32_t D_SFT_SCPD_2; /**< DMSS SFT SCPD 2 Register, offset: 0x38 */ 87 __IO uint32_t D_SFT_SCPD_3; /**< DMSS SFT SCPD 3 Register, offset: 0x3C */ 88 __I uint32_t D_UCSERR_CNT; /**< DMSS UCS ERR Register, offset: 0x40 */ 89 __I uint32_t D_CSERR_CNT; /**< DMSS CS ERR CNT Register, offset: 0x44 */ 90 } DMSS_SAFETY_Type, *DMSS_SAFETY_MemMapPtr; 91 92 /** Number of instances of the DMSS_SAFETY module. */ 93 #define DMSS_SAFETY_INSTANCE_COUNT (1u) 94 95 /* DMSS_SAFETY - Peripheral instance base addresses */ 96 /** Peripheral CEVA_SPF2__DMSS_SAFETY base address */ 97 #define IP_CEVA_SPF2__DMSS_SAFETY_BASE (0x244007B0u) 98 /** Peripheral CEVA_SPF2__DMSS_SAFETY base pointer */ 99 #define IP_CEVA_SPF2__DMSS_SAFETY ((DMSS_SAFETY_Type *)IP_CEVA_SPF2__DMSS_SAFETY_BASE) 100 /** Array initializer of DMSS_SAFETY peripheral base addresses */ 101 #define IP_DMSS_SAFETY_BASE_ADDRS { IP_CEVA_SPF2__DMSS_SAFETY_BASE } 102 /** Array initializer of DMSS_SAFETY peripheral base pointers */ 103 #define IP_DMSS_SAFETY_BASE_PTRS { IP_CEVA_SPF2__DMSS_SAFETY } 104 105 /* ---------------------------------------------------------------------------- 106 -- DMSS_SAFETY Register Masks 107 ---------------------------------------------------------------------------- */ 108 109 /*! 110 * @addtogroup DMSS_SAFETY_Register_Masks DMSS_SAFETY Register Masks 111 * @{ 112 */ 113 114 /*! @name D_UCSERR - DMSS UCS ERR Register */ 115 /*! @{ */ 116 117 #define DMSS_SAFETY_D_UCSERR_D_UCSERR_MASK (0x1U) 118 #define DMSS_SAFETY_D_UCSERR_D_UCSERR_SHIFT (0U) 119 #define DMSS_SAFETY_D_UCSERR_D_UCSERR_WIDTH (1U) 120 #define DMSS_SAFETY_D_UCSERR_D_UCSERR(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_D_UCSERR_SHIFT)) & DMSS_SAFETY_D_UCSERR_D_UCSERR_MASK) 121 122 #define DMSS_SAFETY_D_UCSERR_D_ECC_ERR_MASK (0x2U) 123 #define DMSS_SAFETY_D_UCSERR_D_ECC_ERR_SHIFT (1U) 124 #define DMSS_SAFETY_D_UCSERR_D_ECC_ERR_WIDTH (1U) 125 #define DMSS_SAFETY_D_UCSERR_D_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_D_ECC_ERR_SHIFT)) & DMSS_SAFETY_D_UCSERR_D_ECC_ERR_MASK) 126 127 #define DMSS_SAFETY_D_UCSERR_D_MSS_PERR_MASK (0x200U) 128 #define DMSS_SAFETY_D_UCSERR_D_MSS_PERR_SHIFT (9U) 129 #define DMSS_SAFETY_D_UCSERR_D_MSS_PERR_WIDTH (1U) 130 #define DMSS_SAFETY_D_UCSERR_D_MSS_PERR(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_D_MSS_PERR_SHIFT)) & DMSS_SAFETY_D_UCSERR_D_MSS_PERR_MASK) 131 132 #define DMSS_SAFETY_D_UCSERR_D_UCECNTEV_MASK (0x10000U) 133 #define DMSS_SAFETY_D_UCSERR_D_UCECNTEV_SHIFT (16U) 134 #define DMSS_SAFETY_D_UCSERR_D_UCECNTEV_WIDTH (1U) 135 #define DMSS_SAFETY_D_UCSERR_D_UCECNTEV(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_D_UCECNTEV_SHIFT)) & DMSS_SAFETY_D_UCSERR_D_UCECNTEV_MASK) 136 137 #define DMSS_SAFETY_D_UCSERR_D_UCECNTOV_MASK (0x20000U) 138 #define DMSS_SAFETY_D_UCSERR_D_UCECNTOV_SHIFT (17U) 139 #define DMSS_SAFETY_D_UCSERR_D_UCECNTOV_WIDTH (1U) 140 #define DMSS_SAFETY_D_UCSERR_D_UCECNTOV(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_D_UCECNTOV_SHIFT)) & DMSS_SAFETY_D_UCSERR_D_UCECNTOV_MASK) 141 142 #define DMSS_SAFETY_D_UCSERR_CWDOGIRQ_MASK (0x40000000U) 143 #define DMSS_SAFETY_D_UCSERR_CWDOGIRQ_SHIFT (30U) 144 #define DMSS_SAFETY_D_UCSERR_CWDOGIRQ_WIDTH (1U) 145 #define DMSS_SAFETY_D_UCSERR_CWDOGIRQ(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_CWDOGIRQ_SHIFT)) & DMSS_SAFETY_D_UCSERR_CWDOGIRQ_MASK) 146 147 #define DMSS_SAFETY_D_UCSERR_CENSIRQ_MASK (0x80000000U) 148 #define DMSS_SAFETY_D_UCSERR_CENSIRQ_SHIFT (31U) 149 #define DMSS_SAFETY_D_UCSERR_CENSIRQ_WIDTH (1U) 150 #define DMSS_SAFETY_D_UCSERR_CENSIRQ(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_CENSIRQ_SHIFT)) & DMSS_SAFETY_D_UCSERR_CENSIRQ_MASK) 151 /*! @} */ 152 153 /*! @name D_CSERR - DMSS CS ERR Register */ 154 /*! @{ */ 155 156 #define DMSS_SAFETY_D_CSERR_D_CSERR_MASK (0x1U) 157 #define DMSS_SAFETY_D_CSERR_D_CSERR_SHIFT (0U) 158 #define DMSS_SAFETY_D_CSERR_D_CSERR_WIDTH (1U) 159 #define DMSS_SAFETY_D_CSERR_D_CSERR(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_D_CSERR_SHIFT)) & DMSS_SAFETY_D_CSERR_D_CSERR_MASK) 160 161 #define DMSS_SAFETY_D_CSERR_D_ECC_COR_MASK (0x2U) 162 #define DMSS_SAFETY_D_CSERR_D_ECC_COR_SHIFT (1U) 163 #define DMSS_SAFETY_D_CSERR_D_ECC_COR_WIDTH (1U) 164 #define DMSS_SAFETY_D_CSERR_D_ECC_COR(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_D_ECC_COR_SHIFT)) & DMSS_SAFETY_D_CSERR_D_ECC_COR_MASK) 165 166 #define DMSS_SAFETY_D_CSERR_D_CECNTEV_MASK (0x10000U) 167 #define DMSS_SAFETY_D_CSERR_D_CECNTEV_SHIFT (16U) 168 #define DMSS_SAFETY_D_CSERR_D_CECNTEV_WIDTH (1U) 169 #define DMSS_SAFETY_D_CSERR_D_CECNTEV(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_D_CECNTEV_SHIFT)) & DMSS_SAFETY_D_CSERR_D_CECNTEV_MASK) 170 171 #define DMSS_SAFETY_D_CSERR_D_CECNTOV_MASK (0x20000U) 172 #define DMSS_SAFETY_D_CSERR_D_CECNTOV_SHIFT (17U) 173 #define DMSS_SAFETY_D_CSERR_D_CECNTOV_WIDTH (1U) 174 #define DMSS_SAFETY_D_CSERR_D_CECNTOV(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_D_CECNTOV_SHIFT)) & DMSS_SAFETY_D_CSERR_D_CECNTOV_MASK) 175 176 #define DMSS_SAFETY_D_CSERR_NNSE_MASK (0x80000000U) 177 #define DMSS_SAFETY_D_CSERR_NNSE_SHIFT (31U) 178 #define DMSS_SAFETY_D_CSERR_NNSE_WIDTH (1U) 179 #define DMSS_SAFETY_D_CSERR_NNSE(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_NNSE_SHIFT)) & DMSS_SAFETY_D_CSERR_NNSE_MASK) 180 /*! @} */ 181 182 /*! @name D_UCSERR_S - DMSS UCS ERR Shadow Register */ 183 /*! @{ */ 184 185 #define DMSS_SAFETY_D_UCSERR_S_D_ECC_ERR_S_MASK (0x2U) 186 #define DMSS_SAFETY_D_UCSERR_S_D_ECC_ERR_S_SHIFT (1U) 187 #define DMSS_SAFETY_D_UCSERR_S_D_ECC_ERR_S_WIDTH (1U) 188 #define DMSS_SAFETY_D_UCSERR_S_D_ECC_ERR_S(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_S_D_ECC_ERR_S_SHIFT)) & DMSS_SAFETY_D_UCSERR_S_D_ECC_ERR_S_MASK) 189 190 #define DMSS_SAFETY_D_UCSERR_S_D_MSS_PERR_S_MASK (0x200U) 191 #define DMSS_SAFETY_D_UCSERR_S_D_MSS_PERR_S_SHIFT (9U) 192 #define DMSS_SAFETY_D_UCSERR_S_D_MSS_PERR_S_WIDTH (1U) 193 #define DMSS_SAFETY_D_UCSERR_S_D_MSS_PERR_S(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_S_D_MSS_PERR_S_SHIFT)) & DMSS_SAFETY_D_UCSERR_S_D_MSS_PERR_S_MASK) 194 /*! @} */ 195 196 /*! @name D_CSERR_S - DMSS CS ERR Shadow Register */ 197 /*! @{ */ 198 199 #define DMSS_SAFETY_D_CSERR_S_D_ECC_COR_S_MASK (0x2U) 200 #define DMSS_SAFETY_D_CSERR_S_D_ECC_COR_S_SHIFT (1U) 201 #define DMSS_SAFETY_D_CSERR_S_D_ECC_COR_S_WIDTH (1U) 202 #define DMSS_SAFETY_D_CSERR_S_D_ECC_COR_S(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_S_D_ECC_COR_S_SHIFT)) & DMSS_SAFETY_D_CSERR_S_D_ECC_COR_S_MASK) 203 /*! @} */ 204 205 /*! @name D_CSERR_M - DMSS CS ERR Mask Register */ 206 /*! @{ */ 207 208 #define DMSS_SAFETY_D_CSERR_M_D_CSRERR_M_MASK (0x1U) 209 #define DMSS_SAFETY_D_CSERR_M_D_CSRERR_M_SHIFT (0U) 210 #define DMSS_SAFETY_D_CSERR_M_D_CSRERR_M_WIDTH (1U) 211 #define DMSS_SAFETY_D_CSERR_M_D_CSRERR_M(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_M_D_CSRERR_M_SHIFT)) & DMSS_SAFETY_D_CSERR_M_D_CSRERR_M_MASK) 212 213 #define DMSS_SAFETY_D_CSERR_M_D_ECC_COR_M_MASK (0x2U) 214 #define DMSS_SAFETY_D_CSERR_M_D_ECC_COR_M_SHIFT (1U) 215 #define DMSS_SAFETY_D_CSERR_M_D_ECC_COR_M_WIDTH (1U) 216 #define DMSS_SAFETY_D_CSERR_M_D_ECC_COR_M(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_M_D_ECC_COR_M_SHIFT)) & DMSS_SAFETY_D_CSERR_M_D_ECC_COR_M_MASK) 217 /*! @} */ 218 219 /*! @name D_ECC_TCFG - DMSS ECC TCFG Register */ 220 /*! @{ */ 221 222 #define DMSS_SAFETY_D_ECC_TCFG_D_FLIPCFG_MASK (0xFFFFFFFFU) 223 #define DMSS_SAFETY_D_ECC_TCFG_D_FLIPCFG_SHIFT (0U) 224 #define DMSS_SAFETY_D_ECC_TCFG_D_FLIPCFG_WIDTH (32U) 225 #define DMSS_SAFETY_D_ECC_TCFG_D_FLIPCFG(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_ECC_TCFG_D_FLIPCFG_SHIFT)) & DMSS_SAFETY_D_ECC_TCFG_D_FLIPCFG_MASK) 226 /*! @} */ 227 228 /*! @name D_ECC_TCFG_2 - DMSS ECC TCFG 2 Register */ 229 /*! @{ */ 230 231 #define DMSS_SAFETY_D_ECC_TCFG_2_D_FLIPCFGE_MASK (0x7FU) 232 #define DMSS_SAFETY_D_ECC_TCFG_2_D_FLIPCFGE_SHIFT (0U) 233 #define DMSS_SAFETY_D_ECC_TCFG_2_D_FLIPCFGE_WIDTH (7U) 234 #define DMSS_SAFETY_D_ECC_TCFG_2_D_FLIPCFGE(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_ECC_TCFG_2_D_FLIPCFGE_SHIFT)) & DMSS_SAFETY_D_ECC_TCFG_2_D_FLIPCFGE_MASK) 235 236 #define DMSS_SAFETY_D_ECC_TCFG_2_D_TRIG_MASK (0x80000000U) 237 #define DMSS_SAFETY_D_ECC_TCFG_2_D_TRIG_SHIFT (31U) 238 #define DMSS_SAFETY_D_ECC_TCFG_2_D_TRIG_WIDTH (1U) 239 #define DMSS_SAFETY_D_ECC_TCFG_2_D_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_ECC_TCFG_2_D_TRIG_SHIFT)) & DMSS_SAFETY_D_ECC_TCFG_2_D_TRIG_MASK) 240 /*! @} */ 241 242 /*! @name D_SFT_SCPD_0 - DMSS SFT SCPD 0 Register */ 243 /*! @{ */ 244 245 #define DMSS_SAFETY_D_SFT_SCPD_0_SFT_SCPD0_MASK (0xFFFFFFFFU) 246 #define DMSS_SAFETY_D_SFT_SCPD_0_SFT_SCPD0_SHIFT (0U) 247 #define DMSS_SAFETY_D_SFT_SCPD_0_SFT_SCPD0_WIDTH (32U) 248 #define DMSS_SAFETY_D_SFT_SCPD_0_SFT_SCPD0(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_SFT_SCPD_0_SFT_SCPD0_SHIFT)) & DMSS_SAFETY_D_SFT_SCPD_0_SFT_SCPD0_MASK) 249 /*! @} */ 250 251 /*! @name D_SFT_SCPD_1 - DMSS SFT SCPD 1 Register */ 252 /*! @{ */ 253 254 #define DMSS_SAFETY_D_SFT_SCPD_1_SFT_SCPD1_MASK (0xFFFFFFFFU) 255 #define DMSS_SAFETY_D_SFT_SCPD_1_SFT_SCPD1_SHIFT (0U) 256 #define DMSS_SAFETY_D_SFT_SCPD_1_SFT_SCPD1_WIDTH (32U) 257 #define DMSS_SAFETY_D_SFT_SCPD_1_SFT_SCPD1(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_SFT_SCPD_1_SFT_SCPD1_SHIFT)) & DMSS_SAFETY_D_SFT_SCPD_1_SFT_SCPD1_MASK) 258 /*! @} */ 259 260 /*! @name D_SFT_SCPD_2 - DMSS SFT SCPD 2 Register */ 261 /*! @{ */ 262 263 #define DMSS_SAFETY_D_SFT_SCPD_2_SFT_SCPD2_MASK (0xFFFFFFFFU) 264 #define DMSS_SAFETY_D_SFT_SCPD_2_SFT_SCPD2_SHIFT (0U) 265 #define DMSS_SAFETY_D_SFT_SCPD_2_SFT_SCPD2_WIDTH (32U) 266 #define DMSS_SAFETY_D_SFT_SCPD_2_SFT_SCPD2(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_SFT_SCPD_2_SFT_SCPD2_SHIFT)) & DMSS_SAFETY_D_SFT_SCPD_2_SFT_SCPD2_MASK) 267 /*! @} */ 268 269 /*! @name D_SFT_SCPD_3 - DMSS SFT SCPD 3 Register */ 270 /*! @{ */ 271 272 #define DMSS_SAFETY_D_SFT_SCPD_3_SFT_SCPD3_MASK (0xFFFFFFFFU) 273 #define DMSS_SAFETY_D_SFT_SCPD_3_SFT_SCPD3_SHIFT (0U) 274 #define DMSS_SAFETY_D_SFT_SCPD_3_SFT_SCPD3_WIDTH (32U) 275 #define DMSS_SAFETY_D_SFT_SCPD_3_SFT_SCPD3(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_SFT_SCPD_3_SFT_SCPD3_SHIFT)) & DMSS_SAFETY_D_SFT_SCPD_3_SFT_SCPD3_MASK) 276 /*! @} */ 277 278 /*! @name D_UCSERR_CNT - DMSS UCS ERR Register */ 279 /*! @{ */ 280 281 #define DMSS_SAFETY_D_UCSERR_CNT_D_UCSERR_CNT_V_MASK (0xFFFFU) 282 #define DMSS_SAFETY_D_UCSERR_CNT_D_UCSERR_CNT_V_SHIFT (0U) 283 #define DMSS_SAFETY_D_UCSERR_CNT_D_UCSERR_CNT_V_WIDTH (16U) 284 #define DMSS_SAFETY_D_UCSERR_CNT_D_UCSERR_CNT_V(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_UCSERR_CNT_D_UCSERR_CNT_V_SHIFT)) & DMSS_SAFETY_D_UCSERR_CNT_D_UCSERR_CNT_V_MASK) 285 /*! @} */ 286 287 /*! @name D_CSERR_CNT - DMSS CS ERR CNT Register */ 288 /*! @{ */ 289 290 #define DMSS_SAFETY_D_CSERR_CNT_D_CSERR_CNT_V_MASK (0xFFFFU) 291 #define DMSS_SAFETY_D_CSERR_CNT_D_CSERR_CNT_V_SHIFT (0U) 292 #define DMSS_SAFETY_D_CSERR_CNT_D_CSERR_CNT_V_WIDTH (16U) 293 #define DMSS_SAFETY_D_CSERR_CNT_D_CSERR_CNT_V(x) (((uint32_t)(((uint32_t)(x)) << DMSS_SAFETY_D_CSERR_CNT_D_CSERR_CNT_V_SHIFT)) & DMSS_SAFETY_D_CSERR_CNT_D_CSERR_CNT_V_MASK) 294 /*! @} */ 295 296 /*! 297 * @} 298 */ /* end of group DMSS_SAFETY_Register_Masks */ 299 300 /*! 301 * @} 302 */ /* end of group DMSS_SAFETY_Peripheral_Access_Layer */ 303 304 #endif /* #if !defined(S32Z2_DMSS_SAFETY_H_) */ 305
