1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CORE_SAFETY.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CORE_SAFETY 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CORE_SAFETY_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CORE_SAFETY_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CORE_SAFETY Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CORE_SAFETY_Peripheral_Access_Layer CORE_SAFETY Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CORE_SAFETY - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t C_UCPERR; /**< Core UCP ERR Register, offset: 0x0 */ 74 __O uint32_t C_UCPERR_S; /**< Core UCP ERR Shadow Register, offset: 0x4 */ 75 } CORE_SAFETY_Type, *CORE_SAFETY_MemMapPtr; 76 77 /** Number of instances of the CORE_SAFETY module. */ 78 #define CORE_SAFETY_INSTANCE_COUNT (1u) 79 80 /* CORE_SAFETY - Peripheral instance base addresses */ 81 /** Peripheral CEVA_SPF2__CORE_SAFETY base address */ 82 #define IP_CEVA_SPF2__CORE_SAFETY_BASE (0x24400750u) 83 /** Peripheral CEVA_SPF2__CORE_SAFETY base pointer */ 84 #define IP_CEVA_SPF2__CORE_SAFETY ((CORE_SAFETY_Type *)IP_CEVA_SPF2__CORE_SAFETY_BASE) 85 /** Array initializer of CORE_SAFETY peripheral base addresses */ 86 #define IP_CORE_SAFETY_BASE_ADDRS { IP_CEVA_SPF2__CORE_SAFETY_BASE } 87 /** Array initializer of CORE_SAFETY peripheral base pointers */ 88 #define IP_CORE_SAFETY_BASE_PTRS { IP_CEVA_SPF2__CORE_SAFETY } 89 90 /* ---------------------------------------------------------------------------- 91 -- CORE_SAFETY Register Masks 92 ---------------------------------------------------------------------------- */ 93 94 /*! 95 * @addtogroup CORE_SAFETY_Register_Masks CORE_SAFETY Register Masks 96 * @{ 97 */ 98 99 /*! @name C_UCPERR - Core UCP ERR Register */ 100 /*! @{ */ 101 102 #define CORE_SAFETY_C_UCPERR_C_UCPERR_MASK (0x1U) 103 #define CORE_SAFETY_C_UCPERR_C_UCPERR_SHIFT (0U) 104 #define CORE_SAFETY_C_UCPERR_C_UCPERR_WIDTH (1U) 105 #define CORE_SAFETY_C_UCPERR_C_UCPERR(x) (((uint32_t)(((uint32_t)(x)) << CORE_SAFETY_C_UCPERR_C_UCPERR_SHIFT)) & CORE_SAFETY_C_UCPERR_C_UCPERR_MASK) 106 107 #define CORE_SAFETY_C_UCPERR_P_ECC_ERR_MASK (0x2U) 108 #define CORE_SAFETY_C_UCPERR_P_ECC_ERR_SHIFT (1U) 109 #define CORE_SAFETY_C_UCPERR_P_ECC_ERR_WIDTH (1U) 110 #define CORE_SAFETY_C_UCPERR_P_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << CORE_SAFETY_C_UCPERR_P_ECC_ERR_SHIFT)) & CORE_SAFETY_C_UCPERR_P_ECC_ERR_MASK) 111 112 #define CORE_SAFETY_C_UCPERR_P_EAC_ERR_MASK (0x8U) 113 #define CORE_SAFETY_C_UCPERR_P_EAC_ERR_SHIFT (3U) 114 #define CORE_SAFETY_C_UCPERR_P_EAC_ERR_WIDTH (1U) 115 #define CORE_SAFETY_C_UCPERR_P_EAC_ERR(x) (((uint32_t)(((uint32_t)(x)) << CORE_SAFETY_C_UCPERR_P_EAC_ERR_SHIFT)) & CORE_SAFETY_C_UCPERR_P_EAC_ERR_MASK) 116 117 #define CORE_SAFETY_C_UCPERR_C_ILPE_MASK (0x100U) 118 #define CORE_SAFETY_C_UCPERR_C_ILPE_SHIFT (8U) 119 #define CORE_SAFETY_C_UCPERR_C_ILPE_WIDTH (1U) 120 #define CORE_SAFETY_C_UCPERR_C_ILPE(x) (((uint32_t)(((uint32_t)(x)) << CORE_SAFETY_C_UCPERR_C_ILPE_SHIFT)) & CORE_SAFETY_C_UCPERR_C_ILPE_MASK) 121 /*! @} */ 122 123 /*! @name C_UCPERR_S - Core UCP ERR Shadow Register */ 124 /*! @{ */ 125 126 #define CORE_SAFETY_C_UCPERR_S_P_ECC_ERR_S_MASK (0x2U) 127 #define CORE_SAFETY_C_UCPERR_S_P_ECC_ERR_S_SHIFT (1U) 128 #define CORE_SAFETY_C_UCPERR_S_P_ECC_ERR_S_WIDTH (1U) 129 #define CORE_SAFETY_C_UCPERR_S_P_ECC_ERR_S(x) (((uint32_t)(((uint32_t)(x)) << CORE_SAFETY_C_UCPERR_S_P_ECC_ERR_S_SHIFT)) & CORE_SAFETY_C_UCPERR_S_P_ECC_ERR_S_MASK) 130 /*! @} */ 131 132 /*! 133 * @} 134 */ /* end of group CORE_SAFETY_Register_Masks */ 135 136 /*! 137 * @} 138 */ /* end of group CORE_SAFETY_Peripheral_Access_Layer */ 139 140 #endif /* #if !defined(S32Z2_CORE_SAFETY_H_) */ 141
