1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ACE.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ACE 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ACE_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ACE_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ACE Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ACE_Peripheral_Access_Layer ACE Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ACE - Register Layout Typedef */ 72 typedef struct { 73 __O uint64_t INIT_VEC; /**< Initial Value, offset: 0x0, available only on: AES.ACE.AHB/AES__ACE__AHB (missing on AES.ACE.AHB2/AES__ACE__AHB2) */ 74 __O uint64_t DATA_IN; /**< Data Input, offset: 0x8, available only on: AES.ACE.AHB/AES__ACE__AHB (missing on AES.ACE.AHB2/AES__ACE__AHB2) */ 75 uint8_t RESERVED_0[240]; 76 __I uint64_t STATUS; /**< Status, offset: 0x100, available only on: AES.ACE.AHB2/AES__ACE__AHB2 (missing on AES.ACE.AHB/AES__ACE__AHB) */ 77 __IO uint64_t CONTROL; /**< Control, offset: 0x108, available only on: AES.ACE.AHB2/AES__ACE__AHB2 (missing on AES.ACE.AHB/AES__ACE__AHB) */ 78 uint8_t RESERVED_1[8]; 79 __IO uint64_t RESULT; /**< Result, offset: 0x118, available only on: AES.ACE.AHB2/AES__ACE__AHB2 (missing on AES.ACE.AHB/AES__ACE__AHB) */ 80 __IO uint64_t AUTH_TAG; /**< Auth Tag Output, offset: 0x120, available only on: AES.ACE.AHB2/AES__ACE__AHB2 (missing on AES.ACE.AHB/AES__ACE__AHB) */ 81 __I uint64_t VERSION; /**< ACE Version, offset: 0x128, available only on: AES.ACE.AHB2/AES__ACE__AHB2 (missing on AES.ACE.AHB/AES__ACE__AHB) */ 82 } ACE_Type, *ACE_MemMapPtr; 83 84 /** Number of instances of the ACE module. */ 85 #define ACE_INSTANCE_COUNT (2u) 86 87 /* ACE - Peripheral instance base addresses */ 88 /** Peripheral AES__ACE__AHB base address */ 89 #define IP_AES__ACE__AHB_BASE (0x47000000u) 90 /** Peripheral AES__ACE__AHB base pointer */ 91 #define IP_AES__ACE__AHB ((ACE_Type *)IP_AES__ACE__AHB_BASE) 92 /** Peripheral AES__ACE__AHB2 base address */ 93 #define IP_AES__ACE__AHB2_BASE (0x47000000u) 94 /** Peripheral AES__ACE__AHB2 base pointer */ 95 #define IP_AES__ACE__AHB2 ((ACE_Type *)IP_AES__ACE__AHB2_BASE) 96 /** Array initializer of ACE peripheral base addresses */ 97 #define IP_ACE_BASE_ADDRS { IP_AES__ACE__AHB_BASE, IP_AES__ACE__AHB2_BASE } 98 /** Array initializer of ACE peripheral base pointers */ 99 #define IP_ACE_BASE_PTRS { IP_AES__ACE__AHB, IP_AES__ACE__AHB2 } 100 101 /* ---------------------------------------------------------------------------- 102 -- ACE Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup ACE_Register_Masks ACE Register Masks 107 * @{ 108 */ 109 110 /*! @name INIT_VEC - Initial Value */ 111 /*! @{ */ 112 113 #define ACE_INIT_VEC_DATA_MASK (0xFFFFFFFFFFFFFFFFU) 114 #define ACE_INIT_VEC_DATA_SHIFT (0U) 115 #define ACE_INIT_VEC_DATA_WIDTH (64U) 116 #define ACE_INIT_VEC_DATA(x) (((uint64_t)(((uint64_t)(x)) << ACE_INIT_VEC_DATA_SHIFT)) & ACE_INIT_VEC_DATA_MASK) 117 /*! @} */ 118 119 /*! @name DATA_IN - Data Input */ 120 /*! @{ */ 121 122 #define ACE_DATA_IN_DATA_MASK (0xFFFFFFFFFFFFFFFFU) 123 #define ACE_DATA_IN_DATA_SHIFT (0U) 124 #define ACE_DATA_IN_DATA_WIDTH (64U) 125 #define ACE_DATA_IN_DATA(x) (((uint64_t)(((uint64_t)(x)) << ACE_DATA_IN_DATA_SHIFT)) & ACE_DATA_IN_DATA_MASK) 126 /*! @} */ 127 128 /*! @name STATUS - Status */ 129 /*! @{ */ 130 131 #define ACE_STATUS_BUSY_MASK (0x2U) 132 #define ACE_STATUS_BUSY_SHIFT (1U) 133 #define ACE_STATUS_BUSY_WIDTH (1U) 134 #define ACE_STATUS_BUSY(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_BUSY_SHIFT)) & ACE_STATUS_BUSY_MASK) 135 136 #define ACE_STATUS_ERROR_MASK (0x1CU) 137 #define ACE_STATUS_ERROR_SHIFT (2U) 138 #define ACE_STATUS_ERROR_WIDTH (3U) 139 #define ACE_STATUS_ERROR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_ERROR_SHIFT)) & ACE_STATUS_ERROR_MASK) 140 141 #define ACE_STATUS_K_ERR_MASK (0x10000U) 142 #define ACE_STATUS_K_ERR_SHIFT (16U) 143 #define ACE_STATUS_K_ERR_WIDTH (1U) 144 #define ACE_STATUS_K_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_K_ERR_SHIFT)) & ACE_STATUS_K_ERR_MASK) 145 146 #define ACE_STATUS_CMP_ERR_MASK (0x20000U) 147 #define ACE_STATUS_CMP_ERR_SHIFT (17U) 148 #define ACE_STATUS_CMP_ERR_WIDTH (1U) 149 #define ACE_STATUS_CMP_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_CMP_ERR_SHIFT)) & ACE_STATUS_CMP_ERR_MASK) 150 151 #define ACE_STATUS_KD_ERR_MASK (0x40000U) 152 #define ACE_STATUS_KD_ERR_SHIFT (18U) 153 #define ACE_STATUS_KD_ERR_WIDTH (1U) 154 #define ACE_STATUS_KD_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_KD_ERR_SHIFT)) & ACE_STATUS_KD_ERR_MASK) 155 156 #define ACE_STATUS_KP_ERR_MASK (0x80000U) 157 #define ACE_STATUS_KP_ERR_SHIFT (19U) 158 #define ACE_STATUS_KP_ERR_WIDTH (1U) 159 #define ACE_STATUS_KP_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_KP_ERR_SHIFT)) & ACE_STATUS_KP_ERR_MASK) 160 161 #define ACE_STATUS_VERIFY_ERR_MASK (0x100000U) 162 #define ACE_STATUS_VERIFY_ERR_SHIFT (20U) 163 #define ACE_STATUS_VERIFY_ERR_WIDTH (1U) 164 #define ACE_STATUS_VERIFY_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_VERIFY_ERR_SHIFT)) & ACE_STATUS_VERIFY_ERR_MASK) 165 166 #define ACE_STATUS_DMA_ERR_MASK (0x200000U) 167 #define ACE_STATUS_DMA_ERR_SHIFT (21U) 168 #define ACE_STATUS_DMA_ERR_WIDTH (1U) 169 #define ACE_STATUS_DMA_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_DMA_ERR_SHIFT)) & ACE_STATUS_DMA_ERR_MASK) 170 171 #define ACE_STATUS_ECC_ERR_MASK (0x400000U) 172 #define ACE_STATUS_ECC_ERR_SHIFT (22U) 173 #define ACE_STATUS_ECC_ERR_WIDTH (1U) 174 #define ACE_STATUS_ECC_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_ECC_ERR_SHIFT)) & ACE_STATUS_ECC_ERR_MASK) 175 176 #define ACE_STATUS_DMA1_DID_ERR_MASK (0x800000U) 177 #define ACE_STATUS_DMA1_DID_ERR_SHIFT (23U) 178 #define ACE_STATUS_DMA1_DID_ERR_WIDTH (1U) 179 #define ACE_STATUS_DMA1_DID_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_DMA1_DID_ERR_SHIFT)) & ACE_STATUS_DMA1_DID_ERR_MASK) 180 181 #define ACE_STATUS_DMA2_DID_ERR_MASK (0x1000000U) 182 #define ACE_STATUS_DMA2_DID_ERR_SHIFT (24U) 183 #define ACE_STATUS_DMA2_DID_ERR_WIDTH (1U) 184 #define ACE_STATUS_DMA2_DID_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_DMA2_DID_ERR_SHIFT)) & ACE_STATUS_DMA2_DID_ERR_MASK) 185 186 #define ACE_STATUS_KP_CRC_ERR_MASK (0x2000000U) 187 #define ACE_STATUS_KP_CRC_ERR_SHIFT (25U) 188 #define ACE_STATUS_KP_CRC_ERR_WIDTH (1U) 189 #define ACE_STATUS_KP_CRC_ERR(x) (((uint64_t)(((uint64_t)(x)) << ACE_STATUS_KP_CRC_ERR_SHIFT)) & ACE_STATUS_KP_CRC_ERR_MASK) 190 /*! @} */ 191 192 /*! @name CONTROL - Control */ 193 /*! @{ */ 194 195 #define ACE_CONTROL_ENABLE_MASK (0x1U) 196 #define ACE_CONTROL_ENABLE_SHIFT (0U) 197 #define ACE_CONTROL_ENABLE_WIDTH (1U) 198 #define ACE_CONTROL_ENABLE(x) (((uint64_t)(((uint64_t)(x)) << ACE_CONTROL_ENABLE_SHIFT)) & ACE_CONTROL_ENABLE_MASK) 199 200 #define ACE_CONTROL_RESET_MASK (0x2U) 201 #define ACE_CONTROL_RESET_SHIFT (1U) 202 #define ACE_CONTROL_RESET_WIDTH (1U) 203 #define ACE_CONTROL_RESET(x) (((uint64_t)(((uint64_t)(x)) << ACE_CONTROL_RESET_SHIFT)) & ACE_CONTROL_RESET_MASK) 204 205 #define ACE_CONTROL_MASK_MASK (0x1FCU) 206 #define ACE_CONTROL_MASK_SHIFT (2U) 207 #define ACE_CONTROL_MASK_WIDTH (7U) 208 #define ACE_CONTROL_MASK(x) (((uint64_t)(((uint64_t)(x)) << ACE_CONTROL_MASK_SHIFT)) & ACE_CONTROL_MASK_MASK) 209 /*! @} */ 210 211 /*! @name RESULT - Result */ 212 /*! @{ */ 213 214 #define ACE_RESULT_DATA_MASK (0xFFFFFFFFFFFFFFFFU) 215 #define ACE_RESULT_DATA_SHIFT (0U) 216 #define ACE_RESULT_DATA_WIDTH (64U) 217 #define ACE_RESULT_DATA(x) (((uint64_t)(((uint64_t)(x)) << ACE_RESULT_DATA_SHIFT)) & ACE_RESULT_DATA_MASK) 218 /*! @} */ 219 220 /*! @name AUTH_TAG - Auth Tag Output */ 221 /*! @{ */ 222 223 #define ACE_AUTH_TAG_DATA_MASK (0xFFFFFFFFFFFFFFFFU) 224 #define ACE_AUTH_TAG_DATA_SHIFT (0U) 225 #define ACE_AUTH_TAG_DATA_WIDTH (64U) 226 #define ACE_AUTH_TAG_DATA(x) (((uint64_t)(((uint64_t)(x)) << ACE_AUTH_TAG_DATA_SHIFT)) & ACE_AUTH_TAG_DATA_MASK) 227 /*! @} */ 228 229 /*! @name VERSION - ACE Version */ 230 /*! @{ */ 231 232 #define ACE_VERSION_EXT_REV_MASK (0xFU) 233 #define ACE_VERSION_EXT_REV_SHIFT (0U) 234 #define ACE_VERSION_EXT_REV_WIDTH (4U) 235 #define ACE_VERSION_EXT_REV(x) (((uint64_t)(((uint64_t)(x)) << ACE_VERSION_EXT_REV_SHIFT)) & ACE_VERSION_EXT_REV_MASK) 236 237 #define ACE_VERSION_MINOR_REV2_MASK (0xF0U) 238 #define ACE_VERSION_MINOR_REV2_SHIFT (4U) 239 #define ACE_VERSION_MINOR_REV2_WIDTH (4U) 240 #define ACE_VERSION_MINOR_REV2(x) (((uint64_t)(((uint64_t)(x)) << ACE_VERSION_MINOR_REV2_SHIFT)) & ACE_VERSION_MINOR_REV2_MASK) 241 242 #define ACE_VERSION_MINOR_REV1_MASK (0xF00U) 243 #define ACE_VERSION_MINOR_REV1_SHIFT (8U) 244 #define ACE_VERSION_MINOR_REV1_WIDTH (4U) 245 #define ACE_VERSION_MINOR_REV1(x) (((uint64_t)(((uint64_t)(x)) << ACE_VERSION_MINOR_REV1_SHIFT)) & ACE_VERSION_MINOR_REV1_MASK) 246 247 #define ACE_VERSION_MAJOR_REV_MASK (0xF000U) 248 #define ACE_VERSION_MAJOR_REV_SHIFT (12U) 249 #define ACE_VERSION_MAJOR_REV_WIDTH (4U) 250 #define ACE_VERSION_MAJOR_REV(x) (((uint64_t)(((uint64_t)(x)) << ACE_VERSION_MAJOR_REV_SHIFT)) & ACE_VERSION_MAJOR_REV_MASK) 251 252 #define ACE_VERSION_MILESTONE_MASK (0x30000U) 253 #define ACE_VERSION_MILESTONE_SHIFT (16U) 254 #define ACE_VERSION_MILESTONE_WIDTH (2U) 255 #define ACE_VERSION_MILESTONE(x) (((uint64_t)(((uint64_t)(x)) << ACE_VERSION_MILESTONE_SHIFT)) & ACE_VERSION_MILESTONE_MASK) 256 /*! @} */ 257 258 /*! 259 * @} 260 */ /* end of group ACE_Register_Masks */ 261 262 /*! 263 * @} 264 */ /* end of group ACE_Peripheral_Access_Layer */ 265 266 #endif /* #if !defined(S32Z2_ACE_H_) */ 267
