1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2021 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K344_VIRT_WRAPPER.h
10  * @version 1.9
11  * @date 2021-10-27
12  * @brief Peripheral Access Layer for S32K344_VIRT_WRAPPER
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K344_VIRT_WRAPPER_H_)  /* Check if memory map has not been already included */
58 #define S32K344_VIRT_WRAPPER_H_
59 
60 #include "S32K344_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- VIRT_WRAPPER Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup VIRT_WRAPPER_Peripheral_Access_Layer VIRT_WRAPPER Peripheral Access Layer
68  * @{
69  */
70 
71 /** VIRT_WRAPPER - Size of Registers Arrays */
72 #define VIRT_WRAPPER_REG_A_COUNT                  32u
73 #define VIRT_WRAPPER_REG_B_COUNT                  32u
74 #define VIRT_WRAPPER_REG_C_COUNT                  1u
75 #define VIRT_WRAPPER_REG_D_COUNT                  1u
76 
77 /** VIRT_WRAPPER - Register Layout Typedef */
78 typedef struct {
79   __IO uint32_t REG_A[VIRT_WRAPPER_REG_A_COUNT];   /**< Parameter_n Register, array offset: 0x0, array step: 0x4 */
80   __IO uint32_t REG_B[VIRT_WRAPPER_REG_B_COUNT];   /**< Parameter_n Register, array offset: 0x80, array step: 0x4 */
81   __IO uint32_t REG_C[VIRT_WRAPPER_REG_C_COUNT];   /**< Parameter_n Register, array offset: 0x100, array step: 0x4 */
82   __IO uint32_t REG_D[VIRT_WRAPPER_REG_D_COUNT];   /**< Parameter_n Register, array offset: 0x104, array step: 0x4 */
83 } VIRT_WRAPPER_Type, *VIRT_WRAPPER_MemMapPtr;
84 
85 /** Number of instances of the VIRT_WRAPPER module. */
86 #define VIRT_WRAPPER_INSTANCE_COUNT              (1u)
87 
88 /* VIRT_WRAPPER - Peripheral instance base addresses */
89 /** Peripheral VIRT_WRAPPER base address */
90 #define IP_VIRT_WRAPPER_BASE                     (0x402A8000u)
91 /** Peripheral VIRT_WRAPPER base pointer */
92 #define IP_VIRT_WRAPPER                          ((VIRT_WRAPPER_Type *)IP_VIRT_WRAPPER_BASE)
93 /** Array initializer of VIRT_WRAPPER peripheral base addresses */
94 #define IP_VIRT_WRAPPER_BASE_ADDRS               { IP_VIRT_WRAPPER_BASE }
95 /** Array initializer of VIRT_WRAPPER peripheral base pointers */
96 #define IP_VIRT_WRAPPER_BASE_PTRS                { IP_VIRT_WRAPPER }
97 
98 /* ----------------------------------------------------------------------------
99    -- VIRT_WRAPPER Register Masks
100    ---------------------------------------------------------------------------- */
101 
102 /*!
103  * @addtogroup VIRT_WRAPPER_Register_Masks VIRT_WRAPPER Register Masks
104  * @{
105  */
106 
107 /*! @name REG_A - Parameter_n Register */
108 /*! @{ */
109 
110 #define VIRT_WRAPPER_REG_A_PAD_0_MASK            (0x3U)
111 #define VIRT_WRAPPER_REG_A_PAD_0_SHIFT           (0U)
112 #define VIRT_WRAPPER_REG_A_PAD_0_WIDTH           (2U)
113 #define VIRT_WRAPPER_REG_A_PAD_0(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_0_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_0_MASK)
114 
115 #define VIRT_WRAPPER_REG_A_PAD_1_MASK            (0xCU)
116 #define VIRT_WRAPPER_REG_A_PAD_1_SHIFT           (2U)
117 #define VIRT_WRAPPER_REG_A_PAD_1_WIDTH           (2U)
118 #define VIRT_WRAPPER_REG_A_PAD_1(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_1_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_1_MASK)
119 
120 #define VIRT_WRAPPER_REG_A_PAD_2_MASK            (0x30U)
121 #define VIRT_WRAPPER_REG_A_PAD_2_SHIFT           (4U)
122 #define VIRT_WRAPPER_REG_A_PAD_2_WIDTH           (2U)
123 #define VIRT_WRAPPER_REG_A_PAD_2(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_2_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_2_MASK)
124 
125 #define VIRT_WRAPPER_REG_A_PAD_3_MASK            (0xC0U)
126 #define VIRT_WRAPPER_REG_A_PAD_3_SHIFT           (6U)
127 #define VIRT_WRAPPER_REG_A_PAD_3_WIDTH           (2U)
128 #define VIRT_WRAPPER_REG_A_PAD_3(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_3_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_3_MASK)
129 
130 #define VIRT_WRAPPER_REG_A_PAD_4_MASK            (0x300U)
131 #define VIRT_WRAPPER_REG_A_PAD_4_SHIFT           (8U)
132 #define VIRT_WRAPPER_REG_A_PAD_4_WIDTH           (2U)
133 #define VIRT_WRAPPER_REG_A_PAD_4(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_4_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_4_MASK)
134 
135 #define VIRT_WRAPPER_REG_A_PAD_5_MASK            (0xC00U)
136 #define VIRT_WRAPPER_REG_A_PAD_5_SHIFT           (10U)
137 #define VIRT_WRAPPER_REG_A_PAD_5_WIDTH           (2U)
138 #define VIRT_WRAPPER_REG_A_PAD_5(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_5_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_5_MASK)
139 
140 #define VIRT_WRAPPER_REG_A_PAD_6_MASK            (0x3000U)
141 #define VIRT_WRAPPER_REG_A_PAD_6_SHIFT           (12U)
142 #define VIRT_WRAPPER_REG_A_PAD_6_WIDTH           (2U)
143 #define VIRT_WRAPPER_REG_A_PAD_6(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_6_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_6_MASK)
144 
145 #define VIRT_WRAPPER_REG_A_PAD_7_MASK            (0xC000U)
146 #define VIRT_WRAPPER_REG_A_PAD_7_SHIFT           (14U)
147 #define VIRT_WRAPPER_REG_A_PAD_7_WIDTH           (2U)
148 #define VIRT_WRAPPER_REG_A_PAD_7(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_7_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_7_MASK)
149 
150 #define VIRT_WRAPPER_REG_A_PAD_8_MASK            (0x30000U)
151 #define VIRT_WRAPPER_REG_A_PAD_8_SHIFT           (16U)
152 #define VIRT_WRAPPER_REG_A_PAD_8_WIDTH           (2U)
153 #define VIRT_WRAPPER_REG_A_PAD_8(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_8_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_8_MASK)
154 
155 #define VIRT_WRAPPER_REG_A_PAD_9_MASK            (0xC0000U)
156 #define VIRT_WRAPPER_REG_A_PAD_9_SHIFT           (18U)
157 #define VIRT_WRAPPER_REG_A_PAD_9_WIDTH           (2U)
158 #define VIRT_WRAPPER_REG_A_PAD_9(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_9_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_9_MASK)
159 
160 #define VIRT_WRAPPER_REG_A_PAD_10_MASK           (0x300000U)
161 #define VIRT_WRAPPER_REG_A_PAD_10_SHIFT          (20U)
162 #define VIRT_WRAPPER_REG_A_PAD_10_WIDTH          (2U)
163 #define VIRT_WRAPPER_REG_A_PAD_10(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_10_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_10_MASK)
164 
165 #define VIRT_WRAPPER_REG_A_PAD_11_MASK           (0xC00000U)
166 #define VIRT_WRAPPER_REG_A_PAD_11_SHIFT          (22U)
167 #define VIRT_WRAPPER_REG_A_PAD_11_WIDTH          (2U)
168 #define VIRT_WRAPPER_REG_A_PAD_11(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_11_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_11_MASK)
169 
170 #define VIRT_WRAPPER_REG_A_PAD_12_MASK           (0x3000000U)
171 #define VIRT_WRAPPER_REG_A_PAD_12_SHIFT          (24U)
172 #define VIRT_WRAPPER_REG_A_PAD_12_WIDTH          (2U)
173 #define VIRT_WRAPPER_REG_A_PAD_12(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_12_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_12_MASK)
174 
175 #define VIRT_WRAPPER_REG_A_PAD_13_MASK           (0xC000000U)
176 #define VIRT_WRAPPER_REG_A_PAD_13_SHIFT          (26U)
177 #define VIRT_WRAPPER_REG_A_PAD_13_WIDTH          (2U)
178 #define VIRT_WRAPPER_REG_A_PAD_13(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_13_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_13_MASK)
179 
180 #define VIRT_WRAPPER_REG_A_PAD_14_MASK           (0x30000000U)
181 #define VIRT_WRAPPER_REG_A_PAD_14_SHIFT          (28U)
182 #define VIRT_WRAPPER_REG_A_PAD_14_WIDTH          (2U)
183 #define VIRT_WRAPPER_REG_A_PAD_14(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_14_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_14_MASK)
184 
185 #define VIRT_WRAPPER_REG_A_PAD_15_MASK           (0xC0000000U)
186 #define VIRT_WRAPPER_REG_A_PAD_15_SHIFT          (30U)
187 #define VIRT_WRAPPER_REG_A_PAD_15_WIDTH          (2U)
188 #define VIRT_WRAPPER_REG_A_PAD_15(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_A_PAD_15_SHIFT)) & VIRT_WRAPPER_REG_A_PAD_15_MASK)
189 /*! @} */
190 
191 /*! @name REG_B - Parameter_n Register */
192 /*! @{ */
193 
194 #define VIRT_WRAPPER_REG_B_INMUX_0_MASK          (0x3U)
195 #define VIRT_WRAPPER_REG_B_INMUX_0_SHIFT         (0U)
196 #define VIRT_WRAPPER_REG_B_INMUX_0_WIDTH         (2U)
197 #define VIRT_WRAPPER_REG_B_INMUX_0(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_0_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_0_MASK)
198 
199 #define VIRT_WRAPPER_REG_B_INMUX_1_MASK          (0xCU)
200 #define VIRT_WRAPPER_REG_B_INMUX_1_SHIFT         (2U)
201 #define VIRT_WRAPPER_REG_B_INMUX_1_WIDTH         (2U)
202 #define VIRT_WRAPPER_REG_B_INMUX_1(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_1_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_1_MASK)
203 
204 #define VIRT_WRAPPER_REG_B_INMUX_2_MASK          (0x30U)
205 #define VIRT_WRAPPER_REG_B_INMUX_2_SHIFT         (4U)
206 #define VIRT_WRAPPER_REG_B_INMUX_2_WIDTH         (2U)
207 #define VIRT_WRAPPER_REG_B_INMUX_2(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_2_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_2_MASK)
208 
209 #define VIRT_WRAPPER_REG_B_INMUX_3_MASK          (0xC0U)
210 #define VIRT_WRAPPER_REG_B_INMUX_3_SHIFT         (6U)
211 #define VIRT_WRAPPER_REG_B_INMUX_3_WIDTH         (2U)
212 #define VIRT_WRAPPER_REG_B_INMUX_3(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_3_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_3_MASK)
213 
214 #define VIRT_WRAPPER_REG_B_INMUX_4_MASK          (0x300U)
215 #define VIRT_WRAPPER_REG_B_INMUX_4_SHIFT         (8U)
216 #define VIRT_WRAPPER_REG_B_INMUX_4_WIDTH         (2U)
217 #define VIRT_WRAPPER_REG_B_INMUX_4(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_4_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_4_MASK)
218 
219 #define VIRT_WRAPPER_REG_B_INMUX_5_MASK          (0xC00U)
220 #define VIRT_WRAPPER_REG_B_INMUX_5_SHIFT         (10U)
221 #define VIRT_WRAPPER_REG_B_INMUX_5_WIDTH         (2U)
222 #define VIRT_WRAPPER_REG_B_INMUX_5(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_5_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_5_MASK)
223 
224 #define VIRT_WRAPPER_REG_B_INMUX_6_MASK          (0x3000U)
225 #define VIRT_WRAPPER_REG_B_INMUX_6_SHIFT         (12U)
226 #define VIRT_WRAPPER_REG_B_INMUX_6_WIDTH         (2U)
227 #define VIRT_WRAPPER_REG_B_INMUX_6(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_6_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_6_MASK)
228 
229 #define VIRT_WRAPPER_REG_B_INMUX_7_MASK          (0xC000U)
230 #define VIRT_WRAPPER_REG_B_INMUX_7_SHIFT         (14U)
231 #define VIRT_WRAPPER_REG_B_INMUX_7_WIDTH         (2U)
232 #define VIRT_WRAPPER_REG_B_INMUX_7(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_7_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_7_MASK)
233 
234 #define VIRT_WRAPPER_REG_B_INMUX_8_MASK          (0x30000U)
235 #define VIRT_WRAPPER_REG_B_INMUX_8_SHIFT         (16U)
236 #define VIRT_WRAPPER_REG_B_INMUX_8_WIDTH         (2U)
237 #define VIRT_WRAPPER_REG_B_INMUX_8(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_8_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_8_MASK)
238 
239 #define VIRT_WRAPPER_REG_B_INMUX_9_MASK          (0xC0000U)
240 #define VIRT_WRAPPER_REG_B_INMUX_9_SHIFT         (18U)
241 #define VIRT_WRAPPER_REG_B_INMUX_9_WIDTH         (2U)
242 #define VIRT_WRAPPER_REG_B_INMUX_9(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_9_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_9_MASK)
243 
244 #define VIRT_WRAPPER_REG_B_INMUX_10_MASK         (0x300000U)
245 #define VIRT_WRAPPER_REG_B_INMUX_10_SHIFT        (20U)
246 #define VIRT_WRAPPER_REG_B_INMUX_10_WIDTH        (2U)
247 #define VIRT_WRAPPER_REG_B_INMUX_10(x)           (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_10_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_10_MASK)
248 
249 #define VIRT_WRAPPER_REG_B_INMUX_11_MASK         (0xC00000U)
250 #define VIRT_WRAPPER_REG_B_INMUX_11_SHIFT        (22U)
251 #define VIRT_WRAPPER_REG_B_INMUX_11_WIDTH        (2U)
252 #define VIRT_WRAPPER_REG_B_INMUX_11(x)           (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_11_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_11_MASK)
253 
254 #define VIRT_WRAPPER_REG_B_INMUX_12_MASK         (0x3000000U)
255 #define VIRT_WRAPPER_REG_B_INMUX_12_SHIFT        (24U)
256 #define VIRT_WRAPPER_REG_B_INMUX_12_WIDTH        (2U)
257 #define VIRT_WRAPPER_REG_B_INMUX_12(x)           (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_12_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_12_MASK)
258 
259 #define VIRT_WRAPPER_REG_B_INMUX_13_MASK         (0xC000000U)
260 #define VIRT_WRAPPER_REG_B_INMUX_13_SHIFT        (26U)
261 #define VIRT_WRAPPER_REG_B_INMUX_13_WIDTH        (2U)
262 #define VIRT_WRAPPER_REG_B_INMUX_13(x)           (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_13_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_13_MASK)
263 
264 #define VIRT_WRAPPER_REG_B_INMUX_14_MASK         (0x30000000U)
265 #define VIRT_WRAPPER_REG_B_INMUX_14_SHIFT        (28U)
266 #define VIRT_WRAPPER_REG_B_INMUX_14_WIDTH        (2U)
267 #define VIRT_WRAPPER_REG_B_INMUX_14(x)           (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_14_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_14_MASK)
268 
269 #define VIRT_WRAPPER_REG_B_INMUX_15_MASK         (0xC0000000U)
270 #define VIRT_WRAPPER_REG_B_INMUX_15_SHIFT        (30U)
271 #define VIRT_WRAPPER_REG_B_INMUX_15_WIDTH        (2U)
272 #define VIRT_WRAPPER_REG_B_INMUX_15(x)           (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_B_INMUX_15_SHIFT)) & VIRT_WRAPPER_REG_B_INMUX_15_MASK)
273 /*! @} */
274 
275 /*! @name REG_C - Parameter_n Register */
276 /*! @{ */
277 
278 #define VIRT_WRAPPER_REG_C_INTC_CTRL_MASK        (0x3U)
279 #define VIRT_WRAPPER_REG_C_INTC_CTRL_SHIFT       (0U)
280 #define VIRT_WRAPPER_REG_C_INTC_CTRL_WIDTH       (2U)
281 #define VIRT_WRAPPER_REG_C_INTC_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_C_INTC_CTRL_SHIFT)) & VIRT_WRAPPER_REG_C_INTC_CTRL_MASK)
282 /*! @} */
283 
284 /*! @name REG_D - Parameter_n Register */
285 /*! @{ */
286 
287 #define VIRT_WRAPPER_REG_D_REG_GCR_MASK          (0xC0000000U)
288 #define VIRT_WRAPPER_REG_D_REG_GCR_SHIFT         (30U)
289 #define VIRT_WRAPPER_REG_D_REG_GCR_WIDTH         (2U)
290 #define VIRT_WRAPPER_REG_D_REG_GCR(x)            (((uint32_t)(((uint32_t)(x)) << VIRT_WRAPPER_REG_D_REG_GCR_SHIFT)) & VIRT_WRAPPER_REG_D_REG_GCR_MASK)
291 /*! @} */
292 
293 /*!
294  * @}
295  */ /* end of group VIRT_WRAPPER_Register_Masks */
296 
297 /*!
298  * @}
299  */ /* end of group VIRT_WRAPPER_Peripheral_Access_Layer */
300 
301 #endif  /* #if !defined(S32K344_VIRT_WRAPPER_H_) */
302