1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MPU.h 10 * @version 1.5 11 * @date 2020-11-11 12 * @brief Peripheral Access Layer for S32K344_MPU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MPU_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MPU_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_MPU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_MPU_Peripheral_Access_Layer S32_MPU Peripheral Access Layer 68 */ 69 /** S32_MPU - Size of Registers Arrays */ 70 #define S32_MPU_A_COUNT 3u 71 72 /** S32_MPU - Register Layout Typedef */ 73 typedef struct { 74 uint8_t RESERVED_0[3472]; 75 __I uint32_t TYPE; /**< MPU Type Register, offset: 0xD90 */ 76 __IO uint32_t CTRL; /**< MPU Control Register, offset: 0xD94 */ 77 __IO uint32_t RNR; /**< MPU Region Number Register, offset: 0xD98 */ 78 __IO uint32_t RBAR; /**< MPU Region Base Address Register, offset: 0xD9C */ 79 __IO uint32_t RASR; /**< MPU Region Attribute and Size Register, offset: 0xDA0 */ 80 struct { /* offset: 0xDA4, array step: 0x8 */ 81 __IO uint32_t RBAR; /**< Alias of RBAR0..Alias of RBAR2, array offset: 0xDA4, array step: 0x8 */ 82 __IO uint32_t RASR; /**< Alias of RASR0..Alias of RASR2, array offset: 0xDA8, array step: 0x8 */ 83 } A[S32_MPU_A_COUNT]; 84 } S32_MPU_Type, *S32_MPU_MemMapPtr; 85 86 /** Number of instances of the S32_MPU module. */ 87 #define S32_MPU_INSTANCE_COUNT (1u) 88 89 /* S32_MPU - Peripheral instance base addresses */ 90 /** Peripheral S32_MPU base address */ 91 #define S32_MPU_BASE (0xE000E000u) 92 /** Peripheral S32_MPU base pointer */ 93 #define S32_MPU ((S32_MPU_Type *)S32_MPU_BASE) 94 /** Array initializer of S32_MPU peripheral base addresses */ 95 #define S32_MPU_BASE_ADDRS { S32_MPU_BASE } 96 /** Array initializer of S32_MPU peripheral base pointers */ 97 #define S32_MPU_BASE_PTRS { S32_MPU } 98 99 /* ---------------------------------------------------------------------------- 100 -- S32_MPU Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup S32_MPU_Register_Masks S32_MPU Register Masks 105 * @{ 106 */ 107 108 /* TYPE Bit Fields */ 109 #define S32_MPU_TYPE_SEPARATE_MASK 0x1u 110 #define S32_MPU_TYPE_SEPARATE_SHIFT 0u 111 #define S32_MPU_TYPE_SEPARATE_WIDTH 1u 112 #define S32_MPU_TYPE_SEPARATE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_TYPE_SEPARATE_SHIFT))&S32_MPU_TYPE_SEPARATE_MASK) 113 #define S32_MPU_TYPE_DREGION_MASK 0xFF00u 114 #define S32_MPU_TYPE_DREGION_SHIFT 8u 115 #define S32_MPU_TYPE_DREGION_WIDTH 8u 116 #define S32_MPU_TYPE_DREGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_TYPE_DREGION_SHIFT))&S32_MPU_TYPE_DREGION_MASK) 117 #define S32_MPU_TYPE_IREGION_MASK 0xFF0000u 118 #define S32_MPU_TYPE_IREGION_SHIFT 16u 119 #define S32_MPU_TYPE_IREGION_WIDTH 8u 120 #define S32_MPU_TYPE_IREGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_TYPE_IREGION_SHIFT))&S32_MPU_TYPE_IREGION_MASK) 121 /* CTRL Bit Fields */ 122 #define S32_MPU_CTRL_ENABLE_MASK 0x1u 123 #define S32_MPU_CTRL_ENABLE_SHIFT 0u 124 #define S32_MPU_CTRL_ENABLE_WIDTH 1u 125 #define S32_MPU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_CTRL_ENABLE_SHIFT))&S32_MPU_CTRL_ENABLE_MASK) 126 #define S32_MPU_CTRL_HFNMIENA_MASK 0x2u 127 #define S32_MPU_CTRL_HFNMIENA_SHIFT 1u 128 #define S32_MPU_CTRL_HFNMIENA_WIDTH 1u 129 #define S32_MPU_CTRL_HFNMIENA(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_CTRL_HFNMIENA_SHIFT))&S32_MPU_CTRL_HFNMIENA_MASK) 130 #define S32_MPU_CTRL_PRIVDEFENA_MASK 0x4u 131 #define S32_MPU_CTRL_PRIVDEFENA_SHIFT 2u 132 #define S32_MPU_CTRL_PRIVDEFENA_WIDTH 1u 133 #define S32_MPU_CTRL_PRIVDEFENA(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_CTRL_PRIVDEFENA_SHIFT))&S32_MPU_CTRL_PRIVDEFENA_MASK) 134 /* RNR Bit Fields */ 135 #define S32_MPU_RNR_REGION_MASK 0xFFu 136 #define S32_MPU_RNR_REGION_SHIFT 0u 137 #define S32_MPU_RNR_REGION_WIDTH 8u 138 #define S32_MPU_RNR_REGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RNR_REGION_SHIFT))&S32_MPU_RNR_REGION_MASK) 139 /* RBAR Bit Fields */ 140 #define S32_MPU_RBAR_REGION_MASK 0xFu 141 #define S32_MPU_RBAR_REGION_SHIFT 0u 142 #define S32_MPU_RBAR_REGION_WIDTH 4u 143 #define S32_MPU_RBAR_REGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_REGION_SHIFT))&S32_MPU_RBAR_REGION_MASK) 144 #define S32_MPU_RBAR_VALID_MASK 0x10u 145 #define S32_MPU_RBAR_VALID_SHIFT 4u 146 #define S32_MPU_RBAR_VALID_WIDTH 1u 147 #define S32_MPU_RBAR_VALID(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_VALID_SHIFT))&S32_MPU_RBAR_VALID_MASK) 148 #define S32_MPU_RBAR_ADDR_MASK 0xFFFFFFE0u 149 #define S32_MPU_RBAR_ADDR_SHIFT 5u 150 #define S32_MPU_RBAR_ADDR_WIDTH 27u 151 #define S32_MPU_RBAR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_ADDR_SHIFT))&S32_MPU_RBAR_ADDR_MASK) 152 /* RASR Bit Fields */ 153 #define S32_MPU_RASR_ENABLE_MASK 0x1u 154 #define S32_MPU_RASR_ENABLE_SHIFT 0u 155 #define S32_MPU_RASR_ENABLE_WIDTH 1u 156 #define S32_MPU_RASR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_ENABLE_SHIFT))&S32_MPU_RASR_ENABLE_MASK) 157 #define S32_MPU_RASR_SIZE_MASK 0x3Eu 158 #define S32_MPU_RASR_SIZE_SHIFT 1u 159 #define S32_MPU_RASR_SIZE_WIDTH 5u 160 #define S32_MPU_RASR_SIZE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_SIZE_SHIFT))&S32_MPU_RASR_SIZE_MASK) 161 #define S32_MPU_RASR_SRD_MASK 0xFF00u 162 #define S32_MPU_RASR_SRD_SHIFT 8u 163 #define S32_MPU_RASR_SRD_WIDTH 8u 164 #define S32_MPU_RASR_SRD(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_SRD_SHIFT))&S32_MPU_RASR_SRD_MASK) 165 #define S32_MPU_RASR_B_MASK 0x10000u 166 #define S32_MPU_RASR_B_SHIFT 16u 167 #define S32_MPU_RASR_B_WIDTH 1u 168 #define S32_MPU_RASR_B(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_B_SHIFT))&S32_MPU_RASR_B_MASK) 169 #define S32_MPU_RASR_C_MASK 0x20000u 170 #define S32_MPU_RASR_C_SHIFT 17u 171 #define S32_MPU_RASR_C_WIDTH 1u 172 #define S32_MPU_RASR_C(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_C_SHIFT))&S32_MPU_RASR_C_MASK) 173 #define S32_MPU_RASR_S_MASK 0x40000u 174 #define S32_MPU_RASR_S_SHIFT 18u 175 #define S32_MPU_RASR_S_WIDTH 1u 176 #define S32_MPU_RASR_S(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_S_SHIFT))&S32_MPU_RASR_S_MASK) 177 #define S32_MPU_RASR_TEX_MASK 0x380000u 178 #define S32_MPU_RASR_TEX_SHIFT 19u 179 #define S32_MPU_RASR_TEX_WIDTH 3u 180 #define S32_MPU_RASR_TEX(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_TEX_SHIFT))&S32_MPU_RASR_TEX_MASK) 181 #define S32_MPU_RASR_AP_MASK 0x7000000u 182 #define S32_MPU_RASR_AP_SHIFT 24u 183 #define S32_MPU_RASR_AP_WIDTH 3u 184 #define S32_MPU_RASR_AP(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_AP_SHIFT))&S32_MPU_RASR_AP_MASK) 185 #define S32_MPU_RASR_XN_MASK 0x10000000u 186 #define S32_MPU_RASR_XN_SHIFT 28u 187 #define S32_MPU_RASR_XN_WIDTH 1u 188 #define S32_MPU_RASR_XN(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RASR_XN_SHIFT))&S32_MPU_RASR_XN_MASK) 189 /* A_RBAR Bit Fields */ 190 #define S32_MPU_A_RBAR_REGION_MASK 0xFu 191 #define S32_MPU_A_RBAR_REGION_SHIFT 0u 192 #define S32_MPU_A_RBAR_REGION_WIDTH 4u 193 #define S32_MPU_A_RBAR_REGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RBAR_REGION_SHIFT))&S32_MPU_A_RBAR_REGION_MASK) 194 #define S32_MPU_A_RBAR_VALID_MASK 0x10u 195 #define S32_MPU_A_RBAR_VALID_SHIFT 4u 196 #define S32_MPU_A_RBAR_VALID_WIDTH 1u 197 #define S32_MPU_A_RBAR_VALID(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RBAR_VALID_SHIFT))&S32_MPU_A_RBAR_VALID_MASK) 198 #define S32_MPU_A_RBAR_ADDR_MASK 0xFFFFFFE0u 199 #define S32_MPU_A_RBAR_ADDR_SHIFT 5u 200 #define S32_MPU_A_RBAR_ADDR_WIDTH 27u 201 #define S32_MPU_A_RBAR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RBAR_ADDR_SHIFT))&S32_MPU_A_RBAR_ADDR_MASK) 202 /* A_RASR Bit Fields */ 203 #define S32_MPU_A_RASR_ENABLE_MASK 0x1u 204 #define S32_MPU_A_RASR_ENABLE_SHIFT 0u 205 #define S32_MPU_A_RASR_ENABLE_WIDTH 1u 206 #define S32_MPU_A_RASR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_ENABLE_SHIFT))&S32_MPU_A_RASR_ENABLE_MASK) 207 #define S32_MPU_A_RASR_SIZE_MASK 0x3Eu 208 #define S32_MPU_A_RASR_SIZE_SHIFT 1u 209 #define S32_MPU_A_RASR_SIZE_WIDTH 5u 210 #define S32_MPU_A_RASR_SIZE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_SIZE_SHIFT))&S32_MPU_A_RASR_SIZE_MASK) 211 #define S32_MPU_A_RASR_SRD_MASK 0xFF00u 212 #define S32_MPU_A_RASR_SRD_SHIFT 8u 213 #define S32_MPU_A_RASR_SRD_WIDTH 8u 214 #define S32_MPU_A_RASR_SRD(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_SRD_SHIFT))&S32_MPU_A_RASR_SRD_MASK) 215 #define S32_MPU_A_RASR_B_MASK 0x10000u 216 #define S32_MPU_A_RASR_B_SHIFT 16u 217 #define S32_MPU_A_RASR_B_WIDTH 1u 218 #define S32_MPU_A_RASR_B(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_B_SHIFT))&S32_MPU_A_RASR_B_MASK) 219 #define S32_MPU_A_RASR_C_MASK 0x20000u 220 #define S32_MPU_A_RASR_C_SHIFT 17u 221 #define S32_MPU_A_RASR_C_WIDTH 1u 222 #define S32_MPU_A_RASR_C(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_C_SHIFT))&S32_MPU_A_RASR_C_MASK) 223 #define S32_MPU_A_RASR_S_MASK 0x40000u 224 #define S32_MPU_A_RASR_S_SHIFT 18u 225 #define S32_MPU_A_RASR_S_WIDTH 1u 226 #define S32_MPU_A_RASR_S(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_S_SHIFT))&S32_MPU_A_RASR_S_MASK) 227 #define S32_MPU_A_RASR_TEX_MASK 0x380000u 228 #define S32_MPU_A_RASR_TEX_SHIFT 19u 229 #define S32_MPU_A_RASR_TEX_WIDTH 3u 230 #define S32_MPU_A_RASR_TEX(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_TEX_SHIFT))&S32_MPU_A_RASR_TEX_MASK) 231 #define S32_MPU_A_RASR_AP_MASK 0x7000000u 232 #define S32_MPU_A_RASR_AP_SHIFT 24u 233 #define S32_MPU_A_RASR_AP_WIDTH 3u 234 #define S32_MPU_A_RASR_AP(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_AP_SHIFT))&S32_MPU_A_RASR_AP_MASK) 235 #define S32_MPU_A_RASR_XN_MASK 0x10000000u 236 #define S32_MPU_A_RASR_XN_SHIFT 28u 237 #define S32_MPU_A_RASR_XN_WIDTH 1u 238 #define S32_MPU_A_RASR_XN(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RASR_XN_SHIFT))&S32_MPU_A_RASR_XN_MASK) 239 240 /*! 241 * @} 242 */ /* end of group S32_MPU_Register_Masks */ 243 244 /*! 245 * @} 246 */ /* end of group S32_MPU_Peripheral_Access_Layer */ 247 248 #endif /* #if !defined(S32K344_MPU_H_) */ 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