1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2021 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K344_INTM.h
10  * @version 1.9
11  * @date 2021-10-27
12  * @brief Peripheral Access Layer for S32K344_INTM
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K344_INTM_H_)  /* Check if memory map has not been already included */
58 #define S32K344_INTM_H_
59 
60 #include "S32K344_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- INTM Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer
68  * @{
69  */
70 
71 /** INTM - Size of Registers Arrays */
72 #define INTM_MON_COUNT                            4u
73 
74 /** INTM - Register Layout Typedef */
75 typedef struct {
76   __IO uint32_t INTM_MM;                           /**< Monitor Mode, offset: 0x0 */
77   __O  uint32_t INTM_IACK;                         /**< Interrupt Acknowledge, offset: 0x4 */
78   struct {                                         /* offset: 0x8, array step: 0x10 */
79     __IO uint32_t INTM_IRQSEL;                       /**< Interrupt Request Select 0..Interrupt Request Select 3, array offset: 0x8, array step: 0x10 */
80     __IO uint32_t INTM_LATENCY;                      /**< INTM_LATENCY0..INTM_LATENCY3, array offset: 0xC, array step: 0x10 */
81     __IO uint32_t INTM_TIMER;                        /**< Timer 0..Timer 3, array offset: 0x10, array step: 0x10 */
82     __I  uint32_t INTM_STATUS;                       /**< Status 0..Status 3, array offset: 0x14, array step: 0x10 */
83   } MON[INTM_MON_COUNT];
84 } INTM_Type, *INTM_MemMapPtr;
85 
86 /** Number of instances of the INTM module. */
87 #define INTM_INSTANCE_COUNT                      (1u)
88 
89 /* INTM - Peripheral instance base addresses */
90 /** Peripheral INTM base address */
91 #define IP_INTM_BASE                             (0x4027C000u)
92 /** Peripheral INTM base pointer */
93 #define IP_INTM                                  ((INTM_Type *)IP_INTM_BASE)
94 /** Array initializer of INTM peripheral base addresses */
95 #define IP_INTM_BASE_ADDRS                       { IP_INTM_BASE }
96 /** Array initializer of INTM peripheral base pointers */
97 #define IP_INTM_BASE_PTRS                        { IP_INTM }
98 
99 /* ----------------------------------------------------------------------------
100    -- INTM Register Masks
101    ---------------------------------------------------------------------------- */
102 
103 /*!
104  * @addtogroup INTM_Register_Masks INTM Register Masks
105  * @{
106  */
107 
108 /*! @name INTM_MM - Monitor Mode */
109 /*! @{ */
110 
111 #define INTM_INTM_MM_MM_MASK                     (0x1U)
112 #define INTM_INTM_MM_MM_SHIFT                    (0U)
113 #define INTM_INTM_MM_MM_WIDTH                    (1U)
114 #define INTM_INTM_MM_MM(x)                       (((uint32_t)(((uint32_t)(x)) << INTM_INTM_MM_MM_SHIFT)) & INTM_INTM_MM_MM_MASK)
115 /*! @} */
116 
117 /*! @name INTM_IACK - Interrupt Acknowledge */
118 /*! @{ */
119 
120 #define INTM_INTM_IACK_IRQ_MASK                  (0x3FFU)
121 #define INTM_INTM_IACK_IRQ_SHIFT                 (0U)
122 #define INTM_INTM_IACK_IRQ_WIDTH                 (10U)
123 #define INTM_INTM_IACK_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IACK_IRQ_SHIFT)) & INTM_INTM_IACK_IRQ_MASK)
124 /*! @} */
125 
126 /*! @name INTM_IRQSEL - Interrupt Request Select 0..Interrupt Request Select 3 */
127 /*! @{ */
128 
129 #define INTM_INTM_IRQSEL_IRQ_MASK                (0x3FFU)
130 #define INTM_INTM_IRQSEL_IRQ_SHIFT               (0U)
131 #define INTM_INTM_IRQSEL_IRQ_WIDTH               (10U)
132 #define INTM_INTM_IRQSEL_IRQ(x)                  (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IRQSEL_IRQ_SHIFT)) & INTM_INTM_IRQSEL_IRQ_MASK)
133 /*! @} */
134 
135 /*! @name INTM_LATENCY - INTM_LATENCY0..INTM_LATENCY3 */
136 /*! @{ */
137 
138 #define INTM_INTM_LATENCY_LAT_MASK               (0xFFFFFFU)
139 #define INTM_INTM_LATENCY_LAT_SHIFT              (0U)
140 #define INTM_INTM_LATENCY_LAT_WIDTH              (24U)
141 #define INTM_INTM_LATENCY_LAT(x)                 (((uint32_t)(((uint32_t)(x)) << INTM_INTM_LATENCY_LAT_SHIFT)) & INTM_INTM_LATENCY_LAT_MASK)
142 /*! @} */
143 
144 /*! @name INTM_TIMER - Timer 0..Timer 3 */
145 /*! @{ */
146 
147 #define INTM_INTM_TIMER_TIMER_MASK               (0xFFFFFFU)
148 #define INTM_INTM_TIMER_TIMER_SHIFT              (0U)
149 #define INTM_INTM_TIMER_TIMER_WIDTH              (24U)
150 #define INTM_INTM_TIMER_TIMER(x)                 (((uint32_t)(((uint32_t)(x)) << INTM_INTM_TIMER_TIMER_SHIFT)) & INTM_INTM_TIMER_TIMER_MASK)
151 /*! @} */
152 
153 /*! @name INTM_STATUS - Status 0..Status 3 */
154 /*! @{ */
155 
156 #define INTM_INTM_STATUS_STATUS_MASK             (0x1U)
157 #define INTM_INTM_STATUS_STATUS_SHIFT            (0U)
158 #define INTM_INTM_STATUS_STATUS_WIDTH            (1U)
159 #define INTM_INTM_STATUS_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << INTM_INTM_STATUS_STATUS_SHIFT)) & INTM_INTM_STATUS_STATUS_MASK)
160 /*! @} */
161 
162 /*!
163  * @}
164  */ /* end of group INTM_Register_Masks */
165 
166 /*!
167  * @}
168  */ /* end of group INTM_Peripheral_Access_Layer */
169 
170 #endif  /* #if !defined(S32K344_INTM_H_) */
171