1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_DCM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_DCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_DCM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_DCM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DCM_Peripheral_Access_Layer DCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DCM - Size of Registers Arrays */ 72 #define DCM_DCMSRR_COUNT 16u 73 74 /** DCM - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t DCMSTAT; /**< DCM Status, offset: 0x0 */ 77 __IO uint32_t DCMLCC; /**< LC and LC Control, offset: 0x4 */ 78 __IO uint32_t DCMLCS; /**< LC Scan Status, offset: 0x8 */ 79 uint8_t RESERVED_0[16]; 80 __IO uint32_t DCMMISC; /**< DCM Miscellaneous, offset: 0x1C */ 81 __I uint32_t DCMDEB; /**< Debug Status and Configuration, offset: 0x20 */ 82 uint8_t RESERVED_1[8]; 83 __I uint32_t DCMEC; /**< DCF Error Count, offset: 0x2C */ 84 __IO uint32_t DCMSRR[DCM_DCMSRR_COUNT]; /**< DCF Scan Report, array offset: 0x30, array step: 0x4 */ 85 uint8_t RESERVED_2[16]; 86 __IO uint32_t DCMLCS_2; /**< LC Scan Status 2, offset: 0x80 */ 87 } DCM_Type, *DCM_MemMapPtr; 88 89 /** Number of instances of the DCM module. */ 90 #define DCM_INSTANCE_COUNT (1u) 91 92 /* DCM - Peripheral instance base addresses */ 93 /** Peripheral DCM base address */ 94 #define IP_DCM_BASE (0x402AC000u) 95 /** Peripheral DCM base pointer */ 96 #define IP_DCM ((DCM_Type *)IP_DCM_BASE) 97 /** Array initializer of DCM peripheral base addresses */ 98 #define IP_DCM_BASE_ADDRS { IP_DCM_BASE } 99 /** Array initializer of DCM peripheral base pointers */ 100 #define IP_DCM_BASE_PTRS { IP_DCM } 101 102 /* ---------------------------------------------------------------------------- 103 -- DCM Register Masks 104 ---------------------------------------------------------------------------- */ 105 106 /*! 107 * @addtogroup DCM_Register_Masks DCM Register Masks 108 * @{ 109 */ 110 111 /*! @name DCMSTAT - DCM Status */ 112 /*! @{ */ 113 114 #define DCM_DCMSTAT_DCMDONE_MASK (0x1U) 115 #define DCM_DCMSTAT_DCMDONE_SHIFT (0U) 116 #define DCM_DCMSTAT_DCMDONE_WIDTH (1U) 117 #define DCM_DCMSTAT_DCMDONE(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSTAT_DCMDONE_SHIFT)) & DCM_DCMSTAT_DCMDONE_MASK) 118 119 #define DCM_DCMSTAT_DCMERR_MASK (0x2U) 120 #define DCM_DCMSTAT_DCMERR_SHIFT (1U) 121 #define DCM_DCMSTAT_DCMERR_WIDTH (1U) 122 #define DCM_DCMSTAT_DCMERR(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSTAT_DCMERR_SHIFT)) & DCM_DCMSTAT_DCMERR_MASK) 123 124 #define DCM_DCMSTAT_DCMLCST_MASK (0x10U) 125 #define DCM_DCMSTAT_DCMLCST_SHIFT (4U) 126 #define DCM_DCMSTAT_DCMLCST_WIDTH (1U) 127 #define DCM_DCMSTAT_DCMLCST(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSTAT_DCMLCST_SHIFT)) & DCM_DCMSTAT_DCMLCST_MASK) 128 129 #define DCM_DCMSTAT_DCMUTS_MASK (0x100U) 130 #define DCM_DCMSTAT_DCMUTS_SHIFT (8U) 131 #define DCM_DCMSTAT_DCMUTS_WIDTH (1U) 132 #define DCM_DCMSTAT_DCMUTS(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSTAT_DCMUTS_SHIFT)) & DCM_DCMSTAT_DCMUTS_MASK) 133 134 #define DCM_DCMSTAT_DCMOTAS_MASK (0x200U) 135 #define DCM_DCMSTAT_DCMOTAS_SHIFT (9U) 136 #define DCM_DCMSTAT_DCMOTAS_WIDTH (1U) 137 #define DCM_DCMSTAT_DCMOTAS(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSTAT_DCMOTAS_SHIFT)) & DCM_DCMSTAT_DCMOTAS_MASK) 138 139 #define DCM_DCMSTAT_DCMDBGPS_MASK (0x400U) 140 #define DCM_DCMSTAT_DCMDBGPS_SHIFT (10U) 141 #define DCM_DCMSTAT_DCMDBGPS_WIDTH (1U) 142 #define DCM_DCMSTAT_DCMDBGPS(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSTAT_DCMDBGPS_SHIFT)) & DCM_DCMSTAT_DCMDBGPS_MASK) 143 /*! @} */ 144 145 /*! @name DCMLCC - LC and LC Control */ 146 /*! @{ */ 147 148 #define DCM_DCMLCC_DCMCLC_MASK (0x7U) 149 #define DCM_DCMLCC_DCMCLC_SHIFT (0U) 150 #define DCM_DCMLCC_DCMCLC_WIDTH (3U) 151 #define DCM_DCMLCC_DCMCLC(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCC_DCMCLC_SHIFT)) & DCM_DCMLCC_DCMCLC_MASK) 152 153 #define DCM_DCMLCC_DCMLCFN_MASK (0x8U) 154 #define DCM_DCMLCC_DCMLCFN_SHIFT (3U) 155 #define DCM_DCMLCC_DCMLCFN_WIDTH (1U) 156 #define DCM_DCMLCC_DCMLCFN(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCC_DCMLCFN_SHIFT)) & DCM_DCMLCC_DCMLCFN_MASK) 157 158 #define DCM_DCMLCC_DCMRLC_MASK (0x70U) 159 #define DCM_DCMLCC_DCMRLC_SHIFT (4U) 160 #define DCM_DCMLCC_DCMRLC_WIDTH (3U) 161 #define DCM_DCMLCC_DCMRLC(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCC_DCMRLC_SHIFT)) & DCM_DCMLCC_DCMRLC_MASK) 162 163 #define DCM_DCMLCC_DCMFLC_MASK (0x300U) 164 #define DCM_DCMLCC_DCMFLC_SHIFT (8U) 165 #define DCM_DCMLCC_DCMFLC_WIDTH (2U) 166 #define DCM_DCMLCC_DCMFLC(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCC_DCMFLC_SHIFT)) & DCM_DCMLCC_DCMFLC_MASK) 167 /*! @} */ 168 169 /*! @name DCMLCS - LC Scan Status */ 170 /*! @{ */ 171 172 #define DCM_DCMLCS_DCMLCSS1_MASK (0x1U) 173 #define DCM_DCMLCS_DCMLCSS1_SHIFT (0U) 174 #define DCM_DCMLCS_DCMLCSS1_WIDTH (1U) 175 #define DCM_DCMLCS_DCMLCSS1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCSS1_SHIFT)) & DCM_DCMLCS_DCMLCSS1_MASK) 176 177 #define DCM_DCMLCS_DCMLCC1_MASK (0xEU) 178 #define DCM_DCMLCS_DCMLCC1_SHIFT (1U) 179 #define DCM_DCMLCS_DCMLCC1_WIDTH (3U) 180 #define DCM_DCMLCS_DCMLCC1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCC1_SHIFT)) & DCM_DCMLCS_DCMLCC1_MASK) 181 182 #define DCM_DCMLCS_DCMLCE1_MASK (0x10U) 183 #define DCM_DCMLCS_DCMLCE1_SHIFT (4U) 184 #define DCM_DCMLCS_DCMLCE1_WIDTH (1U) 185 #define DCM_DCMLCS_DCMLCE1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCE1_SHIFT)) & DCM_DCMLCS_DCMLCE1_MASK) 186 187 #define DCM_DCMLCS_DCMLCFE1_MASK (0x20U) 188 #define DCM_DCMLCS_DCMLCFE1_SHIFT (5U) 189 #define DCM_DCMLCS_DCMLCFE1_WIDTH (1U) 190 #define DCM_DCMLCS_DCMLCFE1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCFE1_SHIFT)) & DCM_DCMLCS_DCMLCFE1_MASK) 191 192 #define DCM_DCMLCS_DCMLCSS2_MASK (0x40U) 193 #define DCM_DCMLCS_DCMLCSS2_SHIFT (6U) 194 #define DCM_DCMLCS_DCMLCSS2_WIDTH (1U) 195 #define DCM_DCMLCS_DCMLCSS2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCSS2_SHIFT)) & DCM_DCMLCS_DCMLCSS2_MASK) 196 197 #define DCM_DCMLCS_DCMLCC2_MASK (0x380U) 198 #define DCM_DCMLCS_DCMLCC2_SHIFT (7U) 199 #define DCM_DCMLCS_DCMLCC2_WIDTH (3U) 200 #define DCM_DCMLCS_DCMLCC2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCC2_SHIFT)) & DCM_DCMLCS_DCMLCC2_MASK) 201 202 #define DCM_DCMLCS_DCMLCE2_MASK (0x400U) 203 #define DCM_DCMLCS_DCMLCE2_SHIFT (10U) 204 #define DCM_DCMLCS_DCMLCE2_WIDTH (1U) 205 #define DCM_DCMLCS_DCMLCE2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCE2_SHIFT)) & DCM_DCMLCS_DCMLCE2_MASK) 206 207 #define DCM_DCMLCS_DCMLCFE2_MASK (0x800U) 208 #define DCM_DCMLCS_DCMLCFE2_SHIFT (11U) 209 #define DCM_DCMLCS_DCMLCFE2_WIDTH (1U) 210 #define DCM_DCMLCS_DCMLCFE2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCFE2_SHIFT)) & DCM_DCMLCS_DCMLCFE2_MASK) 211 212 #define DCM_DCMLCS_DCMLCSS3_MASK (0x1000U) 213 #define DCM_DCMLCS_DCMLCSS3_SHIFT (12U) 214 #define DCM_DCMLCS_DCMLCSS3_WIDTH (1U) 215 #define DCM_DCMLCS_DCMLCSS3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCSS3_SHIFT)) & DCM_DCMLCS_DCMLCSS3_MASK) 216 217 #define DCM_DCMLCS_DCMLCC3_MASK (0xE000U) 218 #define DCM_DCMLCS_DCMLCC3_SHIFT (13U) 219 #define DCM_DCMLCS_DCMLCC3_WIDTH (3U) 220 #define DCM_DCMLCS_DCMLCC3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCC3_SHIFT)) & DCM_DCMLCS_DCMLCC3_MASK) 221 222 #define DCM_DCMLCS_DCMLCE3_MASK (0x10000U) 223 #define DCM_DCMLCS_DCMLCE3_SHIFT (16U) 224 #define DCM_DCMLCS_DCMLCE3_WIDTH (1U) 225 #define DCM_DCMLCS_DCMLCE3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCE3_SHIFT)) & DCM_DCMLCS_DCMLCE3_MASK) 226 227 #define DCM_DCMLCS_DCMLCFE3_MASK (0x20000U) 228 #define DCM_DCMLCS_DCMLCFE3_SHIFT (17U) 229 #define DCM_DCMLCS_DCMLCFE3_WIDTH (1U) 230 #define DCM_DCMLCS_DCMLCFE3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCFE3_SHIFT)) & DCM_DCMLCS_DCMLCFE3_MASK) 231 232 #define DCM_DCMLCS_DCMLCSS4_MASK (0x40000U) 233 #define DCM_DCMLCS_DCMLCSS4_SHIFT (18U) 234 #define DCM_DCMLCS_DCMLCSS4_WIDTH (1U) 235 #define DCM_DCMLCS_DCMLCSS4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCSS4_SHIFT)) & DCM_DCMLCS_DCMLCSS4_MASK) 236 237 #define DCM_DCMLCS_DCMLCC4_MASK (0x380000U) 238 #define DCM_DCMLCS_DCMLCC4_SHIFT (19U) 239 #define DCM_DCMLCS_DCMLCC4_WIDTH (3U) 240 #define DCM_DCMLCS_DCMLCC4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCC4_SHIFT)) & DCM_DCMLCS_DCMLCC4_MASK) 241 242 #define DCM_DCMLCS_DCMLCE4_MASK (0x400000U) 243 #define DCM_DCMLCS_DCMLCE4_SHIFT (22U) 244 #define DCM_DCMLCS_DCMLCE4_WIDTH (1U) 245 #define DCM_DCMLCS_DCMLCE4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCE4_SHIFT)) & DCM_DCMLCS_DCMLCE4_MASK) 246 247 #define DCM_DCMLCS_DCMLCFE4_MASK (0x800000U) 248 #define DCM_DCMLCS_DCMLCFE4_SHIFT (23U) 249 #define DCM_DCMLCS_DCMLCFE4_WIDTH (1U) 250 #define DCM_DCMLCS_DCMLCFE4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCFE4_SHIFT)) & DCM_DCMLCS_DCMLCFE4_MASK) 251 252 #define DCM_DCMLCS_DCMLCSS5_MASK (0x1000000U) 253 #define DCM_DCMLCS_DCMLCSS5_SHIFT (24U) 254 #define DCM_DCMLCS_DCMLCSS5_WIDTH (1U) 255 #define DCM_DCMLCS_DCMLCSS5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCSS5_SHIFT)) & DCM_DCMLCS_DCMLCSS5_MASK) 256 257 #define DCM_DCMLCS_DCMLCC5_MASK (0xE000000U) 258 #define DCM_DCMLCS_DCMLCC5_SHIFT (25U) 259 #define DCM_DCMLCS_DCMLCC5_WIDTH (3U) 260 #define DCM_DCMLCS_DCMLCC5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCC5_SHIFT)) & DCM_DCMLCS_DCMLCC5_MASK) 261 262 #define DCM_DCMLCS_DCMLCE5_MASK (0x10000000U) 263 #define DCM_DCMLCS_DCMLCE5_SHIFT (28U) 264 #define DCM_DCMLCS_DCMLCE5_WIDTH (1U) 265 #define DCM_DCMLCS_DCMLCE5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCE5_SHIFT)) & DCM_DCMLCS_DCMLCE5_MASK) 266 267 #define DCM_DCMLCS_DCMLCFE5_MASK (0x20000000U) 268 #define DCM_DCMLCS_DCMLCFE5_SHIFT (29U) 269 #define DCM_DCMLCS_DCMLCFE5_WIDTH (1U) 270 #define DCM_DCMLCS_DCMLCFE5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_DCMLCFE5_SHIFT)) & DCM_DCMLCS_DCMLCFE5_MASK) 271 /*! @} */ 272 273 /*! @name DCMMISC - DCM Miscellaneous */ 274 /*! @{ */ 275 276 #define DCM_DCMMISC_DCMDBGT_MASK (0x400U) 277 #define DCM_DCMMISC_DCMDBGT_SHIFT (10U) 278 #define DCM_DCMMISC_DCMDBGT_WIDTH (1U) 279 #define DCM_DCMMISC_DCMDBGT(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMMISC_DCMDBGT_SHIFT)) & DCM_DCMMISC_DCMDBGT_MASK) 280 281 #define DCM_DCMMISC_DCMDBGE_MASK (0x800U) 282 #define DCM_DCMMISC_DCMDBGE_SHIFT (11U) 283 #define DCM_DCMMISC_DCMDBGE_WIDTH (1U) 284 #define DCM_DCMMISC_DCMDBGE(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMMISC_DCMDBGE_SHIFT)) & DCM_DCMMISC_DCMDBGE_MASK) 285 286 #define DCM_DCMMISC_DCMCERS_MASK (0x10000000U) 287 #define DCM_DCMMISC_DCMCERS_SHIFT (28U) 288 #define DCM_DCMMISC_DCMCERS_WIDTH (1U) 289 #define DCM_DCMMISC_DCMCERS(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMMISC_DCMCERS_SHIFT)) & DCM_DCMMISC_DCMCERS_MASK) 290 /*! @} */ 291 292 /*! @name DCMDEB - Debug Status and Configuration */ 293 /*! @{ */ 294 295 #define DCM_DCMDEB_DCM_APPDBG_STAT_MASK (0x2U) 296 #define DCM_DCMDEB_DCM_APPDBG_STAT_SHIFT (1U) 297 #define DCM_DCMDEB_DCM_APPDBG_STAT_WIDTH (1U) 298 #define DCM_DCMDEB_DCM_APPDBG_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMDEB_DCM_APPDBG_STAT_SHIFT)) & DCM_DCMDEB_DCM_APPDBG_STAT_MASK) 299 300 #define DCM_DCMDEB_APPDBG_STAT_SOC_MASK (0x10000U) 301 #define DCM_DCMDEB_APPDBG_STAT_SOC_SHIFT (16U) 302 #define DCM_DCMDEB_APPDBG_STAT_SOC_WIDTH (1U) 303 #define DCM_DCMDEB_APPDBG_STAT_SOC(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMDEB_APPDBG_STAT_SOC_SHIFT)) & DCM_DCMDEB_APPDBG_STAT_SOC_MASK) 304 /*! @} */ 305 306 /*! @name DCMEC - DCF Error Count */ 307 /*! @{ */ 308 309 #define DCM_DCMEC_DCMECT_MASK (0xFFFFU) 310 #define DCM_DCMEC_DCMECT_SHIFT (0U) 311 #define DCM_DCMEC_DCMECT_WIDTH (16U) 312 #define DCM_DCMEC_DCMECT(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMEC_DCMECT_SHIFT)) & DCM_DCMEC_DCMECT_MASK) 313 /*! @} */ 314 315 /*! @name DCMSRR - DCF Scan Report */ 316 /*! @{ */ 317 318 #define DCM_DCMSRR_DCMDCFE1_MASK (0x1FFFFFU) 319 #define DCM_DCMSRR_DCMDCFE1_SHIFT (0U) 320 #define DCM_DCMSRR_DCMDCFE1_WIDTH (21U) 321 #define DCM_DCMSRR_DCMDCFE1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE1_SHIFT)) & DCM_DCMSRR_DCMDCFE1_MASK) 322 323 #define DCM_DCMSRR_DCMDCFF1_MASK (0x7000000U) 324 #define DCM_DCMSRR_DCMDCFF1_SHIFT (24U) 325 #define DCM_DCMSRR_DCMDCFF1_WIDTH (3U) 326 #define DCM_DCMSRR_DCMDCFF1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF1_SHIFT)) & DCM_DCMSRR_DCMDCFF1_MASK) 327 328 #define DCM_DCMSRR_DCMESF1_MASK (0x8000000U) 329 #define DCM_DCMSRR_DCMESF1_SHIFT (27U) 330 #define DCM_DCMSRR_DCMESF1_WIDTH (1U) 331 #define DCM_DCMSRR_DCMESF1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF1_SHIFT)) & DCM_DCMSRR_DCMESF1_MASK) 332 333 #define DCM_DCMSRR_DCMESD1_MASK (0x10000000U) 334 #define DCM_DCMSRR_DCMESD1_SHIFT (28U) 335 #define DCM_DCMSRR_DCMESD1_WIDTH (1U) 336 #define DCM_DCMSRR_DCMESD1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD1_SHIFT)) & DCM_DCMSRR_DCMESD1_MASK) 337 338 #define DCM_DCMSRR_DCMDCFT1_MASK (0x20000000U) 339 #define DCM_DCMSRR_DCMDCFT1_SHIFT (29U) 340 #define DCM_DCMSRR_DCMDCFT1_WIDTH (1U) 341 #define DCM_DCMSRR_DCMDCFT1(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT1_SHIFT)) & DCM_DCMSRR_DCMDCFT1_MASK) 342 343 #define DCM_DCMSRR_DCMDCFE2_MASK (0x1FFFFFU) 344 #define DCM_DCMSRR_DCMDCFE2_SHIFT (0U) 345 #define DCM_DCMSRR_DCMDCFE2_WIDTH (21U) 346 #define DCM_DCMSRR_DCMDCFE2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE2_SHIFT)) & DCM_DCMSRR_DCMDCFE2_MASK) 347 348 #define DCM_DCMSRR_DCMDCFF2_MASK (0x7000000U) 349 #define DCM_DCMSRR_DCMDCFF2_SHIFT (24U) 350 #define DCM_DCMSRR_DCMDCFF2_WIDTH (3U) 351 #define DCM_DCMSRR_DCMDCFF2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF2_SHIFT)) & DCM_DCMSRR_DCMDCFF2_MASK) 352 353 #define DCM_DCMSRR_DCMESF2_MASK (0x8000000U) 354 #define DCM_DCMSRR_DCMESF2_SHIFT (27U) 355 #define DCM_DCMSRR_DCMESF2_WIDTH (1U) 356 #define DCM_DCMSRR_DCMESF2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF2_SHIFT)) & DCM_DCMSRR_DCMESF2_MASK) 357 358 #define DCM_DCMSRR_DCMESD2_MASK (0x10000000U) 359 #define DCM_DCMSRR_DCMESD2_SHIFT (28U) 360 #define DCM_DCMSRR_DCMESD2_WIDTH (1U) 361 #define DCM_DCMSRR_DCMESD2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD2_SHIFT)) & DCM_DCMSRR_DCMESD2_MASK) 362 363 #define DCM_DCMSRR_DCMDCFT2_MASK (0x20000000U) 364 #define DCM_DCMSRR_DCMDCFT2_SHIFT (29U) 365 #define DCM_DCMSRR_DCMDCFT2_WIDTH (1U) 366 #define DCM_DCMSRR_DCMDCFT2(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT2_SHIFT)) & DCM_DCMSRR_DCMDCFT2_MASK) 367 368 #define DCM_DCMSRR_DCMDCFE3_MASK (0x1FFFFFU) 369 #define DCM_DCMSRR_DCMDCFE3_SHIFT (0U) 370 #define DCM_DCMSRR_DCMDCFE3_WIDTH (21U) 371 #define DCM_DCMSRR_DCMDCFE3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE3_SHIFT)) & DCM_DCMSRR_DCMDCFE3_MASK) 372 373 #define DCM_DCMSRR_DCMDCFF3_MASK (0x7000000U) 374 #define DCM_DCMSRR_DCMDCFF3_SHIFT (24U) 375 #define DCM_DCMSRR_DCMDCFF3_WIDTH (3U) 376 #define DCM_DCMSRR_DCMDCFF3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF3_SHIFT)) & DCM_DCMSRR_DCMDCFF3_MASK) 377 378 #define DCM_DCMSRR_DCMESF3_MASK (0x8000000U) 379 #define DCM_DCMSRR_DCMESF3_SHIFT (27U) 380 #define DCM_DCMSRR_DCMESF3_WIDTH (1U) 381 #define DCM_DCMSRR_DCMESF3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF3_SHIFT)) & DCM_DCMSRR_DCMESF3_MASK) 382 383 #define DCM_DCMSRR_DCMESD3_MASK (0x10000000U) 384 #define DCM_DCMSRR_DCMESD3_SHIFT (28U) 385 #define DCM_DCMSRR_DCMESD3_WIDTH (1U) 386 #define DCM_DCMSRR_DCMESD3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD3_SHIFT)) & DCM_DCMSRR_DCMESD3_MASK) 387 388 #define DCM_DCMSRR_DCMDCFT3_MASK (0x20000000U) 389 #define DCM_DCMSRR_DCMDCFT3_SHIFT (29U) 390 #define DCM_DCMSRR_DCMDCFT3_WIDTH (1U) 391 #define DCM_DCMSRR_DCMDCFT3(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT3_SHIFT)) & DCM_DCMSRR_DCMDCFT3_MASK) 392 393 #define DCM_DCMSRR_DCMDCFE4_MASK (0x1FFFFFU) 394 #define DCM_DCMSRR_DCMDCFE4_SHIFT (0U) 395 #define DCM_DCMSRR_DCMDCFE4_WIDTH (21U) 396 #define DCM_DCMSRR_DCMDCFE4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE4_SHIFT)) & DCM_DCMSRR_DCMDCFE4_MASK) 397 398 #define DCM_DCMSRR_DCMDCFF4_MASK (0x7000000U) 399 #define DCM_DCMSRR_DCMDCFF4_SHIFT (24U) 400 #define DCM_DCMSRR_DCMDCFF4_WIDTH (3U) 401 #define DCM_DCMSRR_DCMDCFF4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF4_SHIFT)) & DCM_DCMSRR_DCMDCFF4_MASK) 402 403 #define DCM_DCMSRR_DCMESF4_MASK (0x8000000U) 404 #define DCM_DCMSRR_DCMESF4_SHIFT (27U) 405 #define DCM_DCMSRR_DCMESF4_WIDTH (1U) 406 #define DCM_DCMSRR_DCMESF4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF4_SHIFT)) & DCM_DCMSRR_DCMESF4_MASK) 407 408 #define DCM_DCMSRR_DCMESD4_MASK (0x10000000U) 409 #define DCM_DCMSRR_DCMESD4_SHIFT (28U) 410 #define DCM_DCMSRR_DCMESD4_WIDTH (1U) 411 #define DCM_DCMSRR_DCMESD4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD4_SHIFT)) & DCM_DCMSRR_DCMESD4_MASK) 412 413 #define DCM_DCMSRR_DCMDCFT4_MASK (0x20000000U) 414 #define DCM_DCMSRR_DCMDCFT4_SHIFT (29U) 415 #define DCM_DCMSRR_DCMDCFT4_WIDTH (1U) 416 #define DCM_DCMSRR_DCMDCFT4(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT4_SHIFT)) & DCM_DCMSRR_DCMDCFT4_MASK) 417 418 #define DCM_DCMSRR_DCMDCFE5_MASK (0x1FFFFFU) 419 #define DCM_DCMSRR_DCMDCFE5_SHIFT (0U) 420 #define DCM_DCMSRR_DCMDCFE5_WIDTH (21U) 421 #define DCM_DCMSRR_DCMDCFE5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE5_SHIFT)) & DCM_DCMSRR_DCMDCFE5_MASK) 422 423 #define DCM_DCMSRR_DCMDCFF5_MASK (0x7000000U) 424 #define DCM_DCMSRR_DCMDCFF5_SHIFT (24U) 425 #define DCM_DCMSRR_DCMDCFF5_WIDTH (3U) 426 #define DCM_DCMSRR_DCMDCFF5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF5_SHIFT)) & DCM_DCMSRR_DCMDCFF5_MASK) 427 428 #define DCM_DCMSRR_DCMESF5_MASK (0x8000000U) 429 #define DCM_DCMSRR_DCMESF5_SHIFT (27U) 430 #define DCM_DCMSRR_DCMESF5_WIDTH (1U) 431 #define DCM_DCMSRR_DCMESF5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF5_SHIFT)) & DCM_DCMSRR_DCMESF5_MASK) 432 433 #define DCM_DCMSRR_DCMESD5_MASK (0x10000000U) 434 #define DCM_DCMSRR_DCMESD5_SHIFT (28U) 435 #define DCM_DCMSRR_DCMESD5_WIDTH (1U) 436 #define DCM_DCMSRR_DCMESD5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD5_SHIFT)) & DCM_DCMSRR_DCMESD5_MASK) 437 438 #define DCM_DCMSRR_DCMDCFT5_MASK (0x20000000U) 439 #define DCM_DCMSRR_DCMDCFT5_SHIFT (29U) 440 #define DCM_DCMSRR_DCMDCFT5_WIDTH (1U) 441 #define DCM_DCMSRR_DCMDCFT5(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT5_SHIFT)) & DCM_DCMSRR_DCMDCFT5_MASK) 442 443 #define DCM_DCMSRR_DCMDCFE6_MASK (0x1FFFFFU) 444 #define DCM_DCMSRR_DCMDCFE6_SHIFT (0U) 445 #define DCM_DCMSRR_DCMDCFE6_WIDTH (21U) 446 #define DCM_DCMSRR_DCMDCFE6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE6_SHIFT)) & DCM_DCMSRR_DCMDCFE6_MASK) 447 448 #define DCM_DCMSRR_DCMDCFF6_MASK (0x7000000U) 449 #define DCM_DCMSRR_DCMDCFF6_SHIFT (24U) 450 #define DCM_DCMSRR_DCMDCFF6_WIDTH (3U) 451 #define DCM_DCMSRR_DCMDCFF6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF6_SHIFT)) & DCM_DCMSRR_DCMDCFF6_MASK) 452 453 #define DCM_DCMSRR_DCMESF6_MASK (0x8000000U) 454 #define DCM_DCMSRR_DCMESF6_SHIFT (27U) 455 #define DCM_DCMSRR_DCMESF6_WIDTH (1U) 456 #define DCM_DCMSRR_DCMESF6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF6_SHIFT)) & DCM_DCMSRR_DCMESF6_MASK) 457 458 #define DCM_DCMSRR_DCMESD6_MASK (0x10000000U) 459 #define DCM_DCMSRR_DCMESD6_SHIFT (28U) 460 #define DCM_DCMSRR_DCMESD6_WIDTH (1U) 461 #define DCM_DCMSRR_DCMESD6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD6_SHIFT)) & DCM_DCMSRR_DCMESD6_MASK) 462 463 #define DCM_DCMSRR_DCMDCFT6_MASK (0x20000000U) 464 #define DCM_DCMSRR_DCMDCFT6_SHIFT (29U) 465 #define DCM_DCMSRR_DCMDCFT6_WIDTH (1U) 466 #define DCM_DCMSRR_DCMDCFT6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT6_SHIFT)) & DCM_DCMSRR_DCMDCFT6_MASK) 467 468 #define DCM_DCMSRR_DCMDCFE7_MASK (0x1FFFFFU) 469 #define DCM_DCMSRR_DCMDCFE7_SHIFT (0U) 470 #define DCM_DCMSRR_DCMDCFE7_WIDTH (21U) 471 #define DCM_DCMSRR_DCMDCFE7(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE7_SHIFT)) & DCM_DCMSRR_DCMDCFE7_MASK) 472 473 #define DCM_DCMSRR_DCMDCFF7_MASK (0x7000000U) 474 #define DCM_DCMSRR_DCMDCFF7_SHIFT (24U) 475 #define DCM_DCMSRR_DCMDCFF7_WIDTH (3U) 476 #define DCM_DCMSRR_DCMDCFF7(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF7_SHIFT)) & DCM_DCMSRR_DCMDCFF7_MASK) 477 478 #define DCM_DCMSRR_DCMESF7_MASK (0x8000000U) 479 #define DCM_DCMSRR_DCMESF7_SHIFT (27U) 480 #define DCM_DCMSRR_DCMESF7_WIDTH (1U) 481 #define DCM_DCMSRR_DCMESF7(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF7_SHIFT)) & DCM_DCMSRR_DCMESF7_MASK) 482 483 #define DCM_DCMSRR_DCMESD7_MASK (0x10000000U) 484 #define DCM_DCMSRR_DCMESD7_SHIFT (28U) 485 #define DCM_DCMSRR_DCMESD7_WIDTH (1U) 486 #define DCM_DCMSRR_DCMESD7(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD7_SHIFT)) & DCM_DCMSRR_DCMESD7_MASK) 487 488 #define DCM_DCMSRR_DCMDCFT7_MASK (0x20000000U) 489 #define DCM_DCMSRR_DCMDCFT7_SHIFT (29U) 490 #define DCM_DCMSRR_DCMDCFT7_WIDTH (1U) 491 #define DCM_DCMSRR_DCMDCFT7(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT7_SHIFT)) & DCM_DCMSRR_DCMDCFT7_MASK) 492 493 #define DCM_DCMSRR_DCMDCFE8_MASK (0x1FFFFFU) 494 #define DCM_DCMSRR_DCMDCFE8_SHIFT (0U) 495 #define DCM_DCMSRR_DCMDCFE8_WIDTH (21U) 496 #define DCM_DCMSRR_DCMDCFE8(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE8_SHIFT)) & DCM_DCMSRR_DCMDCFE8_MASK) 497 498 #define DCM_DCMSRR_DCMDCFF8_MASK (0x7000000U) 499 #define DCM_DCMSRR_DCMDCFF8_SHIFT (24U) 500 #define DCM_DCMSRR_DCMDCFF8_WIDTH (3U) 501 #define DCM_DCMSRR_DCMDCFF8(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF8_SHIFT)) & DCM_DCMSRR_DCMDCFF8_MASK) 502 503 #define DCM_DCMSRR_DCMESF8_MASK (0x8000000U) 504 #define DCM_DCMSRR_DCMESF8_SHIFT (27U) 505 #define DCM_DCMSRR_DCMESF8_WIDTH (1U) 506 #define DCM_DCMSRR_DCMESF8(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF8_SHIFT)) & DCM_DCMSRR_DCMESF8_MASK) 507 508 #define DCM_DCMSRR_DCMESD8_MASK (0x10000000U) 509 #define DCM_DCMSRR_DCMESD8_SHIFT (28U) 510 #define DCM_DCMSRR_DCMESD8_WIDTH (1U) 511 #define DCM_DCMSRR_DCMESD8(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD8_SHIFT)) & DCM_DCMSRR_DCMESD8_MASK) 512 513 #define DCM_DCMSRR_DCMDCFT8_MASK (0x20000000U) 514 #define DCM_DCMSRR_DCMDCFT8_SHIFT (29U) 515 #define DCM_DCMSRR_DCMDCFT8_WIDTH (1U) 516 #define DCM_DCMSRR_DCMDCFT8(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT8_SHIFT)) & DCM_DCMSRR_DCMDCFT8_MASK) 517 518 #define DCM_DCMSRR_DCMDCFE9_MASK (0x1FFFFFU) 519 #define DCM_DCMSRR_DCMDCFE9_SHIFT (0U) 520 #define DCM_DCMSRR_DCMDCFE9_WIDTH (21U) 521 #define DCM_DCMSRR_DCMDCFE9(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE9_SHIFT)) & DCM_DCMSRR_DCMDCFE9_MASK) 522 523 #define DCM_DCMSRR_DCMDCFF9_MASK (0x7000000U) 524 #define DCM_DCMSRR_DCMDCFF9_SHIFT (24U) 525 #define DCM_DCMSRR_DCMDCFF9_WIDTH (3U) 526 #define DCM_DCMSRR_DCMDCFF9(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF9_SHIFT)) & DCM_DCMSRR_DCMDCFF9_MASK) 527 528 #define DCM_DCMSRR_DCMESF9_MASK (0x8000000U) 529 #define DCM_DCMSRR_DCMESF9_SHIFT (27U) 530 #define DCM_DCMSRR_DCMESF9_WIDTH (1U) 531 #define DCM_DCMSRR_DCMESF9(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF9_SHIFT)) & DCM_DCMSRR_DCMESF9_MASK) 532 533 #define DCM_DCMSRR_DCMESD9_MASK (0x10000000U) 534 #define DCM_DCMSRR_DCMESD9_SHIFT (28U) 535 #define DCM_DCMSRR_DCMESD9_WIDTH (1U) 536 #define DCM_DCMSRR_DCMESD9(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD9_SHIFT)) & DCM_DCMSRR_DCMESD9_MASK) 537 538 #define DCM_DCMSRR_DCMDCFT9_MASK (0x20000000U) 539 #define DCM_DCMSRR_DCMDCFT9_SHIFT (29U) 540 #define DCM_DCMSRR_DCMDCFT9_WIDTH (1U) 541 #define DCM_DCMSRR_DCMDCFT9(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT9_SHIFT)) & DCM_DCMSRR_DCMDCFT9_MASK) 542 543 #define DCM_DCMSRR_DCMDCFE10_MASK (0x1FFFFFU) 544 #define DCM_DCMSRR_DCMDCFE10_SHIFT (0U) 545 #define DCM_DCMSRR_DCMDCFE10_WIDTH (21U) 546 #define DCM_DCMSRR_DCMDCFE10(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE10_SHIFT)) & DCM_DCMSRR_DCMDCFE10_MASK) 547 548 #define DCM_DCMSRR_DCMDCFF10_MASK (0x7000000U) 549 #define DCM_DCMSRR_DCMDCFF10_SHIFT (24U) 550 #define DCM_DCMSRR_DCMDCFF10_WIDTH (3U) 551 #define DCM_DCMSRR_DCMDCFF10(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF10_SHIFT)) & DCM_DCMSRR_DCMDCFF10_MASK) 552 553 #define DCM_DCMSRR_DCMESF10_MASK (0x8000000U) 554 #define DCM_DCMSRR_DCMESF10_SHIFT (27U) 555 #define DCM_DCMSRR_DCMESF10_WIDTH (1U) 556 #define DCM_DCMSRR_DCMESF10(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF10_SHIFT)) & DCM_DCMSRR_DCMESF10_MASK) 557 558 #define DCM_DCMSRR_DCMESD10_MASK (0x10000000U) 559 #define DCM_DCMSRR_DCMESD10_SHIFT (28U) 560 #define DCM_DCMSRR_DCMESD10_WIDTH (1U) 561 #define DCM_DCMSRR_DCMESD10(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD10_SHIFT)) & DCM_DCMSRR_DCMESD10_MASK) 562 563 #define DCM_DCMSRR_DCMDCFT10_MASK (0x20000000U) 564 #define DCM_DCMSRR_DCMDCFT10_SHIFT (29U) 565 #define DCM_DCMSRR_DCMDCFT10_WIDTH (1U) 566 #define DCM_DCMSRR_DCMDCFT10(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT10_SHIFT)) & DCM_DCMSRR_DCMDCFT10_MASK) 567 568 #define DCM_DCMSRR_DCMDCFE11_MASK (0x1FFFFFU) 569 #define DCM_DCMSRR_DCMDCFE11_SHIFT (0U) 570 #define DCM_DCMSRR_DCMDCFE11_WIDTH (21U) 571 #define DCM_DCMSRR_DCMDCFE11(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE11_SHIFT)) & DCM_DCMSRR_DCMDCFE11_MASK) 572 573 #define DCM_DCMSRR_DCMDCFF11_MASK (0x7000000U) 574 #define DCM_DCMSRR_DCMDCFF11_SHIFT (24U) 575 #define DCM_DCMSRR_DCMDCFF11_WIDTH (3U) 576 #define DCM_DCMSRR_DCMDCFF11(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF11_SHIFT)) & DCM_DCMSRR_DCMDCFF11_MASK) 577 578 #define DCM_DCMSRR_DCMESF11_MASK (0x8000000U) 579 #define DCM_DCMSRR_DCMESF11_SHIFT (27U) 580 #define DCM_DCMSRR_DCMESF11_WIDTH (1U) 581 #define DCM_DCMSRR_DCMESF11(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF11_SHIFT)) & DCM_DCMSRR_DCMESF11_MASK) 582 583 #define DCM_DCMSRR_DCMESD11_MASK (0x10000000U) 584 #define DCM_DCMSRR_DCMESD11_SHIFT (28U) 585 #define DCM_DCMSRR_DCMESD11_WIDTH (1U) 586 #define DCM_DCMSRR_DCMESD11(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD11_SHIFT)) & DCM_DCMSRR_DCMESD11_MASK) 587 588 #define DCM_DCMSRR_DCMDCFT11_MASK (0x20000000U) 589 #define DCM_DCMSRR_DCMDCFT11_SHIFT (29U) 590 #define DCM_DCMSRR_DCMDCFT11_WIDTH (1U) 591 #define DCM_DCMSRR_DCMDCFT11(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT11_SHIFT)) & DCM_DCMSRR_DCMDCFT11_MASK) 592 593 #define DCM_DCMSRR_DCMDCFE12_MASK (0x1FFFFFU) 594 #define DCM_DCMSRR_DCMDCFE12_SHIFT (0U) 595 #define DCM_DCMSRR_DCMDCFE12_WIDTH (21U) 596 #define DCM_DCMSRR_DCMDCFE12(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE12_SHIFT)) & DCM_DCMSRR_DCMDCFE12_MASK) 597 598 #define DCM_DCMSRR_DCMDCFF12_MASK (0x7000000U) 599 #define DCM_DCMSRR_DCMDCFF12_SHIFT (24U) 600 #define DCM_DCMSRR_DCMDCFF12_WIDTH (3U) 601 #define DCM_DCMSRR_DCMDCFF12(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF12_SHIFT)) & DCM_DCMSRR_DCMDCFF12_MASK) 602 603 #define DCM_DCMSRR_DCMESF12_MASK (0x8000000U) 604 #define DCM_DCMSRR_DCMESF12_SHIFT (27U) 605 #define DCM_DCMSRR_DCMESF12_WIDTH (1U) 606 #define DCM_DCMSRR_DCMESF12(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF12_SHIFT)) & DCM_DCMSRR_DCMESF12_MASK) 607 608 #define DCM_DCMSRR_DCMESD12_MASK (0x10000000U) 609 #define DCM_DCMSRR_DCMESD12_SHIFT (28U) 610 #define DCM_DCMSRR_DCMESD12_WIDTH (1U) 611 #define DCM_DCMSRR_DCMESD12(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD12_SHIFT)) & DCM_DCMSRR_DCMESD12_MASK) 612 613 #define DCM_DCMSRR_DCMDCFT12_MASK (0x20000000U) 614 #define DCM_DCMSRR_DCMDCFT12_SHIFT (29U) 615 #define DCM_DCMSRR_DCMDCFT12_WIDTH (1U) 616 #define DCM_DCMSRR_DCMDCFT12(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT12_SHIFT)) & DCM_DCMSRR_DCMDCFT12_MASK) 617 618 #define DCM_DCMSRR_DCMDCFE13_MASK (0x1FFFFFU) 619 #define DCM_DCMSRR_DCMDCFE13_SHIFT (0U) 620 #define DCM_DCMSRR_DCMDCFE13_WIDTH (21U) 621 #define DCM_DCMSRR_DCMDCFE13(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE13_SHIFT)) & DCM_DCMSRR_DCMDCFE13_MASK) 622 623 #define DCM_DCMSRR_DCMDCFF13_MASK (0x7000000U) 624 #define DCM_DCMSRR_DCMDCFF13_SHIFT (24U) 625 #define DCM_DCMSRR_DCMDCFF13_WIDTH (3U) 626 #define DCM_DCMSRR_DCMDCFF13(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF13_SHIFT)) & DCM_DCMSRR_DCMDCFF13_MASK) 627 628 #define DCM_DCMSRR_DCMESF13_MASK (0x8000000U) 629 #define DCM_DCMSRR_DCMESF13_SHIFT (27U) 630 #define DCM_DCMSRR_DCMESF13_WIDTH (1U) 631 #define DCM_DCMSRR_DCMESF13(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF13_SHIFT)) & DCM_DCMSRR_DCMESF13_MASK) 632 633 #define DCM_DCMSRR_DCMESD13_MASK (0x10000000U) 634 #define DCM_DCMSRR_DCMESD13_SHIFT (28U) 635 #define DCM_DCMSRR_DCMESD13_WIDTH (1U) 636 #define DCM_DCMSRR_DCMESD13(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD13_SHIFT)) & DCM_DCMSRR_DCMESD13_MASK) 637 638 #define DCM_DCMSRR_DCMDCFT13_MASK (0x20000000U) 639 #define DCM_DCMSRR_DCMDCFT13_SHIFT (29U) 640 #define DCM_DCMSRR_DCMDCFT13_WIDTH (1U) 641 #define DCM_DCMSRR_DCMDCFT13(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT13_SHIFT)) & DCM_DCMSRR_DCMDCFT13_MASK) 642 643 #define DCM_DCMSRR_DCMDCFE14_MASK (0x1FFFFFU) 644 #define DCM_DCMSRR_DCMDCFE14_SHIFT (0U) 645 #define DCM_DCMSRR_DCMDCFE14_WIDTH (21U) 646 #define DCM_DCMSRR_DCMDCFE14(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE14_SHIFT)) & DCM_DCMSRR_DCMDCFE14_MASK) 647 648 #define DCM_DCMSRR_DCMDCFF14_MASK (0x7000000U) 649 #define DCM_DCMSRR_DCMDCFF14_SHIFT (24U) 650 #define DCM_DCMSRR_DCMDCFF14_WIDTH (3U) 651 #define DCM_DCMSRR_DCMDCFF14(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF14_SHIFT)) & DCM_DCMSRR_DCMDCFF14_MASK) 652 653 #define DCM_DCMSRR_DCMESF14_MASK (0x8000000U) 654 #define DCM_DCMSRR_DCMESF14_SHIFT (27U) 655 #define DCM_DCMSRR_DCMESF14_WIDTH (1U) 656 #define DCM_DCMSRR_DCMESF14(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF14_SHIFT)) & DCM_DCMSRR_DCMESF14_MASK) 657 658 #define DCM_DCMSRR_DCMESD14_MASK (0x10000000U) 659 #define DCM_DCMSRR_DCMESD14_SHIFT (28U) 660 #define DCM_DCMSRR_DCMESD14_WIDTH (1U) 661 #define DCM_DCMSRR_DCMESD14(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD14_SHIFT)) & DCM_DCMSRR_DCMESD14_MASK) 662 663 #define DCM_DCMSRR_DCMDCFT14_MASK (0x20000000U) 664 #define DCM_DCMSRR_DCMDCFT14_SHIFT (29U) 665 #define DCM_DCMSRR_DCMDCFT14_WIDTH (1U) 666 #define DCM_DCMSRR_DCMDCFT14(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT14_SHIFT)) & DCM_DCMSRR_DCMDCFT14_MASK) 667 668 #define DCM_DCMSRR_DCMDCFE15_MASK (0x1FFFFFU) 669 #define DCM_DCMSRR_DCMDCFE15_SHIFT (0U) 670 #define DCM_DCMSRR_DCMDCFE15_WIDTH (21U) 671 #define DCM_DCMSRR_DCMDCFE15(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE15_SHIFT)) & DCM_DCMSRR_DCMDCFE15_MASK) 672 673 #define DCM_DCMSRR_DCMDCFF15_MASK (0x7000000U) 674 #define DCM_DCMSRR_DCMDCFF15_SHIFT (24U) 675 #define DCM_DCMSRR_DCMDCFF15_WIDTH (3U) 676 #define DCM_DCMSRR_DCMDCFF15(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF15_SHIFT)) & DCM_DCMSRR_DCMDCFF15_MASK) 677 678 #define DCM_DCMSRR_DCMESF15_MASK (0x8000000U) 679 #define DCM_DCMSRR_DCMESF15_SHIFT (27U) 680 #define DCM_DCMSRR_DCMESF15_WIDTH (1U) 681 #define DCM_DCMSRR_DCMESF15(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF15_SHIFT)) & DCM_DCMSRR_DCMESF15_MASK) 682 683 #define DCM_DCMSRR_DCMESD15_MASK (0x10000000U) 684 #define DCM_DCMSRR_DCMESD15_SHIFT (28U) 685 #define DCM_DCMSRR_DCMESD15_WIDTH (1U) 686 #define DCM_DCMSRR_DCMESD15(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD15_SHIFT)) & DCM_DCMSRR_DCMESD15_MASK) 687 688 #define DCM_DCMSRR_DCMDCFT15_MASK (0x20000000U) 689 #define DCM_DCMSRR_DCMDCFT15_SHIFT (29U) 690 #define DCM_DCMSRR_DCMDCFT15_WIDTH (1U) 691 #define DCM_DCMSRR_DCMDCFT15(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT15_SHIFT)) & DCM_DCMSRR_DCMDCFT15_MASK) 692 693 #define DCM_DCMSRR_DCMDCFE16_MASK (0x1FFFFFU) 694 #define DCM_DCMSRR_DCMDCFE16_SHIFT (0U) 695 #define DCM_DCMSRR_DCMDCFE16_WIDTH (21U) 696 #define DCM_DCMSRR_DCMDCFE16(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFE16_SHIFT)) & DCM_DCMSRR_DCMDCFE16_MASK) 697 698 #define DCM_DCMSRR_DCMDCFF16_MASK (0x7000000U) 699 #define DCM_DCMSRR_DCMDCFF16_SHIFT (24U) 700 #define DCM_DCMSRR_DCMDCFF16_WIDTH (3U) 701 #define DCM_DCMSRR_DCMDCFF16(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFF16_SHIFT)) & DCM_DCMSRR_DCMDCFF16_MASK) 702 703 #define DCM_DCMSRR_DCMESF16_MASK (0x8000000U) 704 #define DCM_DCMSRR_DCMESF16_SHIFT (27U) 705 #define DCM_DCMSRR_DCMESF16_WIDTH (1U) 706 #define DCM_DCMSRR_DCMESF16(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESF16_SHIFT)) & DCM_DCMSRR_DCMESF16_MASK) 707 708 #define DCM_DCMSRR_DCMESD16_MASK (0x10000000U) 709 #define DCM_DCMSRR_DCMESD16_SHIFT (28U) 710 #define DCM_DCMSRR_DCMESD16_WIDTH (1U) 711 #define DCM_DCMSRR_DCMESD16(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMESD16_SHIFT)) & DCM_DCMSRR_DCMESD16_MASK) 712 713 #define DCM_DCMSRR_DCMDCFT16_MASK (0x20000000U) 714 #define DCM_DCMSRR_DCMDCFT16_SHIFT (29U) 715 #define DCM_DCMSRR_DCMDCFT16_WIDTH (1U) 716 #define DCM_DCMSRR_DCMDCFT16(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMSRR_DCMDCFT16_SHIFT)) & DCM_DCMSRR_DCMDCFT16_MASK) 717 /*! @} */ 718 719 /*! @name DCMLCS_2 - LC Scan Status 2 */ 720 /*! @{ */ 721 722 #define DCM_DCMLCS_2_DCMLCSS6_MASK (0x1U) 723 #define DCM_DCMLCS_2_DCMLCSS6_SHIFT (0U) 724 #define DCM_DCMLCS_2_DCMLCSS6_WIDTH (1U) 725 #define DCM_DCMLCS_2_DCMLCSS6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_2_DCMLCSS6_SHIFT)) & DCM_DCMLCS_2_DCMLCSS6_MASK) 726 727 #define DCM_DCMLCS_2_DCMLCC6_MASK (0xEU) 728 #define DCM_DCMLCS_2_DCMLCC6_SHIFT (1U) 729 #define DCM_DCMLCS_2_DCMLCC6_WIDTH (3U) 730 #define DCM_DCMLCS_2_DCMLCC6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_2_DCMLCC6_SHIFT)) & DCM_DCMLCS_2_DCMLCC6_MASK) 731 732 #define DCM_DCMLCS_2_DCMLCE6_MASK (0x10U) 733 #define DCM_DCMLCS_2_DCMLCE6_SHIFT (4U) 734 #define DCM_DCMLCS_2_DCMLCE6_WIDTH (1U) 735 #define DCM_DCMLCS_2_DCMLCE6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_2_DCMLCE6_SHIFT)) & DCM_DCMLCS_2_DCMLCE6_MASK) 736 737 #define DCM_DCMLCS_2_DCMLCFE6_MASK (0x20U) 738 #define DCM_DCMLCS_2_DCMLCFE6_SHIFT (5U) 739 #define DCM_DCMLCS_2_DCMLCFE6_WIDTH (1U) 740 #define DCM_DCMLCS_2_DCMLCFE6(x) (((uint32_t)(((uint32_t)(x)) << DCM_DCMLCS_2_DCMLCFE6_SHIFT)) & DCM_DCMLCS_2_DCMLCFE6_MASK) 741 /*! @} */ 742 743 /*! 744 * @} 745 */ /* end of group DCM_Register_Masks */ 746 747 /*! 748 * @} 749 */ /* end of group DCM_Peripheral_Access_Layer */ 750 751 #endif /* #if !defined(S32K344_DCM_H_) */ 752
