1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_CRC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_CRC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_CRC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_CRC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CRC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CRC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t DATA; /**< CRC DATA register, offset: 0x0 */ 74 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 75 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 76 } CRC_Type, *CRC_MemMapPtr; 77 78 /** Number of instances of the CRC module. */ 79 #define CRC_INSTANCE_COUNT (1u) 80 81 /* CRC - Peripheral instance base addresses */ 82 /** Peripheral CRC base address */ 83 #define IP_CRC_BASE (0x40380000u) 84 /** Peripheral CRC base pointer */ 85 #define IP_CRC ((CRC_Type *)IP_CRC_BASE) 86 /** Array initializer of CRC peripheral base addresses */ 87 #define IP_CRC_BASE_ADDRS { IP_CRC_BASE } 88 /** Array initializer of CRC peripheral base pointers */ 89 #define IP_CRC_BASE_PTRS { IP_CRC } 90 91 /* ---------------------------------------------------------------------------- 92 -- CRC Register Masks 93 ---------------------------------------------------------------------------- */ 94 95 /*! 96 * @addtogroup CRC_Register_Masks CRC Register Masks 97 * @{ 98 */ 99 100 /*! @name DATA - CRC DATA register */ 101 /*! @{ */ 102 103 #define CRC_DATA_LL_MASK (0xFFU) 104 #define CRC_DATA_LL_SHIFT (0U) 105 #define CRC_DATA_LL_WIDTH (8U) 106 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 107 108 #define CRC_DATA_LU_MASK (0xFF00U) 109 #define CRC_DATA_LU_SHIFT (8U) 110 #define CRC_DATA_LU_WIDTH (8U) 111 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 112 113 #define CRC_DATA_HL_MASK (0xFF0000U) 114 #define CRC_DATA_HL_SHIFT (16U) 115 #define CRC_DATA_HL_WIDTH (8U) 116 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 117 118 #define CRC_DATA_HU_MASK (0xFF000000U) 119 #define CRC_DATA_HU_SHIFT (24U) 120 #define CRC_DATA_HU_WIDTH (8U) 121 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 122 /*! @} */ 123 124 /*! @name GPOLY - CRC Polynomial register */ 125 /*! @{ */ 126 127 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 128 #define CRC_GPOLY_LOW_SHIFT (0U) 129 #define CRC_GPOLY_LOW_WIDTH (16U) 130 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 131 132 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 133 #define CRC_GPOLY_HIGH_SHIFT (16U) 134 #define CRC_GPOLY_HIGH_WIDTH (16U) 135 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 136 /*! @} */ 137 138 /*! @name CTRL - CRC Control register */ 139 /*! @{ */ 140 141 #define CRC_CTRL_TCRC_MASK (0x1000000U) 142 #define CRC_CTRL_TCRC_SHIFT (24U) 143 #define CRC_CTRL_TCRC_WIDTH (1U) 144 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 145 146 #define CRC_CTRL_WAS_MASK (0x2000000U) 147 #define CRC_CTRL_WAS_SHIFT (25U) 148 #define CRC_CTRL_WAS_WIDTH (1U) 149 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 150 151 #define CRC_CTRL_FXOR_MASK (0x4000000U) 152 #define CRC_CTRL_FXOR_SHIFT (26U) 153 #define CRC_CTRL_FXOR_WIDTH (1U) 154 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 155 156 #define CRC_CTRL_TOTR_MASK (0x30000000U) 157 #define CRC_CTRL_TOTR_SHIFT (28U) 158 #define CRC_CTRL_TOTR_WIDTH (2U) 159 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 160 161 #define CRC_CTRL_TOT_MASK (0xC0000000U) 162 #define CRC_CTRL_TOT_SHIFT (30U) 163 #define CRC_CTRL_TOT_WIDTH (2U) 164 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 165 /*! @} */ 166 167 /*! 168 * @} 169 */ /* end of group CRC_Register_Masks */ 170 171 /*! 172 * @} 173 */ /* end of group CRC_Peripheral_Access_Layer */ 174 175 #endif /* #if !defined(S32K344_CRC_H_) */ 176
