1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_M4.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_M4 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 57 /* ---------------------------------------------------------------------------- 58 -- MCU activation 59 ---------------------------------------------------------------------------- */ 60 61 /* Prevention from multiple including the same memory map */ 62 #if !defined(S32K148_COMMON_H_) /* Check if memory map has not been already included */ 63 #define S32K148_COMMON_H_ 64 #define MCU_S32K148 65 66 /* Check if another memory map has not been also included */ 67 #if (defined(MCU_ACTIVE)) 68 #error S32K148_M4 memory map: There is already included another memory map. Only one memory map can be included. 69 #endif /* (defined(MCU_ACTIVE)) */ 70 #define MCU_ACTIVE 71 72 #include "BasicTypes.h" 73 74 /** Memory map major version (memory maps with equal major version number are 75 * compatible) */ 76 #define MCU_MEM_MAP_VERSION 0x0100U 77 /** Memory map minor version */ 78 #define MCU_MEM_MAP_VERSION_MINOR 0x0001U 79 80 /* ---------------------------------------------------------------------------- 81 -- Generic macros 82 ---------------------------------------------------------------------------- */ 83 84 /* IO definitions (access restrictions to peripheral registers) */ 85 /** 86 * IO Type Qualifiers are used 87 * \li to specify the access to peripheral variables. 88 * \li for automatic generation of peripheral register debug information. 89 */ 90 #ifndef __IO 91 #ifdef __cplusplus 92 #define __I volatile /*!< Defines 'read only' permissions */ 93 #else 94 #define __I volatile const /*!< Defines 'read only' permissions */ 95 #endif 96 #define __O volatile /*!< Defines 'write only' permissions */ 97 #define __IO volatile /*!< Defines 'read / write' permissions */ 98 #endif 99 100 101 /** 102 * @brief 32 bits memory read macro. 103 */ 104 #if !defined(REG_READ32) 105 #define REG_READ32(address) (*(volatile uint32_t*)(address)) 106 #endif 107 108 /** 109 * @brief 32 bits memory write macro. 110 */ 111 #if !defined(REG_WRITE32) 112 #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) 113 #endif 114 115 /** 116 * @brief 32 bits bits setting macro. 117 */ 118 #if !defined(REG_BIT_SET32) 119 #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) 120 #endif 121 122 /** 123 * @brief 32 bits bits clearing macro. 124 */ 125 #if !defined(REG_BIT_CLEAR32) 126 #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) 127 #endif 128 129 /** 130 * @brief 32 bit clear bits and set with new value 131 * @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 132 */ 133 #if !defined(REG_RMW32) 134 #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) 135 #endif 136 137 138 /* ---------------------------------------------------------------------------- 139 -- Interrupt vector numbers 140 ---------------------------------------------------------------------------- */ 141 142 /*! 143 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 144 * @{ 145 */ 146 147 /** Interrupt Number Definitions */ 148 #define NUMBER_OF_INT_VECTORS 163 /**< Number of interrupts in the Vector table */ 149 150 typedef enum { 151 /* Auxiliary constants */ 152 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 153 154 /* Core interrupts */ 155 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 156 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ 157 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ 158 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ 159 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ 160 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ 161 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ 162 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ 163 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ 164 165 /* Device specific interrupts */ 166 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ 167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ 168 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ 169 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ 170 DMA4_IRQn = 4, /**< DMA channel 4 transfer complete */ 171 DMA5_IRQn = 5, /**< DMA channel 5 transfer complete */ 172 DMA6_IRQn = 6, /**< DMA channel 6 transfer complete */ 173 DMA7_IRQn = 7, /**< DMA channel 7 transfer complete */ 174 DMA8_IRQn = 8, /**< DMA channel 8 transfer complete */ 175 DMA9_IRQn = 9, /**< DMA channel 9 transfer complete */ 176 DMA10_IRQn = 10, /**< DMA channel 10 transfer complete */ 177 DMA11_IRQn = 11, /**< DMA channel 11 transfer complete */ 178 DMA12_IRQn = 12, /**< DMA channel 12 transfer complete */ 179 DMA13_IRQn = 13, /**< DMA channel 13 transfer complete */ 180 DMA14_IRQn = 14, /**< DMA channel 14 transfer complete */ 181 DMA15_IRQn = 15, /**< DMA channel 15 transfer complete */ 182 DMA_Error_IRQn = 16, /**< DMA error interrupt channels 0-15 */ 183 MCM_IRQn = 17, /**< FPU sources */ 184 FTFC_CMD_IRQn = 18, /**< FTFC Command complete */ 185 FTFC_Read_Collision_IRQn = 19, /**< FTFC Read collision */ 186 LVD_LVW_IRQn = 20, /**< PMC Low voltage detect interrupt */ 187 FTFC_Fault_IRQn = 21, /**< FTFC Double bit fault detect */ 188 WDOG_EWM_IRQn = 22, /**< Interrupt request out before WDOG reset out, EWM output as interrupt */ 189 RCM_IRQn = 23, /**< RCM Asynchronous Interrupt */ 190 LPI2C0_Master_IRQn = 24, /**< LPI2C0 Master Interrupt */ 191 LPI2C0_Slave_IRQn = 25, /**< LPI2C0 Slave Interrupt */ 192 LPSPI0_IRQn = 26, /**< LPSPI0 Interrupt */ 193 LPSPI1_IRQn = 27, /**< LPSPI1 Interrupt */ 194 LPSPI2_IRQn = 28, /**< LPSPI2 Interrupt */ 195 LPI2C1_Master_IRQn = 29, /**< LPI2C1 Master Interrupt */ 196 LPI2C1_Slave_IRQn = 30, /**< LPI2C1 Slave Interrupt */ 197 LPUART0_RxTx_IRQn = 31, /**< LPUART0 Transmit / Receive Interrupt / Error / Overrun */ 198 LPUART1_RxTx_IRQn = 33, /**< LPUART1 Transmit / Receive Interrupt / Error / Overrun */ 199 LPUART2_RxTx_IRQn = 35, /**< LPUART2 Transmit / Receive Interrupt / Error / Overrun */ 200 ADC0_IRQn = 39, /**< ADC0 interrupt request */ 201 ADC1_IRQn = 40, /**< ADC1 interrupt request */ 202 CMP0_IRQn = 41, /**< CMP0 interrupt request */ 203 ERM_single_fault_IRQn = 44, /**< ERM single bit error correction */ 204 ERM_double_fault_IRQn = 45, /**< ERM double bit error non-correctable */ 205 RTC_IRQn = 46, /**< RTC alarm interrupt */ 206 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ 207 LPIT0_Ch0_IRQn = 48, /**< LPIT0 channel 0 overflow interrupt */ 208 LPIT0_Ch1_IRQn = 49, /**< LPIT0 channel 1 overflow interrupt */ 209 LPIT0_Ch2_IRQn = 50, /**< LPIT0 channel 2 overflow interrupt */ 210 LPIT0_Ch3_IRQn = 51, /**< LPIT0 channel 3 overflow interrupt */ 211 PDB0_IRQn = 52, /**< PDB0 interrupt */ 212 SAI1_TX_SYNC_IRQn = 55, /**< Transmit Synchronous interupt (for interrupt controller) */ 213 SAI1_RX_SYNC_IRQn = 56, /**< Transmit Synchronous interupt (for interrupt controller) */ 214 SCG_IRQn = 57, /**< SCG bus interrupt request */ 215 LPTMR0_IRQn = 58, /**< LPTIMER interrupt request */ 216 PORTA_IRQn = 59, /**< Port A pin detect interrupt */ 217 PORTB_IRQn = 60, /**< Port B pin detect interrupt */ 218 PORTC_IRQn = 61, /**< Port C pin detect interrupt */ 219 PORTD_IRQn = 62, /**< Port D pin detect interrupt */ 220 PORTE_IRQn = 63, /**< Port E pin detect interrupt */ 221 SWI_IRQn = 64, /**< Software interrupt */ 222 QSPI_Ored_IRQn = 65, /**< All interrupts ORed output */ 223 PDB1_IRQn = 68, /**< PDB1 interrupt */ 224 FLEXIO_IRQn = 69, /**< Software interrupt */ 225 SAI0_TX_SYNC_IRQn = 70, /**< Transmit Synchronous interupt (for interrupt controller) */ 226 SAI0_RX_SYNC_IRQn = 71, /**< Transmit Synchronous interupt (for interrupt controller) */ 227 ENET_Timer_IRQn = 72, /**< 1588 Timer Interrupt - synchronous, Period EventTimer Overflow, Time stamp available */ 228 ENET_TX_Buffer_IRQn = 73, /**< Data transfer done, Transmit Buffer Done for Ring/Queue 0, Transmit Frame Done for Ring/Queue 0 */ 229 ENET_RX_Buffer_IRQn = 74, /**< Receive Buffer Done for Ring/Queue 0, Receive Frame Done for Ring/Queue 0 */ 230 ENET_PRE_IRQn = 75, /**< Payload receive error, Collision retry limit reached, Late collision detected, AXI Bus Error detected, Babbling transmit error, Babbling receive error, Transmit FIFO underrun */ 231 ENET_STOP_IRQn = 76, /**< ENET Graceful stop */ 232 ENET_WAKE_IRQn = 77, /**< ENET Wake from sleep. */ 233 CAN0_ORed_IRQn = 78, /**< CAN0 OR'ed Bus in Off State. */ 234 CAN0_Error_IRQn = 79, /**< CAN0 Interrupt indicating that errors were detected on the CAN bus */ 235 CAN0_Wake_Up_IRQn = 80, /**< CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ 236 CAN0_ORed_0_15_MB_IRQn = 81, /**< CAN0 OR'ed Message buffer (0-15) */ 237 CAN0_ORed_16_31_MB_IRQn = 82, /**< CAN0 OR'ed Message buffer (16-31) */ 238 CAN1_ORed_IRQn = 85, /**< CAN1 OR'ed Bus in Off State */ 239 CAN1_Error_IRQn = 86, /**< CAN1 Interrupt indicating that errors were detected on the CAN bus */ 240 CAN1_ORed_0_15_MB_IRQn = 88, /**< CAN1 OR'ed Message buffer (0-15) */ 241 CAN1_ORed_16_31_MB_IRQn = 89, /**< CAN1 OR'ed Message buffer (16-31) */ 242 CAN2_ORed_IRQn = 92, /**< CAN2 OR'ed Bus in Off State */ 243 CAN2_Error_IRQn = 93, /**< CAN2 Interrupt indicating that errors were detected on the CAN bus, Interrupt indicating that errors were detected on the CAN bus for FD messages in the Fast Bit Rate region */ 244 CAN2_ORed_0_15_MB_IRQn = 95, /**< CAN2 OR'ed Message buffer (0-15) */ 245 CAN2_ORed_16_31_MB_IRQn = 96, /**< CAN1 OR'ed Message buffer (16-31) */ 246 FTM0_Ch0_Ch1_IRQn = 99, /**< FTM0 Channel 0 and 1 interrupt */ 247 FTM0_Ch2_Ch3_IRQn = 100, /**< FTM0 Channel 2 and 3 interrupt */ 248 FTM0_Ch4_Ch5_IRQn = 101, /**< FTM0 Channel 4 and 5 interrupt */ 249 FTM0_Ch6_Ch7_IRQn = 102, /**< FTM0 Channel 6 and 7 interrupt */ 250 FTM0_Fault_IRQn = 103, /**< FTM0 Fault interrupt */ 251 FTM0_Ovf_Reload_IRQn = 104, /**< FTM0 Counter overflow and Reload interrupt */ 252 FTM1_Ch0_Ch1_IRQn = 105, /**< FTM1 Channel 0 and 1 interrupt */ 253 FTM1_Ch2_Ch3_IRQn = 106, /**< FTM1 Channel 2 and 3 interrupt */ 254 FTM1_Ch4_Ch5_IRQn = 107, /**< FTM1 Channel 4 and 5 interrupt */ 255 FTM1_Ch6_Ch7_IRQn = 108, /**< FTM1 Channel 6 and 7 interrupt */ 256 FTM1_Fault_IRQn = 109, /**< FTM1 Fault interrupt */ 257 FTM1_Ovf_Reload_IRQn = 110, /**< FTM1 Counter overflow and Reload interrupt */ 258 FTM2_Ch0_Ch1_IRQn = 111, /**< FTM2 Channel 0 and 1 interrupt */ 259 FTM2_Ch2_Ch3_IRQn = 112, /**< FTM2 Channel 2 and 3 interrupt */ 260 FTM2_Ch4_Ch5_IRQn = 113, /**< FTM2 Channel 4 and 5 interrupt */ 261 FTM2_Ch6_Ch7_IRQn = 114, /**< FTM2 Channel 6 and 7 interrupt */ 262 FTM2_Fault_IRQn = 115, /**< FTM2 Fault interrupt */ 263 FTM2_Ovf_Reload_IRQn = 116, /**< FTM2 Counter overflow and Reload interrupt */ 264 FTM3_Ch0_Ch1_IRQn = 117, /**< FTM3 Channel 0 and 1 interrupt */ 265 FTM3_Ch2_Ch3_IRQn = 118, /**< FTM3 Channel 2 and 3 interrupt */ 266 FTM3_Ch4_Ch5_IRQn = 119, /**< FTM3 Channel 4 and 5 interrupt */ 267 FTM3_Ch6_Ch7_IRQn = 120, /**< FTM3 Channel 6 and 7 interrupt */ 268 FTM3_Fault_IRQn = 121, /**< FTM3 Fault interrupt */ 269 FTM3_Ovf_Reload_IRQn = 122, /**< FTM3 Counter overflow and Reload interrupt */ 270 FTM4_Ch0_Ch1_IRQn = 123, /**< FTM4 Channel 0 and 1 interrupt */ 271 FTM4_Ch2_Ch3_IRQn = 124, /**< FTM4 Channel 2 and 3 interrupt */ 272 FTM4_Ch4_Ch5_IRQn = 125, /**< FTM4 Channel 4 and 5 interrupt */ 273 FTM4_Ch6_Ch7_IRQn = 126, /**< FTM4 Channel 6 and 7 interrupt */ 274 FTM4_Fault_IRQn = 127, /**< FTM4 Fault interrupt */ 275 FTM4_Ovf_Reload_IRQn = 128, /**< FTM4 Counter overflow and Reload interrupt */ 276 FTM5_Ch0_Ch1_IRQn = 129, /**< FTM5 Channel 0 and 1 interrupt */ 277 FTM5_Ch2_Ch3_IRQn = 130, /**< FTM5 Channel 2 and 3 interrupt */ 278 FTM5_Ch4_Ch5_IRQn = 131, /**< FTM5 Channel 4 and 5 interrupt */ 279 FTM5_Ch6_Ch7_IRQn = 132, /**< FTM5 Channel 6 and 7 interrupt */ 280 FTM5_Fault_IRQn = 133, /**< FTM5 Fault interrupt */ 281 FTM5_Ovf_Reload_IRQn = 134, /**< FTM5 Counter overflow and Reload interrupt */ 282 FTM6_Ch0_Ch1_IRQn = 135, /**< FTM6 Channel 0 and 1 interrupt */ 283 FTM6_Ch2_Ch3_IRQn = 136, /**< FTM6 Channel 2 and 3 interrupt */ 284 FTM6_Ch4_Ch5_IRQn = 137, /**< FTM6 Channel 4 and 5 interrupt */ 285 FTM6_Ch6_Ch7_IRQn = 138, /**< FTM6 Channel 6 and 7 interrupt */ 286 FTM6_Fault_IRQn = 139, /**< FTM6 Fault interrupt */ 287 FTM6_Ovf_Reload_IRQn = 140, /**< FTM6 Counter overflow and Reload interrupt */ 288 FTM7_Ch0_Ch1_IRQn = 141, /**< FTM7 Channel 0 and 1 interrupt */ 289 FTM7_Ch2_Ch3_IRQn = 142, /**< FTM7 Channel 2 and 3 interrupt */ 290 FTM7_Ch4_Ch5_IRQn = 143, /**< FTM7 Channel 4 and 5 interrupt */ 291 FTM7_Ch6_Ch7_IRQn = 144, /**< FTM7 Channel 6 and 7 interrupt */ 292 FTM7_Fault_IRQn = 145, /**< FTM7 Fault interrupt */ 293 FTM7_Ovf_Reload_IRQn = 146 /**< FTM7 Counter overflow and Reload interrupt */ 294 } IRQn_Type; 295 296 /*! 297 * @} 298 */ /* end of group Interrupt_vector_numbers */ 299 300 301 /* ---------------------------------------------------------------------------- 302 -- Cortex M4 Core Configuration 303 ---------------------------------------------------------------------------- */ 304 305 /*! 306 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration 307 * @{ 308 */ 309 310 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 311 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ 312 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 313 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ 314 315 316 /*! 317 * @} 318 */ /* end of group Cortex_Core_Configuration */ 319 320 321 /* ---------------------------------------------------------------------------- 322 -- SDK Compatibility 323 ---------------------------------------------------------------------------- */ 324 325 /*! 326 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 327 * @{ 328 */ 329 330 /* No SDK compatibility issues. */ 331 332 /*! 333 * @} 334 */ /* end of group SDK_Compatibility_Symbols */ 335 336 337 #endif /* #if !defined(S32K148_COMMON_H_) */ 338 339
