1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K146_MPU.h 10 * @version 1.1 11 * @date 2022-01-31 12 * @brief Peripheral Access Layer for S32K146_MPU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K146_MPU_H_) /* Check if memory map has not been already included */ 58 #define S32K146_MPU_H_ 59 60 #include "S32K146_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MPU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MPU - Size of Registers Arrays */ 72 #define MPU_EAR_EDR_COUNT 4u 73 #define MPU_RGD_COUNT 8u 74 #define MPU_RGDAAC_COUNT 8u 75 76 /** MPU - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ 79 uint8_t RESERVED_0[12]; 80 struct { /* offset: 0x10, array step: 0x8 */ 81 __I uint32_t EAR; /**< Error Address Register, slave port 0..Error Address Register, slave port 3, array offset: 0x10, array step: 0x8 */ 82 __I uint32_t EDR; /**< Error Detail Register, slave port 0..Error Detail Register, slave port 3, array offset: 0x14, array step: 0x8 */ 83 } EAR_EDR[MPU_EAR_EDR_COUNT]; 84 uint8_t RESERVED_1[976]; 85 struct { /* offset: 0x400, array step: 0x10 */ 86 __IO uint32_t WORD0; /**< Region Descriptor 0, Word 0..Region Descriptor 7, Word 0, array offset: 0x400, array step: 0x10 */ 87 __IO uint32_t WORD1; /**< Region Descriptor 0, Word 1..Region Descriptor 7, Word 1, array offset: 0x404, array step: 0x10 */ 88 __IO uint32_t WORD2; /**< Region Descriptor 0, Word 2..Region Descriptor 7, Word 2, array offset: 0x408, array step: 0x10 */ 89 __IO uint32_t WORD3; /**< Region Descriptor 0, Word 3..Region Descriptor 7, Word 3, array offset: 0x40C, array step: 0x10 */ 90 } RGD[MPU_RGD_COUNT]; 91 uint8_t RESERVED_2[896]; 92 __IO uint32_t RGDAAC[MPU_RGDAAC_COUNT]; /**< Region Descriptor Alternate Access Control 0..Region Descriptor Alternate Access Control 7, array offset: 0x800, array step: 0x4 */ 93 } MPU_Type, *MPU_MemMapPtr; 94 95 /** Number of instances of the MPU module. */ 96 #define MPU_INSTANCE_COUNT (1u) 97 98 /* MPU - Peripheral instance base addresses */ 99 /** Peripheral MPU base address */ 100 #define IP_MPU_BASE (0x4000D000u) 101 /** Peripheral MPU base pointer */ 102 #define IP_MPU ((MPU_Type *)IP_MPU_BASE) 103 /** Array initializer of MPU peripheral base addresses */ 104 #define IP_MPU_BASE_ADDRS { IP_MPU_BASE } 105 /** Array initializer of MPU peripheral base pointers */ 106 #define IP_MPU_BASE_PTRS { IP_MPU } 107 108 /* ---------------------------------------------------------------------------- 109 -- MPU Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup MPU_Register_Masks MPU Register Masks 114 * @{ 115 */ 116 117 /*! @name CESR - Control/Error Status Register */ 118 /*! @{ */ 119 120 #define MPU_CESR_VLD_MASK (0x1U) 121 #define MPU_CESR_VLD_SHIFT (0U) 122 #define MPU_CESR_VLD_WIDTH (1U) 123 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK) 124 125 #define MPU_CESR_NRGD_MASK (0xF00U) 126 #define MPU_CESR_NRGD_SHIFT (8U) 127 #define MPU_CESR_NRGD_WIDTH (4U) 128 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK) 129 130 #define MPU_CESR_NSP_MASK (0xF000U) 131 #define MPU_CESR_NSP_SHIFT (12U) 132 #define MPU_CESR_NSP_WIDTH (4U) 133 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK) 134 135 #define MPU_CESR_HRL_MASK (0xF0000U) 136 #define MPU_CESR_HRL_SHIFT (16U) 137 #define MPU_CESR_HRL_WIDTH (4U) 138 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK) 139 140 #define MPU_CESR_SPERR3_MASK (0x10000000U) 141 #define MPU_CESR_SPERR3_SHIFT (28U) 142 #define MPU_CESR_SPERR3_WIDTH (1U) 143 #define MPU_CESR_SPERR3(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR3_SHIFT)) & MPU_CESR_SPERR3_MASK) 144 145 #define MPU_CESR_SPERR2_MASK (0x20000000U) 146 #define MPU_CESR_SPERR2_SHIFT (29U) 147 #define MPU_CESR_SPERR2_WIDTH (1U) 148 #define MPU_CESR_SPERR2(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR2_SHIFT)) & MPU_CESR_SPERR2_MASK) 149 150 #define MPU_CESR_SPERR1_MASK (0x40000000U) 151 #define MPU_CESR_SPERR1_SHIFT (30U) 152 #define MPU_CESR_SPERR1_WIDTH (1U) 153 #define MPU_CESR_SPERR1(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR1_SHIFT)) & MPU_CESR_SPERR1_MASK) 154 155 #define MPU_CESR_SPERR0_MASK (0x80000000U) 156 #define MPU_CESR_SPERR0_SHIFT (31U) 157 #define MPU_CESR_SPERR0_WIDTH (1U) 158 #define MPU_CESR_SPERR0(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR0_SHIFT)) & MPU_CESR_SPERR0_MASK) 159 /*! @} */ 160 161 /*! @name EAR - Error Address Register, slave port 0..Error Address Register, slave port 3 */ 162 /*! @{ */ 163 164 #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU) 165 #define MPU_EAR_EADDR_SHIFT (0U) 166 #define MPU_EAR_EADDR_WIDTH (32U) 167 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK) 168 /*! @} */ 169 170 /*! @name EDR - Error Detail Register, slave port 0..Error Detail Register, slave port 3 */ 171 /*! @{ */ 172 173 #define MPU_EDR_ERW_MASK (0x1U) 174 #define MPU_EDR_ERW_SHIFT (0U) 175 #define MPU_EDR_ERW_WIDTH (1U) 176 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK) 177 178 #define MPU_EDR_EATTR_MASK (0xEU) 179 #define MPU_EDR_EATTR_SHIFT (1U) 180 #define MPU_EDR_EATTR_WIDTH (3U) 181 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK) 182 183 #define MPU_EDR_EMN_MASK (0xF0U) 184 #define MPU_EDR_EMN_SHIFT (4U) 185 #define MPU_EDR_EMN_WIDTH (4U) 186 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK) 187 188 #define MPU_EDR_EPID_MASK (0xFF00U) 189 #define MPU_EDR_EPID_SHIFT (8U) 190 #define MPU_EDR_EPID_WIDTH (8U) 191 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK) 192 193 #define MPU_EDR_EACD_MASK (0xFFFF0000U) 194 #define MPU_EDR_EACD_SHIFT (16U) 195 #define MPU_EDR_EACD_WIDTH (16U) 196 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK) 197 /*! @} */ 198 199 /*! @name RGD_WORD0 - Region Descriptor 0, Word 0..Region Descriptor 7, Word 0 */ 200 /*! @{ */ 201 202 #define MPU_RGD_WORD0_SRTADDR_MASK (0xFFFFFFE0U) 203 #define MPU_RGD_WORD0_SRTADDR_SHIFT (5U) 204 #define MPU_RGD_WORD0_SRTADDR_WIDTH (27U) 205 #define MPU_RGD_WORD0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD0_SRTADDR_SHIFT)) & MPU_RGD_WORD0_SRTADDR_MASK) 206 /*! @} */ 207 208 /*! @name RGD_WORD1 - Region Descriptor 0, Word 1..Region Descriptor 7, Word 1 */ 209 /*! @{ */ 210 211 #define MPU_RGD_WORD1_ENDADDR_MASK (0xFFFFFFE0U) 212 #define MPU_RGD_WORD1_ENDADDR_SHIFT (5U) 213 #define MPU_RGD_WORD1_ENDADDR_WIDTH (27U) 214 #define MPU_RGD_WORD1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD1_ENDADDR_SHIFT)) & MPU_RGD_WORD1_ENDADDR_MASK) 215 /*! @} */ 216 217 /*! @name RGD_WORD2 - Region Descriptor 0, Word 2..Region Descriptor 7, Word 2 */ 218 /*! @{ */ 219 220 #define MPU_RGD_WORD2_M0UM_MASK (0x7U) 221 #define MPU_RGD_WORD2_M0UM_SHIFT (0U) 222 #define MPU_RGD_WORD2_M0UM_WIDTH (3U) 223 #define MPU_RGD_WORD2_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M0UM_SHIFT)) & MPU_RGD_WORD2_M0UM_MASK) 224 225 #define MPU_RGD_WORD2_M0SM_MASK (0x18U) 226 #define MPU_RGD_WORD2_M0SM_SHIFT (3U) 227 #define MPU_RGD_WORD2_M0SM_WIDTH (2U) 228 #define MPU_RGD_WORD2_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M0SM_SHIFT)) & MPU_RGD_WORD2_M0SM_MASK) 229 230 #define MPU_RGD_WORD2_M0PE_MASK (0x20U) 231 #define MPU_RGD_WORD2_M0PE_SHIFT (5U) 232 #define MPU_RGD_WORD2_M0PE_WIDTH (1U) 233 #define MPU_RGD_WORD2_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M0PE_SHIFT)) & MPU_RGD_WORD2_M0PE_MASK) 234 235 #define MPU_RGD_WORD2_M1UM_MASK (0x1C0U) 236 #define MPU_RGD_WORD2_M1UM_SHIFT (6U) 237 #define MPU_RGD_WORD2_M1UM_WIDTH (3U) 238 #define MPU_RGD_WORD2_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M1UM_SHIFT)) & MPU_RGD_WORD2_M1UM_MASK) 239 240 #define MPU_RGD_WORD2_M1SM_MASK (0x600U) 241 #define MPU_RGD_WORD2_M1SM_SHIFT (9U) 242 #define MPU_RGD_WORD2_M1SM_WIDTH (2U) 243 #define MPU_RGD_WORD2_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M1SM_SHIFT)) & MPU_RGD_WORD2_M1SM_MASK) 244 245 #define MPU_RGD_WORD2_M1PE_MASK (0x800U) 246 #define MPU_RGD_WORD2_M1PE_SHIFT (11U) 247 #define MPU_RGD_WORD2_M1PE_WIDTH (1U) 248 #define MPU_RGD_WORD2_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M1PE_SHIFT)) & MPU_RGD_WORD2_M1PE_MASK) 249 250 #define MPU_RGD_WORD2_M2UM_MASK (0x7000U) 251 #define MPU_RGD_WORD2_M2UM_SHIFT (12U) 252 #define MPU_RGD_WORD2_M2UM_WIDTH (3U) 253 #define MPU_RGD_WORD2_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M2UM_SHIFT)) & MPU_RGD_WORD2_M2UM_MASK) 254 255 #define MPU_RGD_WORD2_M2SM_MASK (0x18000U) 256 #define MPU_RGD_WORD2_M2SM_SHIFT (15U) 257 #define MPU_RGD_WORD2_M2SM_WIDTH (2U) 258 #define MPU_RGD_WORD2_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M2SM_SHIFT)) & MPU_RGD_WORD2_M2SM_MASK) 259 260 #define MPU_RGD_WORD2_M3UM_MASK (0x1C0000U) 261 #define MPU_RGD_WORD2_M3UM_SHIFT (18U) 262 #define MPU_RGD_WORD2_M3UM_WIDTH (3U) 263 #define MPU_RGD_WORD2_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M3UM_SHIFT)) & MPU_RGD_WORD2_M3UM_MASK) 264 265 #define MPU_RGD_WORD2_M3SM_MASK (0x600000U) 266 #define MPU_RGD_WORD2_M3SM_SHIFT (21U) 267 #define MPU_RGD_WORD2_M3SM_WIDTH (2U) 268 #define MPU_RGD_WORD2_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M3SM_SHIFT)) & MPU_RGD_WORD2_M3SM_MASK) 269 270 #define MPU_RGD_WORD2_M4WE_MASK (0x1000000U) 271 #define MPU_RGD_WORD2_M4WE_SHIFT (24U) 272 #define MPU_RGD_WORD2_M4WE_WIDTH (1U) 273 #define MPU_RGD_WORD2_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M4WE_SHIFT)) & MPU_RGD_WORD2_M4WE_MASK) 274 275 #define MPU_RGD_WORD2_M4RE_MASK (0x2000000U) 276 #define MPU_RGD_WORD2_M4RE_SHIFT (25U) 277 #define MPU_RGD_WORD2_M4RE_WIDTH (1U) 278 #define MPU_RGD_WORD2_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M4RE_SHIFT)) & MPU_RGD_WORD2_M4RE_MASK) 279 280 #define MPU_RGD_WORD2_M5WE_MASK (0x4000000U) 281 #define MPU_RGD_WORD2_M5WE_SHIFT (26U) 282 #define MPU_RGD_WORD2_M5WE_WIDTH (1U) 283 #define MPU_RGD_WORD2_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M5WE_SHIFT)) & MPU_RGD_WORD2_M5WE_MASK) 284 285 #define MPU_RGD_WORD2_M5RE_MASK (0x8000000U) 286 #define MPU_RGD_WORD2_M5RE_SHIFT (27U) 287 #define MPU_RGD_WORD2_M5RE_WIDTH (1U) 288 #define MPU_RGD_WORD2_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M5RE_SHIFT)) & MPU_RGD_WORD2_M5RE_MASK) 289 290 #define MPU_RGD_WORD2_M6WE_MASK (0x10000000U) 291 #define MPU_RGD_WORD2_M6WE_SHIFT (28U) 292 #define MPU_RGD_WORD2_M6WE_WIDTH (1U) 293 #define MPU_RGD_WORD2_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M6WE_SHIFT)) & MPU_RGD_WORD2_M6WE_MASK) 294 295 #define MPU_RGD_WORD2_M6RE_MASK (0x20000000U) 296 #define MPU_RGD_WORD2_M6RE_SHIFT (29U) 297 #define MPU_RGD_WORD2_M6RE_WIDTH (1U) 298 #define MPU_RGD_WORD2_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M6RE_SHIFT)) & MPU_RGD_WORD2_M6RE_MASK) 299 300 #define MPU_RGD_WORD2_M7WE_MASK (0x40000000U) 301 #define MPU_RGD_WORD2_M7WE_SHIFT (30U) 302 #define MPU_RGD_WORD2_M7WE_WIDTH (1U) 303 #define MPU_RGD_WORD2_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M7WE_SHIFT)) & MPU_RGD_WORD2_M7WE_MASK) 304 305 #define MPU_RGD_WORD2_M7RE_MASK (0x80000000U) 306 #define MPU_RGD_WORD2_M7RE_SHIFT (31U) 307 #define MPU_RGD_WORD2_M7RE_WIDTH (1U) 308 #define MPU_RGD_WORD2_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD2_M7RE_SHIFT)) & MPU_RGD_WORD2_M7RE_MASK) 309 /*! @} */ 310 311 /*! @name RGD_WORD3 - Region Descriptor 0, Word 3..Region Descriptor 7, Word 3 */ 312 /*! @{ */ 313 314 #define MPU_RGD_WORD3_VLD_MASK (0x1U) 315 #define MPU_RGD_WORD3_VLD_SHIFT (0U) 316 #define MPU_RGD_WORD3_VLD_WIDTH (1U) 317 #define MPU_RGD_WORD3_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD3_VLD_SHIFT)) & MPU_RGD_WORD3_VLD_MASK) 318 319 #define MPU_RGD_WORD3_PIDMASK_MASK (0xFF0000U) 320 #define MPU_RGD_WORD3_PIDMASK_SHIFT (16U) 321 #define MPU_RGD_WORD3_PIDMASK_WIDTH (8U) 322 #define MPU_RGD_WORD3_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD3_PIDMASK_SHIFT)) & MPU_RGD_WORD3_PIDMASK_MASK) 323 324 #define MPU_RGD_WORD3_PID_MASK (0xFF000000U) 325 #define MPU_RGD_WORD3_PID_SHIFT (24U) 326 #define MPU_RGD_WORD3_PID_WIDTH (8U) 327 #define MPU_RGD_WORD3_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGD_WORD3_PID_SHIFT)) & MPU_RGD_WORD3_PID_MASK) 328 /*! @} */ 329 330 /*! @name RGDAAC - Region Descriptor Alternate Access Control 0..Region Descriptor Alternate Access Control 7 */ 331 /*! @{ */ 332 333 #define MPU_RGDAAC_M0UM_MASK (0x7U) 334 #define MPU_RGDAAC_M0UM_SHIFT (0U) 335 #define MPU_RGDAAC_M0UM_WIDTH (3U) 336 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK) 337 338 #define MPU_RGDAAC_M0SM_MASK (0x18U) 339 #define MPU_RGDAAC_M0SM_SHIFT (3U) 340 #define MPU_RGDAAC_M0SM_WIDTH (2U) 341 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK) 342 343 #define MPU_RGDAAC_M0PE_MASK (0x20U) 344 #define MPU_RGDAAC_M0PE_SHIFT (5U) 345 #define MPU_RGDAAC_M0PE_WIDTH (1U) 346 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK) 347 348 #define MPU_RGDAAC_M1UM_MASK (0x1C0U) 349 #define MPU_RGDAAC_M1UM_SHIFT (6U) 350 #define MPU_RGDAAC_M1UM_WIDTH (3U) 351 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK) 352 353 #define MPU_RGDAAC_M1SM_MASK (0x600U) 354 #define MPU_RGDAAC_M1SM_SHIFT (9U) 355 #define MPU_RGDAAC_M1SM_WIDTH (2U) 356 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK) 357 358 #define MPU_RGDAAC_M1PE_MASK (0x800U) 359 #define MPU_RGDAAC_M1PE_SHIFT (11U) 360 #define MPU_RGDAAC_M1PE_WIDTH (1U) 361 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK) 362 363 #define MPU_RGDAAC_M2UM_MASK (0x7000U) 364 #define MPU_RGDAAC_M2UM_SHIFT (12U) 365 #define MPU_RGDAAC_M2UM_WIDTH (3U) 366 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK) 367 368 #define MPU_RGDAAC_M2SM_MASK (0x18000U) 369 #define MPU_RGDAAC_M2SM_SHIFT (15U) 370 #define MPU_RGDAAC_M2SM_WIDTH (2U) 371 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK) 372 373 #define MPU_RGDAAC_M3UM_MASK (0x1C0000U) 374 #define MPU_RGDAAC_M3UM_SHIFT (18U) 375 #define MPU_RGDAAC_M3UM_WIDTH (3U) 376 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK) 377 378 #define MPU_RGDAAC_M3SM_MASK (0x600000U) 379 #define MPU_RGDAAC_M3SM_SHIFT (21U) 380 #define MPU_RGDAAC_M3SM_WIDTH (2U) 381 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK) 382 383 #define MPU_RGDAAC_M4WE_MASK (0x1000000U) 384 #define MPU_RGDAAC_M4WE_SHIFT (24U) 385 #define MPU_RGDAAC_M4WE_WIDTH (1U) 386 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK) 387 388 #define MPU_RGDAAC_M4RE_MASK (0x2000000U) 389 #define MPU_RGDAAC_M4RE_SHIFT (25U) 390 #define MPU_RGDAAC_M4RE_WIDTH (1U) 391 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK) 392 393 #define MPU_RGDAAC_M5WE_MASK (0x4000000U) 394 #define MPU_RGDAAC_M5WE_SHIFT (26U) 395 #define MPU_RGDAAC_M5WE_WIDTH (1U) 396 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK) 397 398 #define MPU_RGDAAC_M5RE_MASK (0x8000000U) 399 #define MPU_RGDAAC_M5RE_SHIFT (27U) 400 #define MPU_RGDAAC_M5RE_WIDTH (1U) 401 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK) 402 403 #define MPU_RGDAAC_M6WE_MASK (0x10000000U) 404 #define MPU_RGDAAC_M6WE_SHIFT (28U) 405 #define MPU_RGDAAC_M6WE_WIDTH (1U) 406 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK) 407 408 #define MPU_RGDAAC_M6RE_MASK (0x20000000U) 409 #define MPU_RGDAAC_M6RE_SHIFT (29U) 410 #define MPU_RGDAAC_M6RE_WIDTH (1U) 411 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK) 412 413 #define MPU_RGDAAC_M7WE_MASK (0x40000000U) 414 #define MPU_RGDAAC_M7WE_SHIFT (30U) 415 #define MPU_RGDAAC_M7WE_WIDTH (1U) 416 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK) 417 418 #define MPU_RGDAAC_M7RE_MASK (0x80000000U) 419 #define MPU_RGDAAC_M7RE_SHIFT (31U) 420 #define MPU_RGDAAC_M7RE_WIDTH (1U) 421 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK) 422 /*! @} */ 423 424 /*! 425 * @} 426 */ /* end of group MPU_Register_Masks */ 427 428 /*! 429 * @} 430 */ /* end of group MPU_Peripheral_Access_Layer */ 431 432 #endif /* #if !defined(S32K146_MPU_H_) */ 433
