1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144_PMC.h 10 * @version 1.1 11 * @date 2022-02-07 12 * @brief Peripheral Access Layer for S32K144_PMC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144_PMC_H_) /* Check if memory map has not been already included */ 58 #define S32K144_PMC_H_ 59 60 #include "S32K144_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PMC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PMC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ 74 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ 75 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ 76 uint8_t RESERVED_0[1]; 77 __IO uint8_t LPOTRIM; /**< Low Power Oscillator Trim Register, offset: 0x4 */ 78 } PMC_Type, *PMC_MemMapPtr; 79 80 /** Number of instances of the PMC module. */ 81 #define PMC_INSTANCE_COUNT (1u) 82 83 /* PMC - Peripheral instance base addresses */ 84 /** Peripheral PMC base address */ 85 #define IP_PMC_BASE (0x4007D000u) 86 /** Peripheral PMC base pointer */ 87 #define IP_PMC ((PMC_Type *)IP_PMC_BASE) 88 /** Array initializer of PMC peripheral base addresses */ 89 #define IP_PMC_BASE_ADDRS { IP_PMC_BASE } 90 /** Array initializer of PMC peripheral base pointers */ 91 #define IP_PMC_BASE_PTRS { IP_PMC } 92 93 /* ---------------------------------------------------------------------------- 94 -- PMC Register Masks 95 ---------------------------------------------------------------------------- */ 96 97 /*! 98 * @addtogroup PMC_Register_Masks PMC Register Masks 99 * @{ 100 */ 101 102 /*! @name LVDSC1 - Low Voltage Detect Status and Control 1 Register */ 103 /*! @{ */ 104 105 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 106 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 107 #define PMC_LVDSC1_LVDRE_WIDTH (1U) 108 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 109 110 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 111 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 112 #define PMC_LVDSC1_LVDIE_WIDTH (1U) 113 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 114 115 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 116 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 117 #define PMC_LVDSC1_LVDACK_WIDTH (1U) 118 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 119 120 #define PMC_LVDSC1_LVDF_MASK (0x80U) 121 #define PMC_LVDSC1_LVDF_SHIFT (7U) 122 #define PMC_LVDSC1_LVDF_WIDTH (1U) 123 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 124 /*! @} */ 125 126 /*! @name LVDSC2 - Low Voltage Detect Status and Control 2 Register */ 127 /*! @{ */ 128 129 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 130 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 131 #define PMC_LVDSC2_LVWIE_WIDTH (1U) 132 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 133 134 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 135 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 136 #define PMC_LVDSC2_LVWACK_WIDTH (1U) 137 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 138 139 #define PMC_LVDSC2_LVWF_MASK (0x80U) 140 #define PMC_LVDSC2_LVWF_SHIFT (7U) 141 #define PMC_LVDSC2_LVWF_WIDTH (1U) 142 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 143 /*! @} */ 144 145 /*! @name REGSC - Regulator Status and Control Register */ 146 /*! @{ */ 147 148 #define PMC_REGSC_BIASEN_MASK (0x1U) 149 #define PMC_REGSC_BIASEN_SHIFT (0U) 150 #define PMC_REGSC_BIASEN_WIDTH (1U) 151 #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BIASEN_SHIFT)) & PMC_REGSC_BIASEN_MASK) 152 153 #define PMC_REGSC_CLKBIASDIS_MASK (0x2U) 154 #define PMC_REGSC_CLKBIASDIS_SHIFT (1U) 155 #define PMC_REGSC_CLKBIASDIS_WIDTH (1U) 156 #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_CLKBIASDIS_SHIFT)) & PMC_REGSC_CLKBIASDIS_MASK) 157 158 #define PMC_REGSC_REGFPM_MASK (0x4U) 159 #define PMC_REGSC_REGFPM_SHIFT (2U) 160 #define PMC_REGSC_REGFPM_WIDTH (1U) 161 #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGFPM_SHIFT)) & PMC_REGSC_REGFPM_MASK) 162 163 #define PMC_REGSC_LPOSTAT_MASK (0x40U) 164 #define PMC_REGSC_LPOSTAT_SHIFT (6U) 165 #define PMC_REGSC_LPOSTAT_WIDTH (1U) 166 #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_LPOSTAT_SHIFT)) & PMC_REGSC_LPOSTAT_MASK) 167 168 #define PMC_REGSC_LPODIS_MASK (0x80U) 169 #define PMC_REGSC_LPODIS_SHIFT (7U) 170 #define PMC_REGSC_LPODIS_WIDTH (1U) 171 #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_LPODIS_SHIFT)) & PMC_REGSC_LPODIS_MASK) 172 /*! @} */ 173 174 /*! @name LPOTRIM - Low Power Oscillator Trim Register */ 175 /*! @{ */ 176 177 #define PMC_LPOTRIM_LPOTRIM_MASK (0x1FU) 178 #define PMC_LPOTRIM_LPOTRIM_SHIFT (0U) 179 #define PMC_LPOTRIM_LPOTRIM_WIDTH (5U) 180 #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x)) << PMC_LPOTRIM_LPOTRIM_SHIFT)) & PMC_LPOTRIM_LPOTRIM_MASK) 181 /*! @} */ 182 183 /*! 184 * @} 185 */ /* end of group PMC_Register_Masks */ 186 187 /*! 188 * @} 189 */ /* end of group PMC_Peripheral_Access_Layer */ 190 191 #endif /* #if !defined(S32K144_PMC_H_) */ 192
