1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144_FTFC.h 10 * @version 1.1 11 * @date 2022-02-07 12 * @brief Peripheral Access Layer for S32K144_FTFC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144_FTFC_H_) /* Check if memory map has not been already included */ 58 #define S32K144_FTFC_H_ 59 60 #include "S32K144_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FTFC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FTFC_Peripheral_Access_Layer FTFC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FTFC - Size of Registers Arrays */ 72 #define FTFC_FCCOB_COUNT 12u 73 #define FTFC_FPROT_COUNT 4u 74 75 /** FTFC - Register Layout Typedef */ 76 typedef struct { 77 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 78 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 79 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 80 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 81 __IO uint8_t FCCOB[FTFC_FCCOB_COUNT]; /**< Flash Common Command Object Registers, array offset: 0x4, array step: 0x1 */ 82 __IO uint8_t FPROT[FTFC_FPROT_COUNT]; /**< Program Flash Protection Registers, array offset: 0x10, array step: 0x1 */ 83 uint8_t RESERVED_0[2]; 84 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ 85 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ 86 uint8_t RESERVED_1[20]; 87 __I uint8_t FCSESTAT; /**< Flash CSEc Status Register, offset: 0x2C */ 88 uint8_t RESERVED_2[1]; 89 __IO uint8_t FERSTAT; /**< Flash Error Status Register, offset: 0x2E */ 90 __IO uint8_t FERCNFG; /**< Flash Error Configuration Register, offset: 0x2F */ 91 } FTFC_Type, *FTFC_MemMapPtr; 92 93 /** Number of instances of the FTFC module. */ 94 #define FTFC_INSTANCE_COUNT (1u) 95 96 /* FTFC - Peripheral instance base addresses */ 97 /** Peripheral FTFC base address */ 98 #define IP_FTFC_BASE (0x40020000u) 99 /** Peripheral FTFC base pointer */ 100 #define IP_FTFC ((FTFC_Type *)IP_FTFC_BASE) 101 /** Array initializer of FTFC peripheral base addresses */ 102 #define IP_FTFC_BASE_ADDRS { IP_FTFC_BASE } 103 /** Array initializer of FTFC peripheral base pointers */ 104 #define IP_FTFC_BASE_PTRS { IP_FTFC } 105 106 /* ---------------------------------------------------------------------------- 107 -- FTFC Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup FTFC_Register_Masks FTFC Register Masks 112 * @{ 113 */ 114 115 /*! @name FSTAT - Flash Status Register */ 116 /*! @{ */ 117 118 #define FTFC_FSTAT_MGSTAT0_MASK (0x1U) 119 #define FTFC_FSTAT_MGSTAT0_SHIFT (0U) 120 #define FTFC_FSTAT_MGSTAT0_WIDTH (1U) 121 #define FTFC_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSTAT_MGSTAT0_SHIFT)) & FTFC_FSTAT_MGSTAT0_MASK) 122 123 #define FTFC_FSTAT_FPVIOL_MASK (0x10U) 124 #define FTFC_FSTAT_FPVIOL_SHIFT (4U) 125 #define FTFC_FSTAT_FPVIOL_WIDTH (1U) 126 #define FTFC_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSTAT_FPVIOL_SHIFT)) & FTFC_FSTAT_FPVIOL_MASK) 127 128 #define FTFC_FSTAT_ACCERR_MASK (0x20U) 129 #define FTFC_FSTAT_ACCERR_SHIFT (5U) 130 #define FTFC_FSTAT_ACCERR_WIDTH (1U) 131 #define FTFC_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSTAT_ACCERR_SHIFT)) & FTFC_FSTAT_ACCERR_MASK) 132 133 #define FTFC_FSTAT_RDCOLERR_MASK (0x40U) 134 #define FTFC_FSTAT_RDCOLERR_SHIFT (6U) 135 #define FTFC_FSTAT_RDCOLERR_WIDTH (1U) 136 #define FTFC_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSTAT_RDCOLERR_SHIFT)) & FTFC_FSTAT_RDCOLERR_MASK) 137 138 #define FTFC_FSTAT_CCIF_MASK (0x80U) 139 #define FTFC_FSTAT_CCIF_SHIFT (7U) 140 #define FTFC_FSTAT_CCIF_WIDTH (1U) 141 #define FTFC_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSTAT_CCIF_SHIFT)) & FTFC_FSTAT_CCIF_MASK) 142 /*! @} */ 143 144 /*! @name FCNFG - Flash Configuration Register */ 145 /*! @{ */ 146 147 #define FTFC_FCNFG_EEERDY_MASK (0x1U) 148 #define FTFC_FCNFG_EEERDY_SHIFT (0U) 149 #define FTFC_FCNFG_EEERDY_WIDTH (1U) 150 #define FTFC_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCNFG_EEERDY_SHIFT)) & FTFC_FCNFG_EEERDY_MASK) 151 152 #define FTFC_FCNFG_RAMRDY_MASK (0x2U) 153 #define FTFC_FCNFG_RAMRDY_SHIFT (1U) 154 #define FTFC_FCNFG_RAMRDY_WIDTH (1U) 155 #define FTFC_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCNFG_RAMRDY_SHIFT)) & FTFC_FCNFG_RAMRDY_MASK) 156 157 #define FTFC_FCNFG_ERSSUSP_MASK (0x10U) 158 #define FTFC_FCNFG_ERSSUSP_SHIFT (4U) 159 #define FTFC_FCNFG_ERSSUSP_WIDTH (1U) 160 #define FTFC_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCNFG_ERSSUSP_SHIFT)) & FTFC_FCNFG_ERSSUSP_MASK) 161 162 #define FTFC_FCNFG_ERSAREQ_MASK (0x20U) 163 #define FTFC_FCNFG_ERSAREQ_SHIFT (5U) 164 #define FTFC_FCNFG_ERSAREQ_WIDTH (1U) 165 #define FTFC_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCNFG_ERSAREQ_SHIFT)) & FTFC_FCNFG_ERSAREQ_MASK) 166 167 #define FTFC_FCNFG_RDCOLLIE_MASK (0x40U) 168 #define FTFC_FCNFG_RDCOLLIE_SHIFT (6U) 169 #define FTFC_FCNFG_RDCOLLIE_WIDTH (1U) 170 #define FTFC_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCNFG_RDCOLLIE_SHIFT)) & FTFC_FCNFG_RDCOLLIE_MASK) 171 172 #define FTFC_FCNFG_CCIE_MASK (0x80U) 173 #define FTFC_FCNFG_CCIE_SHIFT (7U) 174 #define FTFC_FCNFG_CCIE_WIDTH (1U) 175 #define FTFC_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCNFG_CCIE_SHIFT)) & FTFC_FCNFG_CCIE_MASK) 176 /*! @} */ 177 178 /*! @name FSEC - Flash Security Register */ 179 /*! @{ */ 180 181 #define FTFC_FSEC_SEC_MASK (0x3U) 182 #define FTFC_FSEC_SEC_SHIFT (0U) 183 #define FTFC_FSEC_SEC_WIDTH (2U) 184 #define FTFC_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSEC_SEC_SHIFT)) & FTFC_FSEC_SEC_MASK) 185 186 #define FTFC_FSEC_FSLACC_MASK (0xCU) 187 #define FTFC_FSEC_FSLACC_SHIFT (2U) 188 #define FTFC_FSEC_FSLACC_WIDTH (2U) 189 #define FTFC_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSEC_FSLACC_SHIFT)) & FTFC_FSEC_FSLACC_MASK) 190 191 #define FTFC_FSEC_MEEN_MASK (0x30U) 192 #define FTFC_FSEC_MEEN_SHIFT (4U) 193 #define FTFC_FSEC_MEEN_WIDTH (2U) 194 #define FTFC_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSEC_MEEN_SHIFT)) & FTFC_FSEC_MEEN_MASK) 195 196 #define FTFC_FSEC_KEYEN_MASK (0xC0U) 197 #define FTFC_FSEC_KEYEN_SHIFT (6U) 198 #define FTFC_FSEC_KEYEN_WIDTH (2U) 199 #define FTFC_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FSEC_KEYEN_SHIFT)) & FTFC_FSEC_KEYEN_MASK) 200 /*! @} */ 201 202 /*! @name FOPT - Flash Option Register */ 203 /*! @{ */ 204 205 #define FTFC_FOPT_OPT_MASK (0xFFU) 206 #define FTFC_FOPT_OPT_SHIFT (0U) 207 #define FTFC_FOPT_OPT_WIDTH (8U) 208 #define FTFC_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FOPT_OPT_SHIFT)) & FTFC_FOPT_OPT_MASK) 209 /*! @} */ 210 211 /*! @name FCCOB - Flash Common Command Object Registers */ 212 /*! @{ */ 213 214 #define FTFC_FCCOB_CCOBn_MASK (0xFFU) 215 #define FTFC_FCCOB_CCOBn_SHIFT (0U) 216 #define FTFC_FCCOB_CCOBn_WIDTH (8U) 217 #define FTFC_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCCOB_CCOBn_SHIFT)) & FTFC_FCCOB_CCOBn_MASK) 218 /*! @} */ 219 220 /*! @name FPROT - Program Flash Protection Registers */ 221 /*! @{ */ 222 223 #define FTFC_FPROT_PROT_MASK (0xFFU) 224 #define FTFC_FPROT_PROT_SHIFT (0U) 225 #define FTFC_FPROT_PROT_WIDTH (8U) 226 #define FTFC_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FPROT_PROT_SHIFT)) & FTFC_FPROT_PROT_MASK) 227 /*! @} */ 228 229 /*! @name FEPROT - EEPROM Protection Register */ 230 /*! @{ */ 231 232 #define FTFC_FEPROT_EPROT_MASK (0xFFU) 233 #define FTFC_FEPROT_EPROT_SHIFT (0U) 234 #define FTFC_FEPROT_EPROT_WIDTH (8U) 235 #define FTFC_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FEPROT_EPROT_SHIFT)) & FTFC_FEPROT_EPROT_MASK) 236 /*! @} */ 237 238 /*! @name FDPROT - Data Flash Protection Register */ 239 /*! @{ */ 240 241 #define FTFC_FDPROT_DPROT_MASK (0xFFU) 242 #define FTFC_FDPROT_DPROT_SHIFT (0U) 243 #define FTFC_FDPROT_DPROT_WIDTH (8U) 244 #define FTFC_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FDPROT_DPROT_SHIFT)) & FTFC_FDPROT_DPROT_MASK) 245 /*! @} */ 246 247 /*! @name FCSESTAT - Flash CSEc Status Register */ 248 /*! @{ */ 249 250 #define FTFC_FCSESTAT_BSY_MASK (0x1U) 251 #define FTFC_FCSESTAT_BSY_SHIFT (0U) 252 #define FTFC_FCSESTAT_BSY_WIDTH (1U) 253 #define FTFC_FCSESTAT_BSY(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_BSY_SHIFT)) & FTFC_FCSESTAT_BSY_MASK) 254 255 #define FTFC_FCSESTAT_SB_MASK (0x2U) 256 #define FTFC_FCSESTAT_SB_SHIFT (1U) 257 #define FTFC_FCSESTAT_SB_WIDTH (1U) 258 #define FTFC_FCSESTAT_SB(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_SB_SHIFT)) & FTFC_FCSESTAT_SB_MASK) 259 260 #define FTFC_FCSESTAT_BIN_MASK (0x4U) 261 #define FTFC_FCSESTAT_BIN_SHIFT (2U) 262 #define FTFC_FCSESTAT_BIN_WIDTH (1U) 263 #define FTFC_FCSESTAT_BIN(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_BIN_SHIFT)) & FTFC_FCSESTAT_BIN_MASK) 264 265 #define FTFC_FCSESTAT_BFN_MASK (0x8U) 266 #define FTFC_FCSESTAT_BFN_SHIFT (3U) 267 #define FTFC_FCSESTAT_BFN_WIDTH (1U) 268 #define FTFC_FCSESTAT_BFN(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_BFN_SHIFT)) & FTFC_FCSESTAT_BFN_MASK) 269 270 #define FTFC_FCSESTAT_BOK_MASK (0x10U) 271 #define FTFC_FCSESTAT_BOK_SHIFT (4U) 272 #define FTFC_FCSESTAT_BOK_WIDTH (1U) 273 #define FTFC_FCSESTAT_BOK(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_BOK_SHIFT)) & FTFC_FCSESTAT_BOK_MASK) 274 275 #define FTFC_FCSESTAT_RIN_MASK (0x20U) 276 #define FTFC_FCSESTAT_RIN_SHIFT (5U) 277 #define FTFC_FCSESTAT_RIN_WIDTH (1U) 278 #define FTFC_FCSESTAT_RIN(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_RIN_SHIFT)) & FTFC_FCSESTAT_RIN_MASK) 279 280 #define FTFC_FCSESTAT_EDB_MASK (0x40U) 281 #define FTFC_FCSESTAT_EDB_SHIFT (6U) 282 #define FTFC_FCSESTAT_EDB_WIDTH (1U) 283 #define FTFC_FCSESTAT_EDB(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_EDB_SHIFT)) & FTFC_FCSESTAT_EDB_MASK) 284 285 #define FTFC_FCSESTAT_IDB_MASK (0x80U) 286 #define FTFC_FCSESTAT_IDB_SHIFT (7U) 287 #define FTFC_FCSESTAT_IDB_WIDTH (1U) 288 #define FTFC_FCSESTAT_IDB(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FCSESTAT_IDB_SHIFT)) & FTFC_FCSESTAT_IDB_MASK) 289 /*! @} */ 290 291 /*! @name FERSTAT - Flash Error Status Register */ 292 /*! @{ */ 293 294 #define FTFC_FERSTAT_DFDIF_MASK (0x2U) 295 #define FTFC_FERSTAT_DFDIF_SHIFT (1U) 296 #define FTFC_FERSTAT_DFDIF_WIDTH (1U) 297 #define FTFC_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FERSTAT_DFDIF_SHIFT)) & FTFC_FERSTAT_DFDIF_MASK) 298 /*! @} */ 299 300 /*! @name FERCNFG - Flash Error Configuration Register */ 301 /*! @{ */ 302 303 #define FTFC_FERCNFG_DFDIE_MASK (0x2U) 304 #define FTFC_FERCNFG_DFDIE_SHIFT (1U) 305 #define FTFC_FERCNFG_DFDIE_WIDTH (1U) 306 #define FTFC_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FERCNFG_DFDIE_SHIFT)) & FTFC_FERCNFG_DFDIE_MASK) 307 308 #define FTFC_FERCNFG_FDFD_MASK (0x20U) 309 #define FTFC_FERCNFG_FDFD_SHIFT (5U) 310 #define FTFC_FERCNFG_FDFD_WIDTH (1U) 311 #define FTFC_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x)) << FTFC_FERCNFG_FDFD_SHIFT)) & FTFC_FERCNFG_FDFD_MASK) 312 /*! @} */ 313 314 /*! 315 * @} 316 */ /* end of group FTFC_Register_Masks */ 317 318 /*! 319 * @} 320 */ /* end of group FTFC_Peripheral_Access_Layer */ 321 322 #endif /* #if !defined(S32K144_FTFC_H_) */ 323
