1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144_ADC.h 10 * @version 1.1 11 * @date 2022-02-07 12 * @brief Peripheral Access Layer for S32K144_ADC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144_ADC_H_) /* Check if memory map has not been already included */ 58 #define S32K144_ADC_H_ 59 60 #include "S32K144_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ADC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ADC - Size of Registers Arrays */ 72 #define ADC_SC1_COUNT 16u 73 #define ADC_R_COUNT 16u 74 #define ADC_CV_COUNT 2u 75 76 /** ADC - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ 79 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ 80 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ 81 __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ 82 __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ 83 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ 84 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ 85 __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ 86 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ 87 __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ 88 __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ 89 __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ 90 __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ 91 __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ 92 __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ 93 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ 94 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ 95 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ 96 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ 97 __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ 98 __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ 99 __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ 100 __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ 101 __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ 102 __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ 103 __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ 104 __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ 105 __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ 106 } ADC_Type, *ADC_MemMapPtr; 107 108 /** Number of instances of the ADC module. */ 109 #define ADC_INSTANCE_COUNT (2u) 110 111 /* ADC - Peripheral instance base addresses */ 112 /** Peripheral ADC0 base address */ 113 #define IP_ADC0_BASE (0x4003B000u) 114 /** Peripheral ADC0 base pointer */ 115 #define IP_ADC0 ((ADC_Type *)IP_ADC0_BASE) 116 /** Peripheral ADC1 base address */ 117 #define IP_ADC1_BASE (0x40027000u) 118 /** Peripheral ADC1 base pointer */ 119 #define IP_ADC1 ((ADC_Type *)IP_ADC1_BASE) 120 /** Array initializer of ADC peripheral base addresses */ 121 #define IP_ADC_BASE_ADDRS { IP_ADC0_BASE, IP_ADC1_BASE } 122 /** Array initializer of ADC peripheral base pointers */ 123 #define IP_ADC_BASE_PTRS { IP_ADC0, IP_ADC1 } 124 125 /* ---------------------------------------------------------------------------- 126 -- ADC Register Masks 127 ---------------------------------------------------------------------------- */ 128 129 /*! 130 * @addtogroup ADC_Register_Masks ADC Register Masks 131 * @{ 132 */ 133 134 /*! @name SC1 - ADC Status and Control Register 1 */ 135 /*! @{ */ 136 137 #define ADC_SC1_ADCH_MASK (0x1FU) 138 #define ADC_SC1_ADCH_SHIFT (0U) 139 #define ADC_SC1_ADCH_WIDTH (5U) 140 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 141 142 #define ADC_SC1_AIEN_MASK (0x40U) 143 #define ADC_SC1_AIEN_SHIFT (6U) 144 #define ADC_SC1_AIEN_WIDTH (1U) 145 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 146 147 #define ADC_SC1_COCO_MASK (0x80U) 148 #define ADC_SC1_COCO_SHIFT (7U) 149 #define ADC_SC1_COCO_WIDTH (1U) 150 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 151 /*! @} */ 152 153 /*! @name CFG1 - ADC Configuration Register 1 */ 154 /*! @{ */ 155 156 #define ADC_CFG1_ADICLK_MASK (0x3U) 157 #define ADC_CFG1_ADICLK_SHIFT (0U) 158 #define ADC_CFG1_ADICLK_WIDTH (2U) 159 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 160 161 #define ADC_CFG1_MODE_MASK (0xCU) 162 #define ADC_CFG1_MODE_SHIFT (2U) 163 #define ADC_CFG1_MODE_WIDTH (2U) 164 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 165 166 #define ADC_CFG1_ADIV_MASK (0x60U) 167 #define ADC_CFG1_ADIV_SHIFT (5U) 168 #define ADC_CFG1_ADIV_WIDTH (2U) 169 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 170 171 #define ADC_CFG1_CLRLTRG_MASK (0x100U) 172 #define ADC_CFG1_CLRLTRG_SHIFT (8U) 173 #define ADC_CFG1_CLRLTRG_WIDTH (1U) 174 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_CLRLTRG_SHIFT)) & ADC_CFG1_CLRLTRG_MASK) 175 /*! @} */ 176 177 /*! @name CFG2 - ADC Configuration Register 2 */ 178 /*! @{ */ 179 180 #define ADC_CFG2_SMPLTS_MASK (0xFFU) 181 #define ADC_CFG2_SMPLTS_SHIFT (0U) 182 #define ADC_CFG2_SMPLTS_WIDTH (8U) 183 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) 184 /*! @} */ 185 186 /*! @name R - ADC Data Result Registers */ 187 /*! @{ */ 188 189 #define ADC_R_D_MASK (0xFFFU) 190 #define ADC_R_D_SHIFT (0U) 191 #define ADC_R_D_WIDTH (12U) 192 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 193 /*! @} */ 194 195 /*! @name CV - Compare Value Registers */ 196 /*! @{ */ 197 198 #define ADC_CV_CV_MASK (0xFFFFU) 199 #define ADC_CV_CV_SHIFT (0U) 200 #define ADC_CV_CV_WIDTH (16U) 201 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) 202 /*! @} */ 203 204 /*! @name SC2 - Status and Control Register 2 */ 205 /*! @{ */ 206 207 #define ADC_SC2_REFSEL_MASK (0x3U) 208 #define ADC_SC2_REFSEL_SHIFT (0U) 209 #define ADC_SC2_REFSEL_WIDTH (2U) 210 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 211 212 #define ADC_SC2_DMAEN_MASK (0x4U) 213 #define ADC_SC2_DMAEN_SHIFT (2U) 214 #define ADC_SC2_DMAEN_WIDTH (1U) 215 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 216 217 #define ADC_SC2_ACREN_MASK (0x8U) 218 #define ADC_SC2_ACREN_SHIFT (3U) 219 #define ADC_SC2_ACREN_WIDTH (1U) 220 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 221 222 #define ADC_SC2_ACFGT_MASK (0x10U) 223 #define ADC_SC2_ACFGT_SHIFT (4U) 224 #define ADC_SC2_ACFGT_WIDTH (1U) 225 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 226 227 #define ADC_SC2_ACFE_MASK (0x20U) 228 #define ADC_SC2_ACFE_SHIFT (5U) 229 #define ADC_SC2_ACFE_WIDTH (1U) 230 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 231 232 #define ADC_SC2_ADTRG_MASK (0x40U) 233 #define ADC_SC2_ADTRG_SHIFT (6U) 234 #define ADC_SC2_ADTRG_WIDTH (1U) 235 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 236 237 #define ADC_SC2_ADACT_MASK (0x80U) 238 #define ADC_SC2_ADACT_SHIFT (7U) 239 #define ADC_SC2_ADACT_WIDTH (1U) 240 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 241 242 #define ADC_SC2_TRGPRNUM_MASK (0x6000U) 243 #define ADC_SC2_TRGPRNUM_SHIFT (13U) 244 #define ADC_SC2_TRGPRNUM_WIDTH (2U) 245 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGPRNUM_SHIFT)) & ADC_SC2_TRGPRNUM_MASK) 246 247 #define ADC_SC2_TRGSTLAT_MASK (0xF0000U) 248 #define ADC_SC2_TRGSTLAT_SHIFT (16U) 249 #define ADC_SC2_TRGSTLAT_WIDTH (4U) 250 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTLAT_SHIFT)) & ADC_SC2_TRGSTLAT_MASK) 251 252 #define ADC_SC2_TRGSTERR_MASK (0xF000000U) 253 #define ADC_SC2_TRGSTERR_SHIFT (24U) 254 #define ADC_SC2_TRGSTERR_WIDTH (4U) 255 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTERR_SHIFT)) & ADC_SC2_TRGSTERR_MASK) 256 /*! @} */ 257 258 /*! @name SC3 - Status and Control Register 3 */ 259 /*! @{ */ 260 261 #define ADC_SC3_AVGS_MASK (0x3U) 262 #define ADC_SC3_AVGS_SHIFT (0U) 263 #define ADC_SC3_AVGS_WIDTH (2U) 264 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 265 266 #define ADC_SC3_AVGE_MASK (0x4U) 267 #define ADC_SC3_AVGE_SHIFT (2U) 268 #define ADC_SC3_AVGE_WIDTH (1U) 269 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 270 271 #define ADC_SC3_ADCO_MASK (0x8U) 272 #define ADC_SC3_ADCO_SHIFT (3U) 273 #define ADC_SC3_ADCO_WIDTH (1U) 274 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 275 276 #define ADC_SC3_CAL_MASK (0x80U) 277 #define ADC_SC3_CAL_SHIFT (7U) 278 #define ADC_SC3_CAL_WIDTH (1U) 279 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 280 /*! @} */ 281 282 /*! @name BASE_OFS - BASE Offset Register */ 283 /*! @{ */ 284 285 #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) 286 #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) 287 #define ADC_BASE_OFS_BA_OFS_WIDTH (8U) 288 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) 289 /*! @} */ 290 291 /*! @name OFS - ADC Offset Correction Register */ 292 /*! @{ */ 293 294 #define ADC_OFS_OFS_MASK (0xFFFFU) 295 #define ADC_OFS_OFS_SHIFT (0U) 296 #define ADC_OFS_OFS_WIDTH (16U) 297 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 298 /*! @} */ 299 300 /*! @name USR_OFS - USER Offset Correction Register */ 301 /*! @{ */ 302 303 #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) 304 #define ADC_USR_OFS_USR_OFS_SHIFT (0U) 305 #define ADC_USR_OFS_USR_OFS_WIDTH (8U) 306 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) 307 /*! @} */ 308 309 /*! @name XOFS - ADC X Offset Correction Register */ 310 /*! @{ */ 311 312 #define ADC_XOFS_XOFS_MASK (0x3FU) 313 #define ADC_XOFS_XOFS_SHIFT (0U) 314 #define ADC_XOFS_XOFS_WIDTH (6U) 315 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) 316 /*! @} */ 317 318 /*! @name YOFS - ADC Y Offset Correction Register */ 319 /*! @{ */ 320 321 #define ADC_YOFS_YOFS_MASK (0xFFU) 322 #define ADC_YOFS_YOFS_SHIFT (0U) 323 #define ADC_YOFS_YOFS_WIDTH (8U) 324 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) 325 /*! @} */ 326 327 /*! @name G - ADC Gain Register */ 328 /*! @{ */ 329 330 #define ADC_G_G_MASK (0x7FFU) 331 #define ADC_G_G_SHIFT (0U) 332 #define ADC_G_G_WIDTH (11U) 333 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) 334 /*! @} */ 335 336 /*! @name UG - ADC User Gain Register */ 337 /*! @{ */ 338 339 #define ADC_UG_UG_MASK (0x3FFU) 340 #define ADC_UG_UG_SHIFT (0U) 341 #define ADC_UG_UG_WIDTH (10U) 342 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) 343 /*! @} */ 344 345 /*! @name CLPS - ADC General Calibration Value Register S */ 346 /*! @{ */ 347 348 #define ADC_CLPS_CLPS_MASK (0x7FU) 349 #define ADC_CLPS_CLPS_SHIFT (0U) 350 #define ADC_CLPS_CLPS_WIDTH (7U) 351 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 352 /*! @} */ 353 354 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ 355 /*! @{ */ 356 357 #define ADC_CLP3_CLP3_MASK (0x3FFU) 358 #define ADC_CLP3_CLP3_SHIFT (0U) 359 #define ADC_CLP3_CLP3_WIDTH (10U) 360 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 361 /*! @} */ 362 363 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ 364 /*! @{ */ 365 366 #define ADC_CLP2_CLP2_MASK (0x3FFU) 367 #define ADC_CLP2_CLP2_SHIFT (0U) 368 #define ADC_CLP2_CLP2_WIDTH (10U) 369 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 370 /*! @} */ 371 372 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ 373 /*! @{ */ 374 375 #define ADC_CLP1_CLP1_MASK (0x1FFU) 376 #define ADC_CLP1_CLP1_SHIFT (0U) 377 #define ADC_CLP1_CLP1_WIDTH (9U) 378 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 379 /*! @} */ 380 381 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ 382 /*! @{ */ 383 384 #define ADC_CLP0_CLP0_MASK (0xFFU) 385 #define ADC_CLP0_CLP0_SHIFT (0U) 386 #define ADC_CLP0_CLP0_WIDTH (8U) 387 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 388 /*! @} */ 389 390 /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ 391 /*! @{ */ 392 393 #define ADC_CLPX_CLPX_MASK (0x7FU) 394 #define ADC_CLPX_CLPX_SHIFT (0U) 395 #define ADC_CLPX_CLPX_WIDTH (7U) 396 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) 397 /*! @} */ 398 399 /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ 400 /*! @{ */ 401 402 #define ADC_CLP9_CLP9_MASK (0x7FU) 403 #define ADC_CLP9_CLP9_SHIFT (0U) 404 #define ADC_CLP9_CLP9_WIDTH (7U) 405 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) 406 /*! @} */ 407 408 /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ 409 /*! @{ */ 410 411 #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) 412 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) 413 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH (4U) 414 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) 415 /*! @} */ 416 417 /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ 418 /*! @{ */ 419 420 #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) 421 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) 422 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH (4U) 423 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) 424 /*! @} */ 425 426 /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ 427 /*! @{ */ 428 429 #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) 430 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) 431 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH (4U) 432 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) 433 /*! @} */ 434 435 /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ 436 /*! @{ */ 437 438 #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) 439 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) 440 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH (4U) 441 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) 442 /*! @} */ 443 444 /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ 445 /*! @{ */ 446 447 #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) 448 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) 449 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH (4U) 450 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) 451 /*! @} */ 452 453 /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ 454 /*! @{ */ 455 456 #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) 457 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) 458 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH (12U) 459 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) 460 /*! @} */ 461 462 /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ 463 /*! @{ */ 464 465 #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) 466 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) 467 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH (12U) 468 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) 469 /*! @} */ 470 471 /*! 472 * @} 473 */ /* end of group ADC_Register_Masks */ 474 475 /*! 476 * @} 477 */ /* end of group ADC_Peripheral_Access_Layer */ 478 479 #endif /* #if !defined(S32K144_ADC_H_) */ 480
