1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144W_RCM.h 10 * @version 1.4 11 * @date 2022-02-09 12 * @brief Peripheral Access Layer for S32K144W_RCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144W_RCM_H_) /* Check if memory map has not been already included */ 58 #define S32K144W_RCM_H_ 59 60 #include "S32K144W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RCM - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x8 */ 76 __IO uint32_t RPC; /**< Reset Pin Control register, offset: 0xC */ 77 uint8_t RESERVED_0[8]; 78 __IO uint32_t SSRS; /**< Sticky System Reset Status Register, offset: 0x18 */ 79 __IO uint32_t SRIE; /**< System Reset Interrupt Enable Register, offset: 0x1C */ 80 } RCM_Type, *RCM_MemMapPtr; 81 82 /** Number of instances of the RCM module. */ 83 #define RCM_INSTANCE_COUNT (1u) 84 85 /* RCM - Peripheral instance base addresses */ 86 /** Peripheral RCM base address */ 87 #define IP_RCM_BASE (0x4007F000u) 88 /** Peripheral RCM base pointer */ 89 #define IP_RCM ((RCM_Type *)IP_RCM_BASE) 90 /** Array initializer of RCM peripheral base addresses */ 91 #define IP_RCM_BASE_ADDRS { IP_RCM_BASE } 92 /** Array initializer of RCM peripheral base pointers */ 93 #define IP_RCM_BASE_PTRS { IP_RCM } 94 95 /* ---------------------------------------------------------------------------- 96 -- RCM Register Masks 97 ---------------------------------------------------------------------------- */ 98 99 /*! 100 * @addtogroup RCM_Register_Masks RCM Register Masks 101 * @{ 102 */ 103 104 /*! @name VERID - Version ID Register */ 105 /*! @{ */ 106 107 #define RCM_VERID_FEATURE_MASK (0xFFFFU) 108 #define RCM_VERID_FEATURE_SHIFT (0U) 109 #define RCM_VERID_FEATURE_WIDTH (16U) 110 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_FEATURE_SHIFT)) & RCM_VERID_FEATURE_MASK) 111 112 #define RCM_VERID_MINOR_MASK (0xFF0000U) 113 #define RCM_VERID_MINOR_SHIFT (16U) 114 #define RCM_VERID_MINOR_WIDTH (8U) 115 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MINOR_SHIFT)) & RCM_VERID_MINOR_MASK) 116 117 #define RCM_VERID_MAJOR_MASK (0xFF000000U) 118 #define RCM_VERID_MAJOR_SHIFT (24U) 119 #define RCM_VERID_MAJOR_WIDTH (8U) 120 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MAJOR_SHIFT)) & RCM_VERID_MAJOR_MASK) 121 /*! @} */ 122 123 /*! @name PARAM - Parameter Register */ 124 /*! @{ */ 125 126 #define RCM_PARAM_EWAKEUP_MASK (0x1U) 127 #define RCM_PARAM_EWAKEUP_SHIFT (0U) 128 #define RCM_PARAM_EWAKEUP_WIDTH (1U) 129 #define RCM_PARAM_EWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EWAKEUP_SHIFT)) & RCM_PARAM_EWAKEUP_MASK) 130 131 #define RCM_PARAM_ELVD_MASK (0x2U) 132 #define RCM_PARAM_ELVD_SHIFT (1U) 133 #define RCM_PARAM_ELVD_WIDTH (1U) 134 #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELVD_SHIFT)) & RCM_PARAM_ELVD_MASK) 135 136 #define RCM_PARAM_ELOC_MASK (0x4U) 137 #define RCM_PARAM_ELOC_SHIFT (2U) 138 #define RCM_PARAM_ELOC_WIDTH (1U) 139 #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOC_SHIFT)) & RCM_PARAM_ELOC_MASK) 140 141 #define RCM_PARAM_ELOL_MASK (0x8U) 142 #define RCM_PARAM_ELOL_SHIFT (3U) 143 #define RCM_PARAM_ELOL_WIDTH (1U) 144 #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOL_SHIFT)) & RCM_PARAM_ELOL_MASK) 145 146 #define RCM_PARAM_ECMU_LOC_MASK (0x10U) 147 #define RCM_PARAM_ECMU_LOC_SHIFT (4U) 148 #define RCM_PARAM_ECMU_LOC_WIDTH (1U) 149 #define RCM_PARAM_ECMU_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ECMU_LOC_SHIFT)) & RCM_PARAM_ECMU_LOC_MASK) 150 151 #define RCM_PARAM_EWDOG_MASK (0x20U) 152 #define RCM_PARAM_EWDOG_SHIFT (5U) 153 #define RCM_PARAM_EWDOG_WIDTH (1U) 154 #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EWDOG_SHIFT)) & RCM_PARAM_EWDOG_MASK) 155 156 #define RCM_PARAM_EPIN_MASK (0x40U) 157 #define RCM_PARAM_EPIN_SHIFT (6U) 158 #define RCM_PARAM_EPIN_WIDTH (1U) 159 #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EPIN_SHIFT)) & RCM_PARAM_EPIN_MASK) 160 161 #define RCM_PARAM_EPOR_MASK (0x80U) 162 #define RCM_PARAM_EPOR_SHIFT (7U) 163 #define RCM_PARAM_EPOR_WIDTH (1U) 164 #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EPOR_SHIFT)) & RCM_PARAM_EPOR_MASK) 165 166 #define RCM_PARAM_EJTAG_MASK (0x100U) 167 #define RCM_PARAM_EJTAG_SHIFT (8U) 168 #define RCM_PARAM_EJTAG_WIDTH (1U) 169 #define RCM_PARAM_EJTAG(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EJTAG_SHIFT)) & RCM_PARAM_EJTAG_MASK) 170 171 #define RCM_PARAM_ELOCKUP_MASK (0x200U) 172 #define RCM_PARAM_ELOCKUP_SHIFT (9U) 173 #define RCM_PARAM_ELOCKUP_WIDTH (1U) 174 #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOCKUP_SHIFT)) & RCM_PARAM_ELOCKUP_MASK) 175 176 #define RCM_PARAM_ESW_MASK (0x400U) 177 #define RCM_PARAM_ESW_SHIFT (10U) 178 #define RCM_PARAM_ESW_WIDTH (1U) 179 #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ESW_SHIFT)) & RCM_PARAM_ESW_MASK) 180 181 #define RCM_PARAM_EMDM_AP_MASK (0x800U) 182 #define RCM_PARAM_EMDM_AP_SHIFT (11U) 183 #define RCM_PARAM_EMDM_AP_WIDTH (1U) 184 #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EMDM_AP_SHIFT)) & RCM_PARAM_EMDM_AP_MASK) 185 186 #define RCM_PARAM_ESACKERR_MASK (0x2000U) 187 #define RCM_PARAM_ESACKERR_SHIFT (13U) 188 #define RCM_PARAM_ESACKERR_WIDTH (1U) 189 #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ESACKERR_SHIFT)) & RCM_PARAM_ESACKERR_MASK) 190 191 #define RCM_PARAM_ETAMPER_MASK (0x8000U) 192 #define RCM_PARAM_ETAMPER_SHIFT (15U) 193 #define RCM_PARAM_ETAMPER_WIDTH (1U) 194 #define RCM_PARAM_ETAMPER(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ETAMPER_SHIFT)) & RCM_PARAM_ETAMPER_MASK) 195 196 #define RCM_PARAM_ECORE1_MASK (0x10000U) 197 #define RCM_PARAM_ECORE1_SHIFT (16U) 198 #define RCM_PARAM_ECORE1_WIDTH (1U) 199 #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ECORE1_SHIFT)) & RCM_PARAM_ECORE1_MASK) 200 /*! @} */ 201 202 /*! @name SRS - System Reset Status Register */ 203 /*! @{ */ 204 205 #define RCM_SRS_LVD_MASK (0x2U) 206 #define RCM_SRS_LVD_SHIFT (1U) 207 #define RCM_SRS_LVD_WIDTH (1U) 208 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LVD_SHIFT)) & RCM_SRS_LVD_MASK) 209 210 #define RCM_SRS_LOC_MASK (0x4U) 211 #define RCM_SRS_LOC_SHIFT (2U) 212 #define RCM_SRS_LOC_WIDTH (1U) 213 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOC_SHIFT)) & RCM_SRS_LOC_MASK) 214 215 #define RCM_SRS_LOL_MASK (0x8U) 216 #define RCM_SRS_LOL_SHIFT (3U) 217 #define RCM_SRS_LOL_WIDTH (1U) 218 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOL_SHIFT)) & RCM_SRS_LOL_MASK) 219 220 #define RCM_SRS_WDOG_MASK (0x20U) 221 #define RCM_SRS_WDOG_SHIFT (5U) 222 #define RCM_SRS_WDOG_WIDTH (1U) 223 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WDOG_SHIFT)) & RCM_SRS_WDOG_MASK) 224 225 #define RCM_SRS_PIN_MASK (0x40U) 226 #define RCM_SRS_PIN_SHIFT (6U) 227 #define RCM_SRS_PIN_WIDTH (1U) 228 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_PIN_SHIFT)) & RCM_SRS_PIN_MASK) 229 230 #define RCM_SRS_POR_MASK (0x80U) 231 #define RCM_SRS_POR_SHIFT (7U) 232 #define RCM_SRS_POR_WIDTH (1U) 233 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_POR_SHIFT)) & RCM_SRS_POR_MASK) 234 235 #define RCM_SRS_JTAG_MASK (0x100U) 236 #define RCM_SRS_JTAG_SHIFT (8U) 237 #define RCM_SRS_JTAG_WIDTH (1U) 238 #define RCM_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_JTAG_SHIFT)) & RCM_SRS_JTAG_MASK) 239 240 #define RCM_SRS_LOCKUP_MASK (0x200U) 241 #define RCM_SRS_LOCKUP_SHIFT (9U) 242 #define RCM_SRS_LOCKUP_WIDTH (1U) 243 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOCKUP_SHIFT)) & RCM_SRS_LOCKUP_MASK) 244 245 #define RCM_SRS_SW_MASK (0x400U) 246 #define RCM_SRS_SW_SHIFT (10U) 247 #define RCM_SRS_SW_WIDTH (1U) 248 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SW_SHIFT)) & RCM_SRS_SW_MASK) 249 250 #define RCM_SRS_MDM_AP_MASK (0x800U) 251 #define RCM_SRS_MDM_AP_SHIFT (11U) 252 #define RCM_SRS_MDM_AP_WIDTH (1U) 253 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_MDM_AP_SHIFT)) & RCM_SRS_MDM_AP_MASK) 254 255 #define RCM_SRS_SACKERR_MASK (0x2000U) 256 #define RCM_SRS_SACKERR_SHIFT (13U) 257 #define RCM_SRS_SACKERR_WIDTH (1U) 258 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SACKERR_SHIFT)) & RCM_SRS_SACKERR_MASK) 259 /*! @} */ 260 261 /*! @name RPC - Reset Pin Control register */ 262 /*! @{ */ 263 264 #define RCM_RPC_RSTFLTSRW_MASK (0x3U) 265 #define RCM_RPC_RSTFLTSRW_SHIFT (0U) 266 #define RCM_RPC_RSTFLTSRW_WIDTH (2U) 267 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSRW_SHIFT)) & RCM_RPC_RSTFLTSRW_MASK) 268 269 #define RCM_RPC_RSTFLTSS_MASK (0x4U) 270 #define RCM_RPC_RSTFLTSS_SHIFT (2U) 271 #define RCM_RPC_RSTFLTSS_WIDTH (1U) 272 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSS_SHIFT)) & RCM_RPC_RSTFLTSS_MASK) 273 274 #define RCM_RPC_RSTFLTSEL_MASK (0x1F00U) 275 #define RCM_RPC_RSTFLTSEL_SHIFT (8U) 276 #define RCM_RPC_RSTFLTSEL_WIDTH (5U) 277 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSEL_SHIFT)) & RCM_RPC_RSTFLTSEL_MASK) 278 /*! @} */ 279 280 /*! @name SSRS - Sticky System Reset Status Register */ 281 /*! @{ */ 282 283 #define RCM_SSRS_SLVD_MASK (0x2U) 284 #define RCM_SSRS_SLVD_SHIFT (1U) 285 #define RCM_SSRS_SLVD_WIDTH (1U) 286 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLVD_SHIFT)) & RCM_SSRS_SLVD_MASK) 287 288 #define RCM_SSRS_SLOC_MASK (0x4U) 289 #define RCM_SSRS_SLOC_SHIFT (2U) 290 #define RCM_SSRS_SLOC_WIDTH (1U) 291 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOC_SHIFT)) & RCM_SSRS_SLOC_MASK) 292 293 #define RCM_SSRS_SLOL_MASK (0x8U) 294 #define RCM_SSRS_SLOL_SHIFT (3U) 295 #define RCM_SSRS_SLOL_WIDTH (1U) 296 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOL_SHIFT)) & RCM_SSRS_SLOL_MASK) 297 298 #define RCM_SSRS_SWDOG_MASK (0x20U) 299 #define RCM_SSRS_SWDOG_SHIFT (5U) 300 #define RCM_SSRS_SWDOG_WIDTH (1U) 301 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWDOG_SHIFT)) & RCM_SSRS_SWDOG_MASK) 302 303 #define RCM_SSRS_SPIN_MASK (0x40U) 304 #define RCM_SSRS_SPIN_SHIFT (6U) 305 #define RCM_SSRS_SPIN_WIDTH (1U) 306 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPIN_SHIFT)) & RCM_SSRS_SPIN_MASK) 307 308 #define RCM_SSRS_SPOR_MASK (0x80U) 309 #define RCM_SSRS_SPOR_SHIFT (7U) 310 #define RCM_SSRS_SPOR_WIDTH (1U) 311 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPOR_SHIFT)) & RCM_SSRS_SPOR_MASK) 312 313 #define RCM_SSRS_SJTAG_MASK (0x100U) 314 #define RCM_SSRS_SJTAG_SHIFT (8U) 315 #define RCM_SSRS_SJTAG_WIDTH (1U) 316 #define RCM_SSRS_SJTAG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SJTAG_SHIFT)) & RCM_SSRS_SJTAG_MASK) 317 318 #define RCM_SSRS_SLOCKUP_MASK (0x200U) 319 #define RCM_SSRS_SLOCKUP_SHIFT (9U) 320 #define RCM_SSRS_SLOCKUP_WIDTH (1U) 321 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOCKUP_SHIFT)) & RCM_SSRS_SLOCKUP_MASK) 322 323 #define RCM_SSRS_SSW_MASK (0x400U) 324 #define RCM_SSRS_SSW_SHIFT (10U) 325 #define RCM_SSRS_SSW_WIDTH (1U) 326 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSW_SHIFT)) & RCM_SSRS_SSW_MASK) 327 328 #define RCM_SSRS_SMDM_AP_MASK (0x800U) 329 #define RCM_SSRS_SMDM_AP_SHIFT (11U) 330 #define RCM_SSRS_SMDM_AP_WIDTH (1U) 331 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SMDM_AP_SHIFT)) & RCM_SSRS_SMDM_AP_MASK) 332 333 #define RCM_SSRS_SSACKERR_MASK (0x2000U) 334 #define RCM_SSRS_SSACKERR_SHIFT (13U) 335 #define RCM_SSRS_SSACKERR_WIDTH (1U) 336 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSACKERR_SHIFT)) & RCM_SSRS_SSACKERR_MASK) 337 /*! @} */ 338 339 /*! @name SRIE - System Reset Interrupt Enable Register */ 340 /*! @{ */ 341 342 #define RCM_SRIE_DELAY_MASK (0x3U) 343 #define RCM_SRIE_DELAY_SHIFT (0U) 344 #define RCM_SRIE_DELAY_WIDTH (2U) 345 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_DELAY_SHIFT)) & RCM_SRIE_DELAY_MASK) 346 347 #define RCM_SRIE_LOC_MASK (0x4U) 348 #define RCM_SRIE_LOC_SHIFT (2U) 349 #define RCM_SRIE_LOC_WIDTH (1U) 350 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOC_SHIFT)) & RCM_SRIE_LOC_MASK) 351 352 #define RCM_SRIE_LOL_MASK (0x8U) 353 #define RCM_SRIE_LOL_SHIFT (3U) 354 #define RCM_SRIE_LOL_WIDTH (1U) 355 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOL_SHIFT)) & RCM_SRIE_LOL_MASK) 356 357 #define RCM_SRIE_WDOG_MASK (0x20U) 358 #define RCM_SRIE_WDOG_SHIFT (5U) 359 #define RCM_SRIE_WDOG_WIDTH (1U) 360 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_WDOG_SHIFT)) & RCM_SRIE_WDOG_MASK) 361 362 #define RCM_SRIE_PIN_MASK (0x40U) 363 #define RCM_SRIE_PIN_SHIFT (6U) 364 #define RCM_SRIE_PIN_WIDTH (1U) 365 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_PIN_SHIFT)) & RCM_SRIE_PIN_MASK) 366 367 #define RCM_SRIE_GIE_MASK (0x80U) 368 #define RCM_SRIE_GIE_SHIFT (7U) 369 #define RCM_SRIE_GIE_WIDTH (1U) 370 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_GIE_SHIFT)) & RCM_SRIE_GIE_MASK) 371 372 #define RCM_SRIE_JTAG_MASK (0x100U) 373 #define RCM_SRIE_JTAG_SHIFT (8U) 374 #define RCM_SRIE_JTAG_WIDTH (1U) 375 #define RCM_SRIE_JTAG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_JTAG_SHIFT)) & RCM_SRIE_JTAG_MASK) 376 377 #define RCM_SRIE_LOCKUP_MASK (0x200U) 378 #define RCM_SRIE_LOCKUP_SHIFT (9U) 379 #define RCM_SRIE_LOCKUP_WIDTH (1U) 380 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOCKUP_SHIFT)) & RCM_SRIE_LOCKUP_MASK) 381 382 #define RCM_SRIE_SW_MASK (0x400U) 383 #define RCM_SRIE_SW_SHIFT (10U) 384 #define RCM_SRIE_SW_WIDTH (1U) 385 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SW_SHIFT)) & RCM_SRIE_SW_MASK) 386 387 #define RCM_SRIE_MDM_AP_MASK (0x800U) 388 #define RCM_SRIE_MDM_AP_SHIFT (11U) 389 #define RCM_SRIE_MDM_AP_WIDTH (1U) 390 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_MDM_AP_SHIFT)) & RCM_SRIE_MDM_AP_MASK) 391 392 #define RCM_SRIE_SACKERR_MASK (0x2000U) 393 #define RCM_SRIE_SACKERR_SHIFT (13U) 394 #define RCM_SRIE_SACKERR_WIDTH (1U) 395 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SACKERR_SHIFT)) & RCM_SRIE_SACKERR_MASK) 396 /*! @} */ 397 398 /*! 399 * @} 400 */ /* end of group RCM_Register_Masks */ 401 402 /*! 403 * @} 404 */ /* end of group RCM_Peripheral_Access_Layer */ 405 406 #endif /* #if !defined(S32K144W_RCM_H_) */ 407
