1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142_LPIT.h 10 * @version 1.1 11 * @date 2022-02-01 12 * @brief Peripheral Access Layer for S32K142_LPIT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142_LPIT_H_) /* Check if memory map has not been already included */ 58 #define S32K142_LPIT_H_ 59 60 #include "S32K142_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPIT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPIT - Size of Registers Arrays */ 72 #define LPIT_TMR_COUNT 4u 73 74 /** LPIT - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 77 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 78 __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ 79 __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ 80 __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ 81 __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ 82 __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ 83 uint8_t RESERVED_0[4]; 84 struct { /* offset: 0x20, array step: 0x10 */ 85 __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ 86 __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ 87 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ 88 uint8_t RESERVED_0[4]; 89 } TMR[LPIT_TMR_COUNT]; 90 } LPIT_Type, *LPIT_MemMapPtr; 91 92 /** Number of instances of the LPIT module. */ 93 #define LPIT_INSTANCE_COUNT (1u) 94 95 /* LPIT - Peripheral instance base addresses */ 96 /** Peripheral LPIT0 base address */ 97 #define IP_LPIT0_BASE (0x40037000u) 98 /** Peripheral LPIT0 base pointer */ 99 #define IP_LPIT0 ((LPIT_Type *)IP_LPIT0_BASE) 100 /** Array initializer of LPIT peripheral base addresses */ 101 #define IP_LPIT_BASE_ADDRS { IP_LPIT0_BASE } 102 /** Array initializer of LPIT peripheral base pointers */ 103 #define IP_LPIT_BASE_PTRS { IP_LPIT0 } 104 105 /* ---------------------------------------------------------------------------- 106 -- LPIT Register Masks 107 ---------------------------------------------------------------------------- */ 108 109 /*! 110 * @addtogroup LPIT_Register_Masks LPIT Register Masks 111 * @{ 112 */ 113 114 /*! @name VERID - Version ID Register */ 115 /*! @{ */ 116 117 #define LPIT_VERID_FEATURE_MASK (0xFFFFU) 118 #define LPIT_VERID_FEATURE_SHIFT (0U) 119 #define LPIT_VERID_FEATURE_WIDTH (16U) 120 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) 121 122 #define LPIT_VERID_MINOR_MASK (0xFF0000U) 123 #define LPIT_VERID_MINOR_SHIFT (16U) 124 #define LPIT_VERID_MINOR_WIDTH (8U) 125 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) 126 127 #define LPIT_VERID_MAJOR_MASK (0xFF000000U) 128 #define LPIT_VERID_MAJOR_SHIFT (24U) 129 #define LPIT_VERID_MAJOR_WIDTH (8U) 130 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) 131 /*! @} */ 132 133 /*! @name PARAM - Parameter Register */ 134 /*! @{ */ 135 136 #define LPIT_PARAM_CHANNEL_MASK (0xFFU) 137 #define LPIT_PARAM_CHANNEL_SHIFT (0U) 138 #define LPIT_PARAM_CHANNEL_WIDTH (8U) 139 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) 140 141 #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) 142 #define LPIT_PARAM_EXT_TRIG_SHIFT (8U) 143 #define LPIT_PARAM_EXT_TRIG_WIDTH (8U) 144 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) 145 /*! @} */ 146 147 /*! @name MCR - Module Control Register */ 148 /*! @{ */ 149 150 #define LPIT_MCR_M_CEN_MASK (0x1U) 151 #define LPIT_MCR_M_CEN_SHIFT (0U) 152 #define LPIT_MCR_M_CEN_WIDTH (1U) 153 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) 154 155 #define LPIT_MCR_SW_RST_MASK (0x2U) 156 #define LPIT_MCR_SW_RST_SHIFT (1U) 157 #define LPIT_MCR_SW_RST_WIDTH (1U) 158 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) 159 160 #define LPIT_MCR_DOZE_EN_MASK (0x4U) 161 #define LPIT_MCR_DOZE_EN_SHIFT (2U) 162 #define LPIT_MCR_DOZE_EN_WIDTH (1U) 163 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) 164 165 #define LPIT_MCR_DBG_EN_MASK (0x8U) 166 #define LPIT_MCR_DBG_EN_SHIFT (3U) 167 #define LPIT_MCR_DBG_EN_WIDTH (1U) 168 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) 169 /*! @} */ 170 171 /*! @name MSR - Module Status Register */ 172 /*! @{ */ 173 174 #define LPIT_MSR_TIF0_MASK (0x1U) 175 #define LPIT_MSR_TIF0_SHIFT (0U) 176 #define LPIT_MSR_TIF0_WIDTH (1U) 177 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) 178 179 #define LPIT_MSR_TIF1_MASK (0x2U) 180 #define LPIT_MSR_TIF1_SHIFT (1U) 181 #define LPIT_MSR_TIF1_WIDTH (1U) 182 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) 183 184 #define LPIT_MSR_TIF2_MASK (0x4U) 185 #define LPIT_MSR_TIF2_SHIFT (2U) 186 #define LPIT_MSR_TIF2_WIDTH (1U) 187 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) 188 189 #define LPIT_MSR_TIF3_MASK (0x8U) 190 #define LPIT_MSR_TIF3_SHIFT (3U) 191 #define LPIT_MSR_TIF3_WIDTH (1U) 192 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) 193 /*! @} */ 194 195 /*! @name MIER - Module Interrupt Enable Register */ 196 /*! @{ */ 197 198 #define LPIT_MIER_TIE0_MASK (0x1U) 199 #define LPIT_MIER_TIE0_SHIFT (0U) 200 #define LPIT_MIER_TIE0_WIDTH (1U) 201 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) 202 203 #define LPIT_MIER_TIE1_MASK (0x2U) 204 #define LPIT_MIER_TIE1_SHIFT (1U) 205 #define LPIT_MIER_TIE1_WIDTH (1U) 206 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) 207 208 #define LPIT_MIER_TIE2_MASK (0x4U) 209 #define LPIT_MIER_TIE2_SHIFT (2U) 210 #define LPIT_MIER_TIE2_WIDTH (1U) 211 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) 212 213 #define LPIT_MIER_TIE3_MASK (0x8U) 214 #define LPIT_MIER_TIE3_SHIFT (3U) 215 #define LPIT_MIER_TIE3_WIDTH (1U) 216 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) 217 /*! @} */ 218 219 /*! @name SETTEN - Set Timer Enable Register */ 220 /*! @{ */ 221 222 #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) 223 #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) 224 #define LPIT_SETTEN_SET_T_EN_0_WIDTH (1U) 225 #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) 226 227 #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) 228 #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) 229 #define LPIT_SETTEN_SET_T_EN_1_WIDTH (1U) 230 #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) 231 232 #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) 233 #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) 234 #define LPIT_SETTEN_SET_T_EN_2_WIDTH (1U) 235 #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) 236 237 #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) 238 #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) 239 #define LPIT_SETTEN_SET_T_EN_3_WIDTH (1U) 240 #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) 241 /*! @} */ 242 243 /*! @name CLRTEN - Clear Timer Enable Register */ 244 /*! @{ */ 245 246 #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) 247 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) 248 #define LPIT_CLRTEN_CLR_T_EN_0_WIDTH (1U) 249 #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) 250 251 #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) 252 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) 253 #define LPIT_CLRTEN_CLR_T_EN_1_WIDTH (1U) 254 #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) 255 256 #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) 257 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) 258 #define LPIT_CLRTEN_CLR_T_EN_2_WIDTH (1U) 259 #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) 260 261 #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) 262 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) 263 #define LPIT_CLRTEN_CLR_T_EN_3_WIDTH (1U) 264 #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) 265 /*! @} */ 266 267 /*! @name TMR_TVAL - Timer Value Register */ 268 /*! @{ */ 269 270 #define LPIT_TMR_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) 271 #define LPIT_TMR_TVAL_TMR_VAL_SHIFT (0U) 272 #define LPIT_TMR_TVAL_TMR_VAL_WIDTH (32U) 273 #define LPIT_TMR_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TVAL_TMR_VAL_SHIFT)) & LPIT_TMR_TVAL_TMR_VAL_MASK) 274 /*! @} */ 275 276 /*! @name TMR_CVAL - Current Timer Value */ 277 /*! @{ */ 278 279 #define LPIT_TMR_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) 280 #define LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT (0U) 281 #define LPIT_TMR_CVAL_TMR_CUR_VAL_WIDTH (32U) 282 #define LPIT_TMR_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_TMR_CVAL_TMR_CUR_VAL_MASK) 283 /*! @} */ 284 285 /*! @name TMR_TCTRL - Timer Control Register */ 286 /*! @{ */ 287 288 #define LPIT_TMR_TCTRL_T_EN_MASK (0x1U) 289 #define LPIT_TMR_TCTRL_T_EN_SHIFT (0U) 290 #define LPIT_TMR_TCTRL_T_EN_WIDTH (1U) 291 #define LPIT_TMR_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_T_EN_SHIFT)) & LPIT_TMR_TCTRL_T_EN_MASK) 292 293 #define LPIT_TMR_TCTRL_CHAIN_MASK (0x2U) 294 #define LPIT_TMR_TCTRL_CHAIN_SHIFT (1U) 295 #define LPIT_TMR_TCTRL_CHAIN_WIDTH (1U) 296 #define LPIT_TMR_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_CHAIN_SHIFT)) & LPIT_TMR_TCTRL_CHAIN_MASK) 297 298 #define LPIT_TMR_TCTRL_MODE_MASK (0xCU) 299 #define LPIT_TMR_TCTRL_MODE_SHIFT (2U) 300 #define LPIT_TMR_TCTRL_MODE_WIDTH (2U) 301 #define LPIT_TMR_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_MODE_SHIFT)) & LPIT_TMR_TCTRL_MODE_MASK) 302 303 #define LPIT_TMR_TCTRL_TSOT_MASK (0x10000U) 304 #define LPIT_TMR_TCTRL_TSOT_SHIFT (16U) 305 #define LPIT_TMR_TCTRL_TSOT_WIDTH (1U) 306 #define LPIT_TMR_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_TSOT_SHIFT)) & LPIT_TMR_TCTRL_TSOT_MASK) 307 308 #define LPIT_TMR_TCTRL_TSOI_MASK (0x20000U) 309 #define LPIT_TMR_TCTRL_TSOI_SHIFT (17U) 310 #define LPIT_TMR_TCTRL_TSOI_WIDTH (1U) 311 #define LPIT_TMR_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_TSOI_SHIFT)) & LPIT_TMR_TCTRL_TSOI_MASK) 312 313 #define LPIT_TMR_TCTRL_TROT_MASK (0x40000U) 314 #define LPIT_TMR_TCTRL_TROT_SHIFT (18U) 315 #define LPIT_TMR_TCTRL_TROT_WIDTH (1U) 316 #define LPIT_TMR_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_TROT_SHIFT)) & LPIT_TMR_TCTRL_TROT_MASK) 317 318 #define LPIT_TMR_TCTRL_TRG_SRC_MASK (0x800000U) 319 #define LPIT_TMR_TCTRL_TRG_SRC_SHIFT (23U) 320 #define LPIT_TMR_TCTRL_TRG_SRC_WIDTH (1U) 321 #define LPIT_TMR_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_TRG_SRC_SHIFT)) & LPIT_TMR_TCTRL_TRG_SRC_MASK) 322 323 #define LPIT_TMR_TCTRL_TRG_SEL_MASK (0xF000000U) 324 #define LPIT_TMR_TCTRL_TRG_SEL_SHIFT (24U) 325 #define LPIT_TMR_TCTRL_TRG_SEL_WIDTH (4U) 326 #define LPIT_TMR_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TMR_TCTRL_TRG_SEL_SHIFT)) & LPIT_TMR_TCTRL_TRG_SEL_MASK) 327 /*! @} */ 328 329 /*! 330 * @} 331 */ /* end of group LPIT_Register_Masks */ 332 333 /*! 334 * @} 335 */ /* end of group LPIT_Peripheral_Access_Layer */ 336 337 #endif /* #if !defined(S32K142_LPIT_H_) */ 338
