1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_FTFM.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_FTFM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_FTFM_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_FTFM_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FTFM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FTFM_Peripheral_Access_Layer FTFM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FTFM - Size of Registers Arrays */ 72 #define FTFM_FCCOB_COUNT 12u 73 #define FTFM_FPROT_COUNT 4u 74 75 /** FTFM - Register Layout Typedef */ 76 typedef struct { 77 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 78 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 79 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 80 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 81 __IO uint8_t FCCOB[FTFM_FCCOB_COUNT]; /**< Flash Common Command Object Registers, array offset: 0x4, array step: 0x1 */ 82 __IO uint8_t FPROT[FTFM_FPROT_COUNT]; /**< Program Flash Protection Registers, array offset: 0x10, array step: 0x1 */ 83 uint8_t RESERVED_0[2]; 84 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ 85 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ 86 uint8_t RESERVED_1[20]; 87 __I uint8_t FCSESTAT1; /**< Flash CSEc Status Register 1, offset: 0x2C */ 88 __I uint8_t FCSESTAT0; /**< Flash CSEc Status Register 0, offset: 0x2D */ 89 __IO uint8_t FERSTAT; /**< Flash Error Status Register, offset: 0x2E */ 90 __IO uint8_t FERCNFG; /**< Flash Error Configuration Register, offset: 0x2F */ 91 } FTFM_Type, *FTFM_MemMapPtr; 92 93 /** Number of instances of the FTFM module. */ 94 #define FTFM_INSTANCE_COUNT (1u) 95 96 /* FTFM - Peripheral instance base addresses */ 97 /** Peripheral FTFM base address */ 98 #define IP_FTFM_BASE (0x40020000u) 99 /** Peripheral FTFM base pointer */ 100 #define IP_FTFM ((FTFM_Type *)IP_FTFM_BASE) 101 /** Array initializer of FTFM peripheral base addresses */ 102 #define IP_FTFM_BASE_ADDRS { IP_FTFM_BASE } 103 /** Array initializer of FTFM peripheral base pointers */ 104 #define IP_FTFM_BASE_PTRS { IP_FTFM } 105 106 /* ---------------------------------------------------------------------------- 107 -- FTFM Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup FTFM_Register_Masks FTFM Register Masks 112 * @{ 113 */ 114 115 /*! @name FSTAT - Flash Status Register */ 116 /*! @{ */ 117 118 #define FTFM_FSTAT_MGSTAT0_MASK (0x1U) 119 #define FTFM_FSTAT_MGSTAT0_SHIFT (0U) 120 #define FTFM_FSTAT_MGSTAT0_WIDTH (1U) 121 #define FTFM_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_MGSTAT0_SHIFT)) & FTFM_FSTAT_MGSTAT0_MASK) 122 123 #define FTFM_FSTAT_MGSTAT1_MASK (0x2U) 124 #define FTFM_FSTAT_MGSTAT1_SHIFT (1U) 125 #define FTFM_FSTAT_MGSTAT1_WIDTH (1U) 126 #define FTFM_FSTAT_MGSTAT1(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_MGSTAT1_SHIFT)) & FTFM_FSTAT_MGSTAT1_MASK) 127 128 #define FTFM_FSTAT_MGSTAT2_MASK (0x4U) 129 #define FTFM_FSTAT_MGSTAT2_SHIFT (2U) 130 #define FTFM_FSTAT_MGSTAT2_WIDTH (1U) 131 #define FTFM_FSTAT_MGSTAT2(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_MGSTAT2_SHIFT)) & FTFM_FSTAT_MGSTAT2_MASK) 132 133 #define FTFM_FSTAT_MGSTAT3_MASK (0x8U) 134 #define FTFM_FSTAT_MGSTAT3_SHIFT (3U) 135 #define FTFM_FSTAT_MGSTAT3_WIDTH (1U) 136 #define FTFM_FSTAT_MGSTAT3(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_MGSTAT3_SHIFT)) & FTFM_FSTAT_MGSTAT3_MASK) 137 138 #define FTFM_FSTAT_FPVIOL_MASK (0x10U) 139 #define FTFM_FSTAT_FPVIOL_SHIFT (4U) 140 #define FTFM_FSTAT_FPVIOL_WIDTH (1U) 141 #define FTFM_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_FPVIOL_SHIFT)) & FTFM_FSTAT_FPVIOL_MASK) 142 143 #define FTFM_FSTAT_ACCERR_MASK (0x20U) 144 #define FTFM_FSTAT_ACCERR_SHIFT (5U) 145 #define FTFM_FSTAT_ACCERR_WIDTH (1U) 146 #define FTFM_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_ACCERR_SHIFT)) & FTFM_FSTAT_ACCERR_MASK) 147 148 #define FTFM_FSTAT_RDCOLERR_MASK (0x40U) 149 #define FTFM_FSTAT_RDCOLERR_SHIFT (6U) 150 #define FTFM_FSTAT_RDCOLERR_WIDTH (1U) 151 #define FTFM_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_RDCOLERR_SHIFT)) & FTFM_FSTAT_RDCOLERR_MASK) 152 153 #define FTFM_FSTAT_CCIF_MASK (0x80U) 154 #define FTFM_FSTAT_CCIF_SHIFT (7U) 155 #define FTFM_FSTAT_CCIF_WIDTH (1U) 156 #define FTFM_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSTAT_CCIF_SHIFT)) & FTFM_FSTAT_CCIF_MASK) 157 /*! @} */ 158 159 /*! @name FCNFG - Flash Configuration Register */ 160 /*! @{ */ 161 162 #define FTFM_FCNFG_EEERDY_MASK (0x1U) 163 #define FTFM_FCNFG_EEERDY_SHIFT (0U) 164 #define FTFM_FCNFG_EEERDY_WIDTH (1U) 165 #define FTFM_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCNFG_EEERDY_SHIFT)) & FTFM_FCNFG_EEERDY_MASK) 166 167 #define FTFM_FCNFG_RAMRDY_MASK (0x2U) 168 #define FTFM_FCNFG_RAMRDY_SHIFT (1U) 169 #define FTFM_FCNFG_RAMRDY_WIDTH (1U) 170 #define FTFM_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCNFG_RAMRDY_SHIFT)) & FTFM_FCNFG_RAMRDY_MASK) 171 172 #define FTFM_FCNFG_ERSSUSP_MASK (0x10U) 173 #define FTFM_FCNFG_ERSSUSP_SHIFT (4U) 174 #define FTFM_FCNFG_ERSSUSP_WIDTH (1U) 175 #define FTFM_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCNFG_ERSSUSP_SHIFT)) & FTFM_FCNFG_ERSSUSP_MASK) 176 177 #define FTFM_FCNFG_ERSAREQ_MASK (0x20U) 178 #define FTFM_FCNFG_ERSAREQ_SHIFT (5U) 179 #define FTFM_FCNFG_ERSAREQ_WIDTH (1U) 180 #define FTFM_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCNFG_ERSAREQ_SHIFT)) & FTFM_FCNFG_ERSAREQ_MASK) 181 182 #define FTFM_FCNFG_RDCOLLIE_MASK (0x40U) 183 #define FTFM_FCNFG_RDCOLLIE_SHIFT (6U) 184 #define FTFM_FCNFG_RDCOLLIE_WIDTH (1U) 185 #define FTFM_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCNFG_RDCOLLIE_SHIFT)) & FTFM_FCNFG_RDCOLLIE_MASK) 186 187 #define FTFM_FCNFG_CCIE_MASK (0x80U) 188 #define FTFM_FCNFG_CCIE_SHIFT (7U) 189 #define FTFM_FCNFG_CCIE_WIDTH (1U) 190 #define FTFM_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCNFG_CCIE_SHIFT)) & FTFM_FCNFG_CCIE_MASK) 191 /*! @} */ 192 193 /*! @name FSEC - Flash Security Register */ 194 /*! @{ */ 195 196 #define FTFM_FSEC_SEC_MASK (0x3U) 197 #define FTFM_FSEC_SEC_SHIFT (0U) 198 #define FTFM_FSEC_SEC_WIDTH (2U) 199 #define FTFM_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSEC_SEC_SHIFT)) & FTFM_FSEC_SEC_MASK) 200 201 #define FTFM_FSEC_FSLACC_MASK (0xCU) 202 #define FTFM_FSEC_FSLACC_SHIFT (2U) 203 #define FTFM_FSEC_FSLACC_WIDTH (2U) 204 #define FTFM_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSEC_FSLACC_SHIFT)) & FTFM_FSEC_FSLACC_MASK) 205 206 #define FTFM_FSEC_MEEN_MASK (0x30U) 207 #define FTFM_FSEC_MEEN_SHIFT (4U) 208 #define FTFM_FSEC_MEEN_WIDTH (2U) 209 #define FTFM_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSEC_MEEN_SHIFT)) & FTFM_FSEC_MEEN_MASK) 210 211 #define FTFM_FSEC_KEYEN_MASK (0xC0U) 212 #define FTFM_FSEC_KEYEN_SHIFT (6U) 213 #define FTFM_FSEC_KEYEN_WIDTH (2U) 214 #define FTFM_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FSEC_KEYEN_SHIFT)) & FTFM_FSEC_KEYEN_MASK) 215 /*! @} */ 216 217 /*! @name FOPT - Flash Option Register */ 218 /*! @{ */ 219 220 #define FTFM_FOPT_OPT_MASK (0xFFU) 221 #define FTFM_FOPT_OPT_SHIFT (0U) 222 #define FTFM_FOPT_OPT_WIDTH (8U) 223 #define FTFM_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FOPT_OPT_SHIFT)) & FTFM_FOPT_OPT_MASK) 224 /*! @} */ 225 226 /*! @name FCCOB - Flash Common Command Object Registers */ 227 /*! @{ */ 228 229 #define FTFM_FCCOB_CCOBn_MASK (0xFFU) 230 #define FTFM_FCCOB_CCOBn_SHIFT (0U) 231 #define FTFM_FCCOB_CCOBn_WIDTH (8U) 232 #define FTFM_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCCOB_CCOBn_SHIFT)) & FTFM_FCCOB_CCOBn_MASK) 233 /*! @} */ 234 235 /*! @name FPROT - Program Flash Protection Registers */ 236 /*! @{ */ 237 238 #define FTFM_FPROT_PROT_MASK (0xFFU) 239 #define FTFM_FPROT_PROT_SHIFT (0U) 240 #define FTFM_FPROT_PROT_WIDTH (8U) 241 #define FTFM_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FPROT_PROT_SHIFT)) & FTFM_FPROT_PROT_MASK) 242 /*! @} */ 243 244 /*! @name FEPROT - EEPROM Protection Register */ 245 /*! @{ */ 246 247 #define FTFM_FEPROT_EPROT_MASK (0xFFU) 248 #define FTFM_FEPROT_EPROT_SHIFT (0U) 249 #define FTFM_FEPROT_EPROT_WIDTH (8U) 250 #define FTFM_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FEPROT_EPROT_SHIFT)) & FTFM_FEPROT_EPROT_MASK) 251 /*! @} */ 252 253 /*! @name FDPROT - Data Flash Protection Register */ 254 /*! @{ */ 255 256 #define FTFM_FDPROT_DPROT_MASK (0xFFU) 257 #define FTFM_FDPROT_DPROT_SHIFT (0U) 258 #define FTFM_FDPROT_DPROT_WIDTH (8U) 259 #define FTFM_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FDPROT_DPROT_SHIFT)) & FTFM_FDPROT_DPROT_MASK) 260 /*! @} */ 261 262 /*! @name FCSESTAT1 - Flash CSEc Status Register 1 */ 263 /*! @{ */ 264 265 #define FTFM_FCSESTAT1_BSY_MASK (0x1U) 266 #define FTFM_FCSESTAT1_BSY_SHIFT (0U) 267 #define FTFM_FCSESTAT1_BSY_WIDTH (1U) 268 #define FTFM_FCSESTAT1_BSY(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_BSY_SHIFT)) & FTFM_FCSESTAT1_BSY_MASK) 269 270 #define FTFM_FCSESTAT1_SB_MASK (0x2U) 271 #define FTFM_FCSESTAT1_SB_SHIFT (1U) 272 #define FTFM_FCSESTAT1_SB_WIDTH (1U) 273 #define FTFM_FCSESTAT1_SB(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_SB_SHIFT)) & FTFM_FCSESTAT1_SB_MASK) 274 275 #define FTFM_FCSESTAT1_BIN_MASK (0x4U) 276 #define FTFM_FCSESTAT1_BIN_SHIFT (2U) 277 #define FTFM_FCSESTAT1_BIN_WIDTH (1U) 278 #define FTFM_FCSESTAT1_BIN(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_BIN_SHIFT)) & FTFM_FCSESTAT1_BIN_MASK) 279 280 #define FTFM_FCSESTAT1_BFN_MASK (0x8U) 281 #define FTFM_FCSESTAT1_BFN_SHIFT (3U) 282 #define FTFM_FCSESTAT1_BFN_WIDTH (1U) 283 #define FTFM_FCSESTAT1_BFN(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_BFN_SHIFT)) & FTFM_FCSESTAT1_BFN_MASK) 284 285 #define FTFM_FCSESTAT1_BOK_MASK (0x10U) 286 #define FTFM_FCSESTAT1_BOK_SHIFT (4U) 287 #define FTFM_FCSESTAT1_BOK_WIDTH (1U) 288 #define FTFM_FCSESTAT1_BOK(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_BOK_SHIFT)) & FTFM_FCSESTAT1_BOK_MASK) 289 290 #define FTFM_FCSESTAT1_RIN_MASK (0x20U) 291 #define FTFM_FCSESTAT1_RIN_SHIFT (5U) 292 #define FTFM_FCSESTAT1_RIN_WIDTH (1U) 293 #define FTFM_FCSESTAT1_RIN(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_RIN_SHIFT)) & FTFM_FCSESTAT1_RIN_MASK) 294 295 #define FTFM_FCSESTAT1_EDB_MASK (0x40U) 296 #define FTFM_FCSESTAT1_EDB_SHIFT (6U) 297 #define FTFM_FCSESTAT1_EDB_WIDTH (1U) 298 #define FTFM_FCSESTAT1_EDB(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_EDB_SHIFT)) & FTFM_FCSESTAT1_EDB_MASK) 299 300 #define FTFM_FCSESTAT1_IDB_MASK (0x80U) 301 #define FTFM_FCSESTAT1_IDB_SHIFT (7U) 302 #define FTFM_FCSESTAT1_IDB_WIDTH (1U) 303 #define FTFM_FCSESTAT1_IDB(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT1_IDB_SHIFT)) & FTFM_FCSESTAT1_IDB_MASK) 304 /*! @} */ 305 306 /*! @name FCSESTAT0 - Flash CSEc Status Register 0 */ 307 /*! @{ */ 308 309 #define FTFM_FCSESTAT0_CMDTYPE_MASK (0x2U) 310 #define FTFM_FCSESTAT0_CMDTYPE_SHIFT (1U) 311 #define FTFM_FCSESTAT0_CMDTYPE_WIDTH (1U) 312 #define FTFM_FCSESTAT0_CMDTYPE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT0_CMDTYPE_SHIFT)) & FTFM_FCSESTAT0_CMDTYPE_MASK) 313 314 #define FTFM_FCSESTAT0_MEMERR_MASK (0x4U) 315 #define FTFM_FCSESTAT0_MEMERR_SHIFT (2U) 316 #define FTFM_FCSESTAT0_MEMERR_WIDTH (1U) 317 #define FTFM_FCSESTAT0_MEMERR(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FCSESTAT0_MEMERR_SHIFT)) & FTFM_FCSESTAT0_MEMERR_MASK) 318 /*! @} */ 319 320 /*! @name FERSTAT - Flash Error Status Register */ 321 /*! @{ */ 322 323 #define FTFM_FERSTAT_PDFDIF_MASK (0x1U) 324 #define FTFM_FERSTAT_PDFDIF_SHIFT (0U) 325 #define FTFM_FERSTAT_PDFDIF_WIDTH (1U) 326 #define FTFM_FERSTAT_PDFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERSTAT_PDFDIF_SHIFT)) & FTFM_FERSTAT_PDFDIF_MASK) 327 328 #define FTFM_FERSTAT_DFDIF_MASK (0x2U) 329 #define FTFM_FERSTAT_DFDIF_SHIFT (1U) 330 #define FTFM_FERSTAT_DFDIF_WIDTH (1U) 331 #define FTFM_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERSTAT_DFDIF_SHIFT)) & FTFM_FERSTAT_DFDIF_MASK) 332 333 #define FTFM_FERSTAT_EDFDIF_MASK (0x4U) 334 #define FTFM_FERSTAT_EDFDIF_SHIFT (2U) 335 #define FTFM_FERSTAT_EDFDIF_WIDTH (1U) 336 #define FTFM_FERSTAT_EDFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERSTAT_EDFDIF_SHIFT)) & FTFM_FERSTAT_EDFDIF_MASK) 337 338 #define FTFM_FERSTAT_CDFDIF_MASK (0x8U) 339 #define FTFM_FERSTAT_CDFDIF_SHIFT (3U) 340 #define FTFM_FERSTAT_CDFDIF_WIDTH (1U) 341 #define FTFM_FERSTAT_CDFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERSTAT_CDFDIF_SHIFT)) & FTFM_FERSTAT_CDFDIF_MASK) 342 /*! @} */ 343 344 /*! @name FERCNFG - Flash Error Configuration Register */ 345 /*! @{ */ 346 347 #define FTFM_FERCNFG_PDFDIE_MASK (0x1U) 348 #define FTFM_FERCNFG_PDFDIE_SHIFT (0U) 349 #define FTFM_FERCNFG_PDFDIE_WIDTH (1U) 350 #define FTFM_FERCNFG_PDFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_PDFDIE_SHIFT)) & FTFM_FERCNFG_PDFDIE_MASK) 351 352 #define FTFM_FERCNFG_DFDIE_MASK (0x2U) 353 #define FTFM_FERCNFG_DFDIE_SHIFT (1U) 354 #define FTFM_FERCNFG_DFDIE_WIDTH (1U) 355 #define FTFM_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_DFDIE_SHIFT)) & FTFM_FERCNFG_DFDIE_MASK) 356 357 #define FTFM_FERCNFG_EDFDIE_MASK (0x4U) 358 #define FTFM_FERCNFG_EDFDIE_SHIFT (2U) 359 #define FTFM_FERCNFG_EDFDIE_WIDTH (1U) 360 #define FTFM_FERCNFG_EDFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_EDFDIE_SHIFT)) & FTFM_FERCNFG_EDFDIE_MASK) 361 362 #define FTFM_FERCNFG_CDFDIE_MASK (0x8U) 363 #define FTFM_FERCNFG_CDFDIE_SHIFT (3U) 364 #define FTFM_FERCNFG_CDFDIE_WIDTH (1U) 365 #define FTFM_FERCNFG_CDFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_CDFDIE_SHIFT)) & FTFM_FERCNFG_CDFDIE_MASK) 366 367 #define FTFM_FERCNFG_PFDFD_MASK (0x10U) 368 #define FTFM_FERCNFG_PFDFD_SHIFT (4U) 369 #define FTFM_FERCNFG_PFDFD_WIDTH (1U) 370 #define FTFM_FERCNFG_PFDFD(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_PFDFD_SHIFT)) & FTFM_FERCNFG_PFDFD_MASK) 371 372 #define FTFM_FERCNFG_FDFD_MASK (0x20U) 373 #define FTFM_FERCNFG_FDFD_SHIFT (5U) 374 #define FTFM_FERCNFG_FDFD_WIDTH (1U) 375 #define FTFM_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_FDFD_SHIFT)) & FTFM_FERCNFG_FDFD_MASK) 376 377 #define FTFM_FERCNFG_EFDFD_MASK (0x40U) 378 #define FTFM_FERCNFG_EFDFD_SHIFT (6U) 379 #define FTFM_FERCNFG_EFDFD_WIDTH (1U) 380 #define FTFM_FERCNFG_EFDFD(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_EFDFD_SHIFT)) & FTFM_FERCNFG_EFDFD_MASK) 381 382 #define FTFM_FERCNFG_CFDFD_MASK (0x80U) 383 #define FTFM_FERCNFG_CFDFD_SHIFT (7U) 384 #define FTFM_FERCNFG_CFDFD_WIDTH (1U) 385 #define FTFM_FERCNFG_CFDFD(x) (((uint8_t)(((uint8_t)(x)) << FTFM_FERCNFG_CFDFD_SHIFT)) & FTFM_FERCNFG_CFDFD_MASK) 386 /*! @} */ 387 388 /*! 389 * @} 390 */ /* end of group FTFM_Register_Masks */ 391 392 /*! 393 * @} 394 */ /* end of group FTFM_Peripheral_Access_Layer */ 395 396 #endif /* #if !defined(S32K142W_FTFM_H_) */ 397
