1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_MCM.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_MCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_MCM_H_) /* Check if memory map has not been already included */ 58 #define S32K118_MCM_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MCM - Size of Registers Arrays */ 72 #define MCM_LMDR_COUNT 2u 73 74 /** MCM - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[8]; 77 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 78 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 79 __IO uint32_t CPCR; /**< Core Platform Control Register, offset: 0xC */ 80 uint8_t RESERVED_1[32]; 81 __IO uint32_t PID; /**< Process ID Register, offset: 0x30 */ 82 uint8_t RESERVED_2[12]; 83 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 84 uint8_t RESERVED_3[956]; 85 __IO uint32_t LMDR[MCM_LMDR_COUNT]; /**< Local Memory Descriptor Register, array offset: 0x400, array step: 0x4 */ 86 uint8_t RESERVED_4[120]; 87 uint32_t LMPECR; /**< LMEM Parity and ECC Control Register, offset: 0x480 */ 88 uint8_t RESERVED_5[4]; 89 __IO uint32_t LMPEIR; /**< LMEM Parity and ECC Interrupt Register, offset: 0x488 */ 90 uint8_t RESERVED_6[4]; 91 __I uint32_t LMFAR; /**< LMEM Fault Address Register, offset: 0x490 */ 92 __I uint32_t LMFATR; /**< LMEM Fault Attribute Register, offset: 0x494 */ 93 uint8_t RESERVED_7[8]; 94 __I uint32_t LMFDHR; /**< LMEM Fault Data High Register, offset: 0x4A0 */ 95 __I uint32_t LMFDLR; /**< LMEM Fault Data Low Register, offset: 0x4A4 */ 96 } MCM_Type, *MCM_MemMapPtr; 97 98 /** Number of instances of the MCM module. */ 99 #define MCM_INSTANCE_COUNT (1u) 100 101 /* MCM - Peripheral instance base addresses */ 102 /** Peripheral MCM base address */ 103 #define IP_MCM_BASE (0xF0003000u) 104 /** Peripheral MCM base pointer */ 105 #define IP_MCM ((MCM_Type *)IP_MCM_BASE) 106 /** Array initializer of MCM peripheral base addresses */ 107 #define IP_MCM_BASE_ADDRS { IP_MCM_BASE } 108 /** Array initializer of MCM peripheral base pointers */ 109 #define IP_MCM_BASE_PTRS { IP_MCM } 110 111 /* ---------------------------------------------------------------------------- 112 -- MCM Register Masks 113 ---------------------------------------------------------------------------- */ 114 115 /*! 116 * @addtogroup MCM_Register_Masks MCM Register Masks 117 * @{ 118 */ 119 120 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 121 /*! @{ */ 122 123 #define MCM_PLASC_ASC_MASK (0xFFU) 124 #define MCM_PLASC_ASC_SHIFT (0U) 125 #define MCM_PLASC_ASC_WIDTH (8U) 126 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 127 /*! @} */ 128 129 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 130 /*! @{ */ 131 132 #define MCM_PLAMC_AMC_MASK (0xFFU) 133 #define MCM_PLAMC_AMC_SHIFT (0U) 134 #define MCM_PLAMC_AMC_WIDTH (8U) 135 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 136 /*! @} */ 137 138 /*! @name CPCR - Core Platform Control Register */ 139 /*! @{ */ 140 141 #define MCM_CPCR_HLT_FSM_ST_MASK (0x3U) 142 #define MCM_CPCR_HLT_FSM_ST_SHIFT (0U) 143 #define MCM_CPCR_HLT_FSM_ST_WIDTH (2U) 144 #define MCM_CPCR_HLT_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_HLT_FSM_ST_SHIFT)) & MCM_CPCR_HLT_FSM_ST_MASK) 145 146 #define MCM_CPCR_AXBS_HLT_REQ_MASK (0x4U) 147 #define MCM_CPCR_AXBS_HLT_REQ_SHIFT (2U) 148 #define MCM_CPCR_AXBS_HLT_REQ_WIDTH (1U) 149 #define MCM_CPCR_AXBS_HLT_REQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_AXBS_HLT_REQ_SHIFT)) & MCM_CPCR_AXBS_HLT_REQ_MASK) 150 151 #define MCM_CPCR_AXBS_HLTD_MASK (0x8U) 152 #define MCM_CPCR_AXBS_HLTD_SHIFT (3U) 153 #define MCM_CPCR_AXBS_HLTD_WIDTH (1U) 154 #define MCM_CPCR_AXBS_HLTD(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_AXBS_HLTD_SHIFT)) & MCM_CPCR_AXBS_HLTD_MASK) 155 156 #define MCM_CPCR_FMC_PF_IDLE_MASK (0x10U) 157 #define MCM_CPCR_FMC_PF_IDLE_SHIFT (4U) 158 #define MCM_CPCR_FMC_PF_IDLE_WIDTH (1U) 159 #define MCM_CPCR_FMC_PF_IDLE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_FMC_PF_IDLE_SHIFT)) & MCM_CPCR_FMC_PF_IDLE_MASK) 160 161 #define MCM_CPCR_PBRIDGE_IDLE_MASK (0x40U) 162 #define MCM_CPCR_PBRIDGE_IDLE_SHIFT (6U) 163 #define MCM_CPCR_PBRIDGE_IDLE_WIDTH (1U) 164 #define MCM_CPCR_PBRIDGE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_PBRIDGE_IDLE_SHIFT)) & MCM_CPCR_PBRIDGE_IDLE_MASK) 165 166 #define MCM_CPCR_CBRR_MASK (0x200U) 167 #define MCM_CPCR_CBRR_SHIFT (9U) 168 #define MCM_CPCR_CBRR_WIDTH (1U) 169 #define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_CBRR_SHIFT)) & MCM_CPCR_CBRR_MASK) 170 /*! @} */ 171 172 /*! @name PID - Process ID Register */ 173 /*! @{ */ 174 175 #define MCM_PID_PID_MASK (0xFFU) 176 #define MCM_PID_PID_SHIFT (0U) 177 #define MCM_PID_PID_WIDTH (8U) 178 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) 179 /*! @} */ 180 181 /*! @name CPO - Compute Operation Control Register */ 182 /*! @{ */ 183 184 #define MCM_CPO_CPOREQ_MASK (0x1U) 185 #define MCM_CPO_CPOREQ_SHIFT (0U) 186 #define MCM_CPO_CPOREQ_WIDTH (1U) 187 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 188 189 #define MCM_CPO_CPOACK_MASK (0x2U) 190 #define MCM_CPO_CPOACK_SHIFT (1U) 191 #define MCM_CPO_CPOACK_WIDTH (1U) 192 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 193 194 #define MCM_CPO_CPOWOI_MASK (0x4U) 195 #define MCM_CPO_CPOWOI_SHIFT (2U) 196 #define MCM_CPO_CPOWOI_WIDTH (1U) 197 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 198 /*! @} */ 199 200 /*! @name LMDR - Local Memory Descriptor Register */ 201 /*! @{ */ 202 203 #define MCM_LMDR_CF0_MASK (0xFU) 204 #define MCM_LMDR_CF0_SHIFT (0U) 205 #define MCM_LMDR_CF0_WIDTH (4U) 206 #define MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF0_SHIFT)) & MCM_LMDR_CF0_MASK) 207 208 #define MCM_LMDR_MT_MASK (0xE000U) 209 #define MCM_LMDR_MT_SHIFT (13U) 210 #define MCM_LMDR_MT_WIDTH (3U) 211 #define MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_MT_SHIFT)) & MCM_LMDR_MT_MASK) 212 213 #define MCM_LMDR_DPW_MASK (0xE0000U) 214 #define MCM_LMDR_DPW_SHIFT (17U) 215 #define MCM_LMDR_DPW_WIDTH (3U) 216 #define MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_DPW_SHIFT)) & MCM_LMDR_DPW_MASK) 217 218 #define MCM_LMDR_WY_MASK (0xF00000U) 219 #define MCM_LMDR_WY_SHIFT (20U) 220 #define MCM_LMDR_WY_WIDTH (4U) 221 #define MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_WY_SHIFT)) & MCM_LMDR_WY_MASK) 222 223 #define MCM_LMDR_LMSZ_MASK (0xF000000U) 224 #define MCM_LMDR_LMSZ_SHIFT (24U) 225 #define MCM_LMDR_LMSZ_WIDTH (4U) 226 #define MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZ_SHIFT)) & MCM_LMDR_LMSZ_MASK) 227 228 #define MCM_LMDR_LMSZH_MASK (0x10000000U) 229 #define MCM_LMDR_LMSZH_SHIFT (28U) 230 #define MCM_LMDR_LMSZH_WIDTH (1U) 231 #define MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZH_SHIFT)) & MCM_LMDR_LMSZH_MASK) 232 233 #define MCM_LMDR_V_MASK (0x80000000U) 234 #define MCM_LMDR_V_SHIFT (31U) 235 #define MCM_LMDR_V_WIDTH (1U) 236 #define MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_V_SHIFT)) & MCM_LMDR_V_MASK) 237 /*! @} */ 238 239 /*! @name LMPEIR - LMEM Parity and ECC Interrupt Register */ 240 /*! @{ */ 241 242 #define MCM_LMPEIR_ENC_MASK (0xFFU) 243 #define MCM_LMPEIR_ENC_SHIFT (0U) 244 #define MCM_LMPEIR_ENC_WIDTH (8U) 245 #define MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_SHIFT)) & MCM_LMPEIR_ENC_MASK) 246 247 #define MCM_LMPEIR_E1B_MASK (0xFF00U) 248 #define MCM_LMPEIR_E1B_SHIFT (8U) 249 #define MCM_LMPEIR_E1B_WIDTH (8U) 250 #define MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_E1B_SHIFT)) & MCM_LMPEIR_E1B_MASK) 251 252 #define MCM_LMPEIR_PEELOC_MASK (0x1F000000U) 253 #define MCM_LMPEIR_PEELOC_SHIFT (24U) 254 #define MCM_LMPEIR_PEELOC_WIDTH (5U) 255 #define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK) 256 257 #define MCM_LMPEIR_V_MASK (0x80000000U) 258 #define MCM_LMPEIR_V_SHIFT (31U) 259 #define MCM_LMPEIR_V_WIDTH (1U) 260 #define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK) 261 /*! @} */ 262 263 /*! @name LMFAR - LMEM Fault Address Register */ 264 /*! @{ */ 265 266 #define MCM_LMFAR_EFADD_MASK (0xFFFFFFFFU) 267 #define MCM_LMFAR_EFADD_SHIFT (0U) 268 #define MCM_LMFAR_EFADD_WIDTH (32U) 269 #define MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK) 270 /*! @} */ 271 272 /*! @name LMFATR - LMEM Fault Attribute Register */ 273 /*! @{ */ 274 275 #define MCM_LMFATR_PEFPRT_MASK (0xFU) 276 #define MCM_LMFATR_PEFPRT_SHIFT (0U) 277 #define MCM_LMFATR_PEFPRT_WIDTH (4U) 278 #define MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFPRT_SHIFT)) & MCM_LMFATR_PEFPRT_MASK) 279 280 #define MCM_LMFATR_PEFSIZE_MASK (0x70U) 281 #define MCM_LMFATR_PEFSIZE_SHIFT (4U) 282 #define MCM_LMFATR_PEFSIZE_WIDTH (3U) 283 #define MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSIZE_SHIFT)) & MCM_LMFATR_PEFSIZE_MASK) 284 285 #define MCM_LMFATR_PEFW_MASK (0x80U) 286 #define MCM_LMFATR_PEFW_SHIFT (7U) 287 #define MCM_LMFATR_PEFW_WIDTH (1U) 288 #define MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFW_SHIFT)) & MCM_LMFATR_PEFW_MASK) 289 290 #define MCM_LMFATR_PEFMST_MASK (0xFF00U) 291 #define MCM_LMFATR_PEFMST_SHIFT (8U) 292 #define MCM_LMFATR_PEFMST_WIDTH (8U) 293 #define MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFMST_SHIFT)) & MCM_LMFATR_PEFMST_MASK) 294 295 #define MCM_LMFATR_OVR_MASK (0x80000000U) 296 #define MCM_LMFATR_OVR_SHIFT (31U) 297 #define MCM_LMFATR_OVR_WIDTH (1U) 298 #define MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK) 299 /*! @} */ 300 301 /*! @name LMFDHR - LMEM Fault Data High Register */ 302 /*! @{ */ 303 304 #define MCM_LMFDHR_PEFDH_MASK (0xFFFFFFFFU) 305 #define MCM_LMFDHR_PEFDH_SHIFT (0U) 306 #define MCM_LMFDHR_PEFDH_WIDTH (32U) 307 #define MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDHR_PEFDH_SHIFT)) & MCM_LMFDHR_PEFDH_MASK) 308 /*! @} */ 309 310 /*! @name LMFDLR - LMEM Fault Data Low Register */ 311 /*! @{ */ 312 313 #define MCM_LMFDLR_PEFDL_MASK (0xFFFFFFFFU) 314 #define MCM_LMFDLR_PEFDL_SHIFT (0U) 315 #define MCM_LMFDLR_PEFDL_WIDTH (32U) 316 #define MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDLR_PEFDL_SHIFT)) & MCM_LMFDLR_PEFDL_MASK) 317 /*! @} */ 318 319 /*! 320 * @} 321 */ /* end of group MCM_Register_Masks */ 322 323 /*! 324 * @} 325 */ /* end of group MCM_Peripheral_Access_Layer */ 326 327 #endif /* #if !defined(S32K118_MCM_H_) */ 328
