1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_ADC.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_ADC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_ADC_H_) /* Check if memory map has not been already included */ 58 #define S32K118_ADC_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ADC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ADC - Size of Registers Arrays */ 72 #define ADC_SC1_COUNT 16u 73 #define ADC_R_COUNT 16u 74 #define ADC_CV_COUNT 2u 75 76 /** ADC - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ 79 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ 80 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ 81 __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ 82 __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ 83 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ 84 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ 85 __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ 86 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ 87 __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ 88 __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ 89 __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ 90 __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ 91 __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ 92 __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ 93 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ 94 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ 95 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ 96 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ 97 __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ 98 __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ 99 __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ 100 __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ 101 __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ 102 __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ 103 __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ 104 __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ 105 __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ 106 } ADC_Type, *ADC_MemMapPtr; 107 108 /** Number of instances of the ADC module. */ 109 #define ADC_INSTANCE_COUNT (1u) 110 111 /* ADC - Peripheral instance base addresses */ 112 /** Peripheral ADC0 base address */ 113 #define IP_ADC0_BASE (0x4003B000u) 114 /** Peripheral ADC0 base pointer */ 115 #define IP_ADC0 ((ADC_Type *)IP_ADC0_BASE) 116 /** Array initializer of ADC peripheral base addresses */ 117 #define IP_ADC_BASE_ADDRS { IP_ADC0_BASE } 118 /** Array initializer of ADC peripheral base pointers */ 119 #define IP_ADC_BASE_PTRS { IP_ADC0 } 120 121 /* ---------------------------------------------------------------------------- 122 -- ADC Register Masks 123 ---------------------------------------------------------------------------- */ 124 125 /*! 126 * @addtogroup ADC_Register_Masks ADC Register Masks 127 * @{ 128 */ 129 130 /*! @name SC1 - ADC Status and Control Register 1 */ 131 /*! @{ */ 132 133 #define ADC_SC1_ADCH_MASK (0x1FU) 134 #define ADC_SC1_ADCH_SHIFT (0U) 135 #define ADC_SC1_ADCH_WIDTH (5U) 136 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 137 138 #define ADC_SC1_AIEN_MASK (0x40U) 139 #define ADC_SC1_AIEN_SHIFT (6U) 140 #define ADC_SC1_AIEN_WIDTH (1U) 141 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 142 143 #define ADC_SC1_COCO_MASK (0x80U) 144 #define ADC_SC1_COCO_SHIFT (7U) 145 #define ADC_SC1_COCO_WIDTH (1U) 146 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 147 /*! @} */ 148 149 /*! @name CFG1 - ADC Configuration Register 1 */ 150 /*! @{ */ 151 152 #define ADC_CFG1_ADICLK_MASK (0x3U) 153 #define ADC_CFG1_ADICLK_SHIFT (0U) 154 #define ADC_CFG1_ADICLK_WIDTH (2U) 155 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 156 157 #define ADC_CFG1_MODE_MASK (0xCU) 158 #define ADC_CFG1_MODE_SHIFT (2U) 159 #define ADC_CFG1_MODE_WIDTH (2U) 160 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 161 162 #define ADC_CFG1_ADIV_MASK (0x60U) 163 #define ADC_CFG1_ADIV_SHIFT (5U) 164 #define ADC_CFG1_ADIV_WIDTH (2U) 165 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 166 167 #define ADC_CFG1_CLRLTRG_MASK (0x100U) 168 #define ADC_CFG1_CLRLTRG_SHIFT (8U) 169 #define ADC_CFG1_CLRLTRG_WIDTH (1U) 170 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_CLRLTRG_SHIFT)) & ADC_CFG1_CLRLTRG_MASK) 171 /*! @} */ 172 173 /*! @name CFG2 - ADC Configuration Register 2 */ 174 /*! @{ */ 175 176 #define ADC_CFG2_SMPLTS_MASK (0xFFU) 177 #define ADC_CFG2_SMPLTS_SHIFT (0U) 178 #define ADC_CFG2_SMPLTS_WIDTH (8U) 179 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) 180 /*! @} */ 181 182 /*! @name R - ADC Data Result Registers */ 183 /*! @{ */ 184 185 #define ADC_R_D_MASK (0xFFFU) 186 #define ADC_R_D_SHIFT (0U) 187 #define ADC_R_D_WIDTH (12U) 188 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 189 /*! @} */ 190 191 /*! @name CV - Compare Value Registers */ 192 /*! @{ */ 193 194 #define ADC_CV_CV_MASK (0xFFFFU) 195 #define ADC_CV_CV_SHIFT (0U) 196 #define ADC_CV_CV_WIDTH (16U) 197 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) 198 /*! @} */ 199 200 /*! @name SC2 - Status and Control Register 2 */ 201 /*! @{ */ 202 203 #define ADC_SC2_REFSEL_MASK (0x3U) 204 #define ADC_SC2_REFSEL_SHIFT (0U) 205 #define ADC_SC2_REFSEL_WIDTH (2U) 206 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 207 208 #define ADC_SC2_DMAEN_MASK (0x4U) 209 #define ADC_SC2_DMAEN_SHIFT (2U) 210 #define ADC_SC2_DMAEN_WIDTH (1U) 211 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 212 213 #define ADC_SC2_ACREN_MASK (0x8U) 214 #define ADC_SC2_ACREN_SHIFT (3U) 215 #define ADC_SC2_ACREN_WIDTH (1U) 216 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 217 218 #define ADC_SC2_ACFGT_MASK (0x10U) 219 #define ADC_SC2_ACFGT_SHIFT (4U) 220 #define ADC_SC2_ACFGT_WIDTH (1U) 221 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 222 223 #define ADC_SC2_ACFE_MASK (0x20U) 224 #define ADC_SC2_ACFE_SHIFT (5U) 225 #define ADC_SC2_ACFE_WIDTH (1U) 226 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 227 228 #define ADC_SC2_ADTRG_MASK (0x40U) 229 #define ADC_SC2_ADTRG_SHIFT (6U) 230 #define ADC_SC2_ADTRG_WIDTH (1U) 231 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 232 233 #define ADC_SC2_ADACT_MASK (0x80U) 234 #define ADC_SC2_ADACT_SHIFT (7U) 235 #define ADC_SC2_ADACT_WIDTH (1U) 236 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 237 238 #define ADC_SC2_TRGPRNUM_MASK (0x6000U) 239 #define ADC_SC2_TRGPRNUM_SHIFT (13U) 240 #define ADC_SC2_TRGPRNUM_WIDTH (2U) 241 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGPRNUM_SHIFT)) & ADC_SC2_TRGPRNUM_MASK) 242 243 #define ADC_SC2_TRGSTLAT_MASK (0xF0000U) 244 #define ADC_SC2_TRGSTLAT_SHIFT (16U) 245 #define ADC_SC2_TRGSTLAT_WIDTH (4U) 246 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTLAT_SHIFT)) & ADC_SC2_TRGSTLAT_MASK) 247 248 #define ADC_SC2_TRGSTERR_MASK (0xF000000U) 249 #define ADC_SC2_TRGSTERR_SHIFT (24U) 250 #define ADC_SC2_TRGSTERR_WIDTH (4U) 251 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTERR_SHIFT)) & ADC_SC2_TRGSTERR_MASK) 252 /*! @} */ 253 254 /*! @name SC3 - Status and Control Register 3 */ 255 /*! @{ */ 256 257 #define ADC_SC3_AVGS_MASK (0x3U) 258 #define ADC_SC3_AVGS_SHIFT (0U) 259 #define ADC_SC3_AVGS_WIDTH (2U) 260 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 261 262 #define ADC_SC3_AVGE_MASK (0x4U) 263 #define ADC_SC3_AVGE_SHIFT (2U) 264 #define ADC_SC3_AVGE_WIDTH (1U) 265 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 266 267 #define ADC_SC3_ADCO_MASK (0x8U) 268 #define ADC_SC3_ADCO_SHIFT (3U) 269 #define ADC_SC3_ADCO_WIDTH (1U) 270 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 271 272 #define ADC_SC3_CAL_MASK (0x80U) 273 #define ADC_SC3_CAL_SHIFT (7U) 274 #define ADC_SC3_CAL_WIDTH (1U) 275 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 276 /*! @} */ 277 278 /*! @name BASE_OFS - BASE Offset Register */ 279 /*! @{ */ 280 281 #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) 282 #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) 283 #define ADC_BASE_OFS_BA_OFS_WIDTH (8U) 284 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) 285 /*! @} */ 286 287 /*! @name OFS - ADC Offset Correction Register */ 288 /*! @{ */ 289 290 #define ADC_OFS_OFS_MASK (0xFFFFU) 291 #define ADC_OFS_OFS_SHIFT (0U) 292 #define ADC_OFS_OFS_WIDTH (16U) 293 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 294 /*! @} */ 295 296 /*! @name USR_OFS - USER Offset Correction Register */ 297 /*! @{ */ 298 299 #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) 300 #define ADC_USR_OFS_USR_OFS_SHIFT (0U) 301 #define ADC_USR_OFS_USR_OFS_WIDTH (8U) 302 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) 303 /*! @} */ 304 305 /*! @name XOFS - ADC X Offset Correction Register */ 306 /*! @{ */ 307 308 #define ADC_XOFS_XOFS_MASK (0x3FU) 309 #define ADC_XOFS_XOFS_SHIFT (0U) 310 #define ADC_XOFS_XOFS_WIDTH (6U) 311 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) 312 /*! @} */ 313 314 /*! @name YOFS - ADC Y Offset Correction Register */ 315 /*! @{ */ 316 317 #define ADC_YOFS_YOFS_MASK (0xFFU) 318 #define ADC_YOFS_YOFS_SHIFT (0U) 319 #define ADC_YOFS_YOFS_WIDTH (8U) 320 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) 321 /*! @} */ 322 323 /*! @name G - ADC Gain Register */ 324 /*! @{ */ 325 326 #define ADC_G_G_MASK (0x7FFU) 327 #define ADC_G_G_SHIFT (0U) 328 #define ADC_G_G_WIDTH (11U) 329 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) 330 /*! @} */ 331 332 /*! @name UG - ADC User Gain Register */ 333 /*! @{ */ 334 335 #define ADC_UG_UG_MASK (0x3FFU) 336 #define ADC_UG_UG_SHIFT (0U) 337 #define ADC_UG_UG_WIDTH (10U) 338 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) 339 /*! @} */ 340 341 /*! @name CLPS - ADC General Calibration Value Register S */ 342 /*! @{ */ 343 344 #define ADC_CLPS_CLPS_MASK (0x7FU) 345 #define ADC_CLPS_CLPS_SHIFT (0U) 346 #define ADC_CLPS_CLPS_WIDTH (7U) 347 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 348 /*! @} */ 349 350 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ 351 /*! @{ */ 352 353 #define ADC_CLP3_CLP3_MASK (0x3FFU) 354 #define ADC_CLP3_CLP3_SHIFT (0U) 355 #define ADC_CLP3_CLP3_WIDTH (10U) 356 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 357 /*! @} */ 358 359 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ 360 /*! @{ */ 361 362 #define ADC_CLP2_CLP2_MASK (0x3FFU) 363 #define ADC_CLP2_CLP2_SHIFT (0U) 364 #define ADC_CLP2_CLP2_WIDTH (10U) 365 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 366 /*! @} */ 367 368 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ 369 /*! @{ */ 370 371 #define ADC_CLP1_CLP1_MASK (0x1FFU) 372 #define ADC_CLP1_CLP1_SHIFT (0U) 373 #define ADC_CLP1_CLP1_WIDTH (9U) 374 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 375 /*! @} */ 376 377 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ 378 /*! @{ */ 379 380 #define ADC_CLP0_CLP0_MASK (0xFFU) 381 #define ADC_CLP0_CLP0_SHIFT (0U) 382 #define ADC_CLP0_CLP0_WIDTH (8U) 383 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 384 /*! @} */ 385 386 /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ 387 /*! @{ */ 388 389 #define ADC_CLPX_CLPX_MASK (0x7FU) 390 #define ADC_CLPX_CLPX_SHIFT (0U) 391 #define ADC_CLPX_CLPX_WIDTH (7U) 392 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) 393 /*! @} */ 394 395 /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ 396 /*! @{ */ 397 398 #define ADC_CLP9_CLP9_MASK (0x7FU) 399 #define ADC_CLP9_CLP9_SHIFT (0U) 400 #define ADC_CLP9_CLP9_WIDTH (7U) 401 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) 402 /*! @} */ 403 404 /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ 405 /*! @{ */ 406 407 #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) 408 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) 409 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH (4U) 410 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) 411 /*! @} */ 412 413 /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ 414 /*! @{ */ 415 416 #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) 417 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) 418 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH (4U) 419 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) 420 /*! @} */ 421 422 /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ 423 /*! @{ */ 424 425 #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) 426 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) 427 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH (4U) 428 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) 429 /*! @} */ 430 431 /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ 432 /*! @{ */ 433 434 #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) 435 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) 436 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH (4U) 437 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) 438 /*! @} */ 439 440 /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ 441 /*! @{ */ 442 443 #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) 444 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) 445 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH (4U) 446 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) 447 /*! @} */ 448 449 /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ 450 /*! @{ */ 451 452 #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) 453 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) 454 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH (12U) 455 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) 456 /*! @} */ 457 458 /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ 459 /*! @{ */ 460 461 #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) 462 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) 463 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH (12U) 464 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) 465 /*! @} */ 466 467 /*! 468 * @} 469 */ /* end of group ADC_Register_Masks */ 470 471 /*! 472 * @} 473 */ /* end of group ADC_Peripheral_Access_Layer */ 474 475 #endif /* #if !defined(S32K118_ADC_H_) */ 476
