1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_MTB_DWT.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_MTB_DWT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_MTB_DWT_H_) /* Check if memory map has not been already included */ 58 #define S32K116_MTB_DWT_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MTB_DWT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MTB_DWT_Peripheral_Access_Layer MTB_DWT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MTB_DWT - Size of Registers Arrays */ 72 #define MTB_DWT_CMF_COUNT 2u 73 #define MTB_DWT_PERIPHID_COUNT 8u 74 #define MTB_DWT_COMPID_COUNT 4u 75 76 /** MTB_DWT - Register Layout Typedef */ 77 typedef struct { 78 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 79 uint8_t RESERVED_0[28]; 80 struct { /* offset: 0x20, array step: 0x10 */ 81 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 82 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 83 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 84 uint8_t RESERVED_0[4]; 85 } CMF[MTB_DWT_CMF_COUNT]; 86 uint8_t RESERVED_1[448]; 87 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 88 uint8_t RESERVED_2[3524]; 89 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 90 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 91 __I uint32_t PERIPHID[MTB_DWT_PERIPHID_COUNT]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 92 __I uint32_t COMPID[MTB_DWT_COMPID_COUNT]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 93 } MTB_DWT_Type, *MTB_DWT_MemMapPtr; 94 95 /** Number of instances of the MTB_DWT module. */ 96 #define MTB_DWT_INSTANCE_COUNT (1u) 97 98 /* MTB_DWT - Peripheral instance base addresses */ 99 /** Peripheral MTB_DWT base address */ 100 #define IP_MTB_DWT_BASE (0xF0001000u) 101 /** Peripheral MTB_DWT base pointer */ 102 #define IP_MTB_DWT ((MTB_DWT_Type *)IP_MTB_DWT_BASE) 103 /** Array initializer of MTB_DWT peripheral base addresses */ 104 #define IP_MTB_DWT_BASE_ADDRS { IP_MTB_DWT_BASE } 105 /** Array initializer of MTB_DWT peripheral base pointers */ 106 #define IP_MTB_DWT_BASE_PTRS { IP_MTB_DWT } 107 108 /* ---------------------------------------------------------------------------- 109 -- MTB_DWT Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup MTB_DWT_Register_Masks MTB_DWT Register Masks 114 * @{ 115 */ 116 117 /*! @name CTRL - MTB DWT Control Register */ 118 /*! @{ */ 119 120 #define MTB_DWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 121 #define MTB_DWT_CTRL_DWTCFGCTRL_SHIFT (0U) 122 #define MTB_DWT_CTRL_DWTCFGCTRL_WIDTH (28U) 123 #define MTB_DWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_CTRL_DWTCFGCTRL_SHIFT)) & MTB_DWT_CTRL_DWTCFGCTRL_MASK) 124 125 #define MTB_DWT_CTRL_NUMCMP_MASK (0xF0000000U) 126 #define MTB_DWT_CTRL_NUMCMP_SHIFT (28U) 127 #define MTB_DWT_CTRL_NUMCMP_WIDTH (4U) 128 #define MTB_DWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_CTRL_NUMCMP_SHIFT)) & MTB_DWT_CTRL_NUMCMP_MASK) 129 /*! @} */ 130 131 /*! @name COMP - MTB_DWT Comparator Register */ 132 /*! @{ */ 133 134 #define MTB_DWT_COMP_COMP_MASK (0xFFFFFFFFU) 135 #define MTB_DWT_COMP_COMP_SHIFT (0U) 136 #define MTB_DWT_COMP_COMP_WIDTH (32U) 137 #define MTB_DWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_COMP_COMP_SHIFT)) & MTB_DWT_COMP_COMP_MASK) 138 /*! @} */ 139 140 /*! @name MASK - MTB_DWT Comparator Mask Register */ 141 /*! @{ */ 142 143 #define MTB_DWT_MASK_MASK_MASK (0x1FU) 144 #define MTB_DWT_MASK_MASK_SHIFT (0U) 145 #define MTB_DWT_MASK_MASK_WIDTH (5U) 146 #define MTB_DWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_MASK_MASK_SHIFT)) & MTB_DWT_MASK_MASK_MASK) 147 /*! @} */ 148 149 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 150 /*! @{ */ 151 152 #define MTB_DWT_FCT_FUNCTION_MASK (0xFU) 153 #define MTB_DWT_FCT_FUNCTION_SHIFT (0U) 154 #define MTB_DWT_FCT_FUNCTION_WIDTH (4U) 155 #define MTB_DWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_FUNCTION_SHIFT)) & MTB_DWT_FCT_FUNCTION_MASK) 156 157 #define MTB_DWT_FCT_DATAVMATCH_MASK (0x100U) 158 #define MTB_DWT_FCT_DATAVMATCH_SHIFT (8U) 159 #define MTB_DWT_FCT_DATAVMATCH_WIDTH (1U) 160 #define MTB_DWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_DATAVMATCH_SHIFT)) & MTB_DWT_FCT_DATAVMATCH_MASK) 161 162 #define MTB_DWT_FCT_DATAVSIZE_MASK (0xC00U) 163 #define MTB_DWT_FCT_DATAVSIZE_SHIFT (10U) 164 #define MTB_DWT_FCT_DATAVSIZE_WIDTH (2U) 165 #define MTB_DWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_DATAVSIZE_SHIFT)) & MTB_DWT_FCT_DATAVSIZE_MASK) 166 167 #define MTB_DWT_FCT_DATAVADDR0_MASK (0xF000U) 168 #define MTB_DWT_FCT_DATAVADDR0_SHIFT (12U) 169 #define MTB_DWT_FCT_DATAVADDR0_WIDTH (4U) 170 #define MTB_DWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_DATAVADDR0_SHIFT)) & MTB_DWT_FCT_DATAVADDR0_MASK) 171 172 #define MTB_DWT_FCT_MATCHED_MASK (0x1000000U) 173 #define MTB_DWT_FCT_MATCHED_SHIFT (24U) 174 #define MTB_DWT_FCT_MATCHED_WIDTH (1U) 175 #define MTB_DWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_MATCHED_SHIFT)) & MTB_DWT_FCT_MATCHED_MASK) 176 /*! @} */ 177 178 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 179 /*! @{ */ 180 181 #define MTB_DWT_TBCTRL_ACOMP0_MASK (0x1U) 182 #define MTB_DWT_TBCTRL_ACOMP0_SHIFT (0U) 183 #define MTB_DWT_TBCTRL_ACOMP0_WIDTH (1U) 184 #define MTB_DWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_TBCTRL_ACOMP0_SHIFT)) & MTB_DWT_TBCTRL_ACOMP0_MASK) 185 186 #define MTB_DWT_TBCTRL_ACOMP1_MASK (0x2U) 187 #define MTB_DWT_TBCTRL_ACOMP1_SHIFT (1U) 188 #define MTB_DWT_TBCTRL_ACOMP1_WIDTH (1U) 189 #define MTB_DWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_TBCTRL_ACOMP1_SHIFT)) & MTB_DWT_TBCTRL_ACOMP1_MASK) 190 191 #define MTB_DWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 192 #define MTB_DWT_TBCTRL_NUMCOMP_SHIFT (28U) 193 #define MTB_DWT_TBCTRL_NUMCOMP_WIDTH (4U) 194 #define MTB_DWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_TBCTRL_NUMCOMP_SHIFT)) & MTB_DWT_TBCTRL_NUMCOMP_MASK) 195 /*! @} */ 196 197 /*! @name DEVICECFG - Device Configuration Register */ 198 /*! @{ */ 199 200 #define MTB_DWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 201 #define MTB_DWT_DEVICECFG_DEVICECFG_SHIFT (0U) 202 #define MTB_DWT_DEVICECFG_DEVICECFG_WIDTH (32U) 203 #define MTB_DWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DWT_DEVICECFG_DEVICECFG_MASK) 204 /*! @} */ 205 206 /*! @name DEVICETYPID - Device Type Identifier Register */ 207 /*! @{ */ 208 209 #define MTB_DWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 210 #define MTB_DWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 211 #define MTB_DWT_DEVICETYPID_DEVICETYPID_WIDTH (32U) 212 #define MTB_DWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DWT_DEVICETYPID_DEVICETYPID_MASK) 213 /*! @} */ 214 215 /*! @name PERIPHID - Peripheral ID Register */ 216 /*! @{ */ 217 218 #define MTB_DWT_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU) 219 #define MTB_DWT_PERIPHID_PERIPHID_SHIFT (0U) 220 #define MTB_DWT_PERIPHID_PERIPHID_WIDTH (32U) 221 #define MTB_DWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID_PERIPHID_MASK) 222 /*! @} */ 223 224 /*! @name COMPID - Component ID Register */ 225 /*! @{ */ 226 227 #define MTB_DWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 228 #define MTB_DWT_COMPID_COMPID_SHIFT (0U) 229 #define MTB_DWT_COMPID_COMPID_WIDTH (32U) 230 #define MTB_DWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_COMPID_COMPID_SHIFT)) & MTB_DWT_COMPID_COMPID_MASK) 231 /*! @} */ 232 233 /*! 234 * @} 235 */ /* end of group MTB_DWT_Register_Masks */ 236 237 /*! 238 * @} 239 */ /* end of group MTB_DWT_Peripheral_Access_Layer */ 240 241 #endif /* #if !defined(S32K116_MTB_DWT_H_) */ 242
