1 /*
2 * Copyright 2022-2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_TRDC_H_
9 #define FSL_TRDC_H_
10
11 #include "fsl_common.h"
12 #include "fsl_trdc_core.h"
13
14 /*!
15 * @addtogroup trdc
16 * @{
17 */
18
19 /******************************************************************************
20 * Definitions
21 *****************************************************************************/
22 #define FSL_TRDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
23
24 #if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
25 /* Hardware configuration definitions */
26 /*!
27 * @brief TRDC hardware configuration.
28 */
29 typedef struct _trdc_hardware_config
30 {
31 uint8_t masterNumber; /*!< Number of bus masters. */
32 uint8_t domainNumber; /*!< Number of domains. */
33 uint8_t mbcNumber; /*!< Number of MBCs. */
34 uint8_t mrcNumber; /*!< Number of MRCs. */
35 } trdc_hardware_config_t;
36 #endif
37
38 #if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
39 /*!
40 * @brief Hardware configuration of the two slave memories within each MBC(memory block checker).
41 */
42 typedef struct _trdc_slave_memory_hardware_config
43 {
44 uint32_t blockNum; /*!< Number of blocks. */
45 uint32_t blockSize; /*!< Block size. */
46 } trdc_slave_memory_hardware_config_t;
47 #endif
48
49 #if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT
50 /* Master domain assignment definitions */
51 /*!
52 * @brief TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for
53 * domain hit evaluation.
54 */
55 typedef enum _trdc_did_sel
56 {
57 kTRDC_DidMda, /*!< Use MDAn[2:0] as DID. */
58 kTRDC_DidInput, /*!< Use the input DID (DID_in) as DID. */
59 kTRDC_DidMdaAndInput, /*!< Use MDAn[2] concatenated with DID_in[1:0] as DID. */
60 kTRDC_DidReserved /*!< Reserved. */
61 } trdc_did_sel_t;
62
63 /*!
64 * @brief TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for
65 * bus master domain assignment.
66 */
67 typedef enum _trdc_secure_attr
68 {
69 kTRDC_ForceSecure, /*!< Force the bus attribute for this master to secure. */
70 kTRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure. */
71 kTRDC_MasterSecure, /*!< Use the bus master's secure/nonsecure attribute directly. */
72 kTRDC_MasterSecure1, /*!< Use the bus master's secure/nonsecure attribute directly. */
73 } trdc_secure_attr_t;
74
75 /*!
76 * @brief The configuration of domain hit evaluation of PID.
77 */
78 typedef enum _trdc_pid_domain_hit_config
79 {
80 kTRDC_pidDomainHitNone0, /*!< No PID is included in the domain hit evaluation. */
81 kTRDC_pidDomainHitNone1, /*!< No PID is included in the domain hit evaluation. */
82 kTRDC_pidDomainHitInclusive, /*!< The PID is included in the domain hit evaluation when (PID & ~PIDM). */
83 kTRDC_pidDomainHitExclusive, /*!< The PID is included in the domain hit evaluation when ~(PID & ~PIDM). */
84 } trdc_pid_domain_hit_config_t;
85
86 /*!
87 * @brief Domain assignment for the processor bus master.
88 */
89 typedef struct _trdc_processor_domain_assignment
90 {
91 uint32_t domainId : 4U; /*!< Domain ID. */
92 uint32_t domainIdSelect : 2U; /*!< Domain ID select method, see @ref trdc_did_sel_t. */
93 uint32_t pidDomainHitConfig : 2U; /*!< The configuration of the domain hit evaluation for PID, see @ref
94 trdc_pid_domain_hit_config_t. */
95 uint32_t pidMask : 6U; /*!< The mask combined with PID, so multiple PID can be included as part of the domain hit
96 determination. Set to 0 to disable. */
97 uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */
98 uint32_t pid : 6U; /*!< The process identifier, combined with pidMask to form the domain hit determination. */
99 uint32_t : 8U; /*!< Reserved. */
100 uint32_t lock : 1U; /*!< Lock the register. */
101 uint32_t : 1U; /*!< Reserved. */
102 } trdc_processor_domain_assignment_t;
103
104 /*!
105 * @brief TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor
106 * bus master domain assignment.
107 */
108 typedef enum _trdc_privilege_attr
109 {
110 kTRDC_ForceUser, /*!< Force the bus attribute for this master to user. */
111 kTRDC_ForcePrivilege, /*!< Force the bus attribute for this master to privileged. */
112 kTRDC_MasterPrivilege, /*!< Use the bus master's attribute directly. */
113 kTRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */
114 } trdc_privilege_attr_t;
115
116 /*!
117 * @brief Domain assignment for the non-processor bus master.
118 */
119 typedef struct _trdc_non_processor_domain_assignment
120 {
121 uint32_t domainId : 4U; /*!< Domain ID. */
122 uint32_t privilegeAttr : 2U; /*!< Privileged attribute, see @ref trdc_privilege_attr_t. */
123 uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */
124 uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */
125 uint32_t : 21U; /*!< Reserved. */
126 uint32_t lock : 1U; /*!< Lock the register. */
127 uint32_t : 1U; /*!< Reserved. */
128 } trdc_non_processor_domain_assignment_t;
129
130 /*!
131 * @brief PID lock configuration.
132 */
133 typedef enum _trdc_pid_lock
134 {
135 kTRDC_PidUnlocked0, /*!< The PID value can be updated by any secure priviledged write. */
136 kTRDC_PidUnlocked1, /*!< The PID value can be updated by any secure priviledged write. */
137 kTRDC_PidUnlocked2, /*!< The PID value can be updated by any secure priviledged write from the bus master that first
138 configured this register. */
139 kTRDC_PidLocked, /*!< The PID value is locked until next reset. */
140 } trdc_pid_lock_t;
141
142 /*!
143 * @brief Process identifier(PID) configuration for processor cores.
144 */
145 typedef struct _trdc_pid_config
146 {
147 uint32_t pid : 6U; /*!< The process identifier of the executing task. The highest bit can be used to define
148 secure/nonsecure attribute of the task. */
149 uint32_t : 23U; /*!< Reserved. */
150 uint32_t lock : 2U; /*!< How to lock the register, see @ref trdc_pid_lock_t. */
151 uint32_t : 1U; /*!< Reserved. */
152 } trdc_pid_config_t;
153 #endif
154
155 #if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
156 /* TZ-M congiguration definitions */
157 /*!
158 * @brief IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.
159 */
160 typedef struct _trdc_idau_config
161 {
162 uint32_t : 8U; /*!< Reserved. */
163 uint32_t lockSecureVTOR : 1U; /*!< Disable writes to secure VTOR(Vector Table Offset Register). */
164 uint32_t lockNonsecureVTOR : 1U; /*!< Disable writes to non-secure VTOR, Application interrupt and Reset Control
165 Registers. */
166 uint32_t lockSecureMPU : 1U; /*!< Disable writes to secure MPU(Memory Protection Unit) from software or from a debug
167 agent connected to the processor in Secure state. */
168 uint32_t lockNonsecureMPU : 1U; /*!< Disable writes to non-secure MPU(Memory Protection Unit) from software or from
169 a debug agent connected to the processor. */
170 uint32_t lockSAU : 1U; /*!< Disable writes to SAU(Security Attribution Unit) registers. */
171 uint32_t : 19U; /*!< Reserved. */
172 } trdc_idau_config_t;
173
174 /* FLW(Flash Logical Window) configuration definitions */
175 /*!
176 * @brief FLW(Flash Logical Window) configuration.
177 */
178 typedef struct _trdc_flw_config
179 {
180 uint16_t blockCount; /*!< Block count of the Flash Logic Window in 32KByte blocks. */
181 uint32_t arrayBaseAddr; /*!< Flash array base address of the Flash Logical Window. */
182 bool lock; /*!< Disable writes to FLW registers. */
183 bool enable; /*!< Enable FLW function. */
184 } trdc_flw_config_t;
185 #endif
186
187 #if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR
188 /* Domain error check and clear definitions */
189 /*!
190 * @brief TRDC controller definition for domain error check. Each TRDC instance may have different
191 * MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.
192 */
193 typedef enum _trdc_controller
194 {
195 kTRDC_MemBlockController0 = 0U, /*!< Memory block checker 0. */
196 kTRDC_MemBlockController1 = 1U, /*!< Memory block checker 1. */
197 kTRDC_MemBlockController2 = 2U, /*!< Memory block checker 2. */
198 kTRDC_MemBlockController3 = 3U, /*!< Memory block checker 3. */
199 kTRDC_MemRegionChecker0 = 4U, /*!< Memory region checker 0. */
200 kTRDC_MemRegionChecker1 = 5U, /*!< Memory region checker 1. */
201 kTRDC_MemRegionChecker2 = 6U, /*!< Memory region checker 2. */
202 kTRDC_MemRegionChecker3 = 7U, /*!< Memory region checker 3. */
203 kTRDC_MemRegionChecker4 = 8U, /*!< Memory region checker 4. */
204 kTRDC_MemRegionChecker5 = 9U, /*!< Memory region checker 5. */
205 kTRDC_MemRegionChecker6 = 10U, /*!< Memory region checker 6. */
206 } trdc_controller_t;
207
208 /*!
209 * @brief TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].
210 */
211 typedef enum _trdc_error_state
212 {
213 kTRDC_ErrorStateNone = 0x00U, /*!< No access violation detected. */
214 kTRDC_ErrorStateNone1 = 0x01U, /*!< No access violation detected. */
215 kTRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected. */
216 kTRDC_ErrorStateMulti = 0x03U /*!< Multiple access violation detected. */
217 } trdc_error_state_t;
218
219 /*!
220 * @brief TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].
221 */
222 typedef enum _trdc_error_attr
223 {
224 kTRDC_ErrorSecureUserInst = 0x00U, /*!< Secure user mode, instruction fetch access. */
225 kTRDC_ErrorSecureUserData = 0x01U, /*!< Secure user mode, data access. */
226 kTRDC_ErrorSecurePrivilegeInst = 0x02U, /*!< Secure privileged mode, instruction fetch access. */
227 kTRDC_ErrorSecurePrivilegeData = 0x03U, /*!< Secure privileged mode, data access. */
228 kTRDC_ErrorNonSecureUserInst = 0x04U, /*!< NonSecure user mode, instruction fetch access. */
229 kTRDC_ErrorNonSecureUserData = 0x05U, /*!< NonSecure user mode, data access. */
230 kTRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access. */
231 kTRDC_ErrorNonSecurePrivilegeData = 0x07U /*!< NonSecure privileged mode, data access. */
232 } trdc_error_attr_t;
233
234 /*!
235 * @brief TRDC domain error access type definition TRDC_DERR_W1_n[ERW].
236 */
237 typedef enum _trdc_error_type
238 {
239 kTRDC_ErrorTypeRead = 0x00U, /*!< Error occurs on read reference. */
240 kTRDC_ErrorTypeWrite = 0x01U /*!< Error occurs on write reference. */
241 } trdc_error_type_t;
242
243 /*!
244 * @brief TRDC domain error definition.
245 */
246 typedef struct _trdc_domain_error
247 {
248 trdc_controller_t controller; /*!< Which controller captured access violation. */
249 uint32_t address; /*!< Access address that generated access violation. */
250 trdc_error_state_t errorState; /*!< Error state. */
251 trdc_error_attr_t errorAttr; /*!< Error attribute. */
252 trdc_error_type_t errorType; /*!< Error type. */
253 uint8_t errorPort; /*!< Error port. */
254 uint8_t domainId; /*!< Domain ID. */
255 uint8_t slaveMemoryIdx; /*!< The slave memory index. Only apply when violation in MBC. */
256 } trdc_domain_error_t;
257 #endif
258
259 #if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \
260 (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC)
261 /* Common definitions for MBC/MRC configuration */
262 /*!
263 * @brief Memory access control configuration for MBC/MRC.
264 */
265 typedef struct _trdc_memory_access_control_config
266 {
267 uint32_t nonsecureUsrX : 1U; /*!< Allow nonsecure user execute access. */
268 uint32_t nonsecureUsrW : 1U; /*!< Allow nonsecure user write access. */
269 uint32_t nonsecureUsrR : 1U; /*!< Allow nonsecure user read access. */
270 uint32_t : 1U; /*!< Reserved. */
271 uint32_t nonsecurePrivX : 1U; /*!< Allow nonsecure privilege execute access. */
272 uint32_t nonsecurePrivW : 1U; /*!< Allow nonsecure privilege write access. */
273 uint32_t nonsecurePrivR : 1U; /*!< Allow nonsecure privilege read access. */
274 uint32_t : 1U; /*!< Reserved. */
275 uint32_t secureUsrX : 1U; /*!< Allow secure user execute access. */
276 uint32_t secureUsrW : 1U; /*!< Allow secure user write access. */
277 uint32_t secureUsrR : 1U; /*!< Allow secure user read access. */
278 uint32_t : 1U; /*!< Reserved. */
279 uint32_t securePrivX : 1U; /*!< Allownsecure privilege execute access. */
280 uint32_t securePrivW : 1U; /*!< Allownsecure privilege write access. */
281 uint32_t securePrivR : 1U; /*!< Allownsecure privilege read access. */
282 uint32_t : 16U; /*!< Reserved. */
283 uint32_t lock : 1U; /*!< Lock the configuration until next reset, only apply to access control register 0. */
284 } trdc_memory_access_control_config_t;
285 #endif
286
287 #if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC
288 /*! @brief The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions.
289 */
290 enum _trdc_region_descriptor
291 {
292 kTRDC_RegionDescriptor0 = (1U << 0U), /*!< Region descriptor 0. */
293 kTRDC_RegionDescriptor1 = (1U << 1U), /*!< Region descriptor 1. */
294 kTRDC_RegionDescriptor2 = (1U << 2U), /*!< Region descriptor 2. */
295 kTRDC_RegionDescriptor3 = (1U << 3U), /*!< Region descriptor 3. */
296 kTRDC_RegionDescriptor4 = (1U << 4U), /*!< Region descriptor 4. */
297 kTRDC_RegionDescriptor5 = (1U << 5U), /*!< Region descriptor 5. */
298 kTRDC_RegionDescriptor6 = (1U << 6U), /*!< Region descriptor 6. */
299 kTRDC_RegionDescriptor7 = (1U << 7U), /*!< Region descriptor 7. */
300 kTRDC_RegionDescriptor8 = (1U << 8U), /*!< Region descriptor 8. */
301 kTRDC_RegionDescriptor9 = (1U << 9U), /*!< Region descriptor 9. */
302 kTRDC_RegionDescriptor10 = (1U << 10U), /*!< Region descriptor 10. */
303 kTRDC_RegionDescriptor11 = (1U << 11U), /*!< Region descriptor 11. */
304 kTRDC_RegionDescriptor12 = (1U << 12U), /*!< Region descriptor 12. */
305 kTRDC_RegionDescriptor13 = (1U << 13U), /*!< Region descriptor 13. */
306 kTRDC_RegionDescriptor14 = (1U << 14U), /*!< Region descriptor 14. */
307 kTRDC_RegionDescriptor15 = (1U << 15U), /*!< Region descriptor 15. */
308 };
309
310 /* MRC configuration definitions */
311 /*! @brief The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or
312 * several domains. */
313 enum _trdc_MRC_domain
314 {
315 kTRDC_MrcDomain0 = (1U << 0U), /*!< Domain 0. */
316 kTRDC_MrcDomain1 = (1U << 1U), /*!< Domain 1. */
317 kTRDC_MrcDomain2 = (1U << 2U), /*!< Domain 2. */
318 kTRDC_MrcDomain3 = (1U << 3U), /*!< Domain 3. */
319 kTRDC_MrcDomain4 = (1U << 4U), /*!< Domain 4. */
320 kTRDC_MrcDomain5 = (1U << 5U), /*!< Domain 5. */
321 kTRDC_MrcDomain6 = (1U << 6U), /*!< Domain 6. */
322 kTRDC_MrcDomain7 = (1U << 7U), /*!< Domain 7. */
323 kTRDC_MrcDomain8 = (1U << 8U), /*!< Domain 8. */
324 kTRDC_MrcDomain9 = (1U << 9U), /*!< Domain 9. */
325 kTRDC_MrcDomain10 = (1U << 10U), /*!< Domain 10. */
326 kTRDC_MrcDomain11 = (1U << 11U), /*!< Domain 11. */
327 kTRDC_MrcDomain12 = (1U << 12U), /*!< Domain 12. */
328 kTRDC_MrcDomain13 = (1U << 13U), /*!< Domain 13. */
329 kTRDC_MrcDomain14 = (1U << 14U), /*!< Domain 14. */
330 kTRDC_MrcDomain15 = (1U << 15U), /*!< Domain 15. */
331 };
332
333 /*!
334 * @brief The configuration of each region descriptor per domain per MRC instance.
335 */
336 typedef struct _trdc_mrc_region_descriptor_config
337 {
338 uint8_t memoryAccessControlSelect; /*!< Select one of the 8 access control policies for this region, for
339 access cotrol policies see @ref trdc_memory_access_control_config_t. */
340 uint32_t startAddr; /*!< Physical start address. */
341 bool valid; /*!< Lock the register. */
342 bool nseEnable; /*!< Enable non-secure accesses and disable secure accesses. */
343 uint32_t endAddr; /*!< Physical start address. */
344 uint8_t mrcIdx; /*!< The index of the MRC for this configuration to take effect. */
345 uint8_t domainIdx; /*!< The index of the domain for this configuration to take effect. */
346 uint8_t regionIdx; /*!< The index of the region for this configuration to take effect. */
347 } trdc_mrc_region_descriptor_config_t;
348 #endif
349
350 #if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
351 /* MBC configuration definitions */
352 /*!
353 * @brief The configuration of MBC NSE update.
354 */
355 #if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && (FSL_FEATURE_TRDC_DOMAIN_COUNT > 0x8U)
356 typedef struct _trdc_mbc_nse_update_config
357 {
358 uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this
359 configuration. */
360 uint32_t : 1U; /*!< Reserved. */
361 uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */
362 uint32_t : 2U; /*!< Reserved. */
363 uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */
364 uint32_t : 4U; /*!< Reserved. */
365 uint32_t domianSelect : 16U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */
366 } trdc_mbc_nse_update_config_t;
367 #else
368 typedef struct _trdc_mbc_nse_update_config
369 {
370 uint32_t : 2U; /*!< Reserved. */
371 uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */
372 uint32_t : 2U; /*!< Reserved. */
373 uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */
374 uint32_t : 4U; /*!< Reserved. */
375 uint32_t domianSelect : 8U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */
376 uint32_t : 7U; /*!< Reserved. */
377 uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this
378 configuration. */
379 } trdc_mbc_nse_update_config_t;
380 #endif
381
382 /*! @brief The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or
383 * several domains. */
384 enum _trdc_MBC_domain
385 {
386 kTRDC_MbcDomain0 = (1U << 0U), /*!< Domain 0. */
387 kTRDC_MbcDomain1 = (1U << 1U), /*!< Domain 1. */
388 kTRDC_MbcDomain2 = (1U << 2U), /*!< Domain 2. */
389 kTRDC_MbcDomain3 = (1U << 3U), /*!< Domain 3. */
390 kTRDC_MbcDomain4 = (1U << 4U), /*!< Domain 4. */
391 kTRDC_MbcDomain5 = (1U << 5U), /*!< Domain 5. */
392 kTRDC_MbcDomain6 = (1U << 6U), /*!< Domain 6. */
393 kTRDC_MbcDomain7 = (1U << 7U), /*!< Domain 7. */
394 };
395
396 /*! @brief The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one
397 * or several memory block. */
398 enum _trdc_MBC_memory
399 {
400 kTRDC_MbcSlaveMemory0 = (1U << 0U), /*!< Memory 0. */
401 kTRDC_MbcSlaveMemory1 = (1U << 1U), /*!< Memory 1. */
402 kTRDC_MbcSlaveMemory2 = (1U << 2U), /*!< Memory 2. */
403 kTRDC_MbcSlaveMemory3 = (1U << 3U), /*!< Memory 3. */
404 };
405
406 /*! @brief The MBC bit enumeration, used to form a mask to set/clear configured words' NSE. */
407 enum _trdc_MBC_bit
408 {
409 kTRDC_MbcBit0 = (1U << 0U), /*!< Bit 0. */
410 kTRDC_MbcBit1 = (1U << 1U), /*!< Bit 1. */
411 kTRDC_MbcBit2 = (1U << 2U), /*!< Bit 2. */
412 kTRDC_MbcBit3 = (1U << 3U), /*!< Bit 3. */
413 kTRDC_MbcBit4 = (1U << 4U), /*!< Bit 4. */
414 kTRDC_MbcBit5 = (1U << 5U), /*!< Bit 5. */
415 kTRDC_MbcBit6 = (1U << 6U), /*!< Bit 6. */
416 kTRDC_MbcBit7 = (1U << 7U), /*!< Bit 7. */
417 kTRDC_MbcBit8 = (1U << 8U), /*!< Bit 8. */
418 kTRDC_MbcBit9 = (1U << 9U), /*!< Bit 9. */
419 kTRDC_MbcBit10 = (1U << 10U), /*!< Bit 10. */
420 kTRDC_MbcBit11 = (1U << 11U), /*!< Bit 11. */
421 kTRDC_MbcBit12 = (1U << 12U), /*!< Bit 12. */
422 kTRDC_MbcBit13 = (1U << 13U), /*!< Bit 13. */
423 kTRDC_MbcBit14 = (1U << 14U), /*!< Bit 14. */
424 kTRDC_MbcBit15 = (1U << 15U), /*!< Bit 15. */
425 kTRDC_MbcBit16 = (1U << 16U), /*!< Bit 16. */
426 kTRDC_MbcBit17 = (1U << 17U), /*!< Bit 17. */
427 kTRDC_MbcBit18 = (1U << 18U), /*!< Bit 18. */
428 kTRDC_MbcBit19 = (1U << 19U), /*!< Bit 19. */
429 kTRDC_MbcBit20 = (1U << 20U), /*!< Bit 20. */
430 kTRDC_MbcBit21 = (1U << 21U), /*!< Bit 21. */
431 kTRDC_MbcBit22 = (1U << 22U), /*!< Bit 22. */
432 kTRDC_MbcBit23 = (1U << 23U), /*!< Bit 23. */
433 kTRDC_MbcBit24 = (1U << 24U), /*!< Bit 24. */
434 kTRDC_MbcBit25 = (1U << 25U), /*!< Bit 25. */
435 kTRDC_MbcBit26 = (1U << 26U), /*!< Bit 26. */
436 kTRDC_MbcBit27 = (1U << 27U), /*!< Bit 27. */
437 kTRDC_MbcBit28 = (1U << 28U), /*!< Bit 28. */
438 kTRDC_MbcBit29 = (1U << 29U), /*!< Bit 29. */
439 kTRDC_MbcBit30 = (1U << 30U), /*!< Bit 30. */
440 kTRDC_MbcBit31 = (1U << 31U), /*!< Bit 31. */
441 };
442
443 /*!
444 * @brief The configuration of each memory block per domain per MBC instance.
445 */
446 typedef struct _trdc_mbc_memory_block_config
447 {
448 uint32_t memoryAccessControlSelect : 3U; /*!< Select one of the 8 access control policies for this memory block, for
449 access cotrol policies see @ref trdc_memory_access_control_config_t. */
450 uint32_t nseEnable : 1U; /*!< Enable non-secure accesses and disable secure accesses. */
451 uint32_t mbcIdx : 4U; /*!< The index of the MBC for this configuration to take effect. */
452 uint32_t domainIdx : 8U; /*!< The index of the domain for this configuration to take effect. */
453 uint32_t slaveMemoryIdx : 8U; /*!< The index of the slave memory for this configuration to take effect. */
454 uint32_t memoryBlockIdx : 8U; /*!< The index of the memory block for this configuration to take effect. */
455 } trdc_mbc_memory_block_config_t;
456 #endif
457
458 /*******************************************************************************
459 * API
460 ******************************************************************************/
461
462 #if defined(__cplusplus)
463 extern "C" {
464 #endif
465
466 /*!
467 * @name Initialization and deinitialization
468 * @{
469 */
470 /*!
471 * @brief Initializes the TRDC module.
472 *
473 * This function enables the TRDC clock.
474 *
475 * @param base TRDC peripheral base address.
476 */
477 void TRDC_Init(TRDC_Type *base);
478
479 /*!
480 * @brief De-initializes the TRDC module.
481 *
482 * This function disables the TRDC clock.
483 *
484 * @param base TRDC peripheral base address.
485 */
486 void TRDC_Deinit(TRDC_Type *base);
487 /*! @} */
488
489 #if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
490 /*!
491 * @name Hardware configuration
492 * @{
493 */
494 /*!
495 * @brief Gets the domain ID of the current bus master.
496 *
497 * @param base TRDC peripheral base address.
498 * @return Domain ID of current bus master.
499 */
TRDC_GetCurrentMasterDomainId(TRDC_Type * base)500 static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)
501 {
502 return (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG1 & TRDC_TRDC_HWCFG1_DID_MASK) >> TRDC_TRDC_HWCFG1_DID_SHIFT);
503 }
504
505 /*!
506 * @brief Gets the TRDC hardware configuration.
507 *
508 * This function gets the TRDC hardware configurations, including number of bus
509 * masters, number of domains, number of MRCs and number of PACs.
510 *
511 * @param base TRDC peripheral base address.
512 * @param config Pointer to the structure to get the configuration.
513 */
514 void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config);
515 /*! @} */
516 #endif
517
518 #if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT
519 /*!
520 * @name Master domain assignment
521 * @{
522 */
523 /*!
524 * @brief Sets the TRDC DAC(Domain Assignment Controllers) global valid.
525 *
526 * Once enabled, it will remain enabled until next reset.
527 *
528 * @param base TRDC peripheral base address.
529 */
TRDC_SetDacGlobalValid(TRDC_Type * base)530 static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)
531 {
532 TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDM_MASK;
533 }
534
535 /*!
536 * @brief Locks the bus master domain assignment register.
537 *
538 * This function locks the master domain assignment. After it is locked, the register can't be changed
539 * until next reset.
540 *
541 * @param base TRDC peripheral base address.
542 * @param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.
543 * @param regNum Which register to configure, processor master can have more than one register for the MDAC
544 configuration.
545 * @param assignIndex Which assignment register to lock.
546 */
TRDC_LockMasterDomainAssignment(TRDC_Type * base,uint8_t master,uint8_t regNum)547 static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum)
548 {
549 /* Make sure in the master range. */
550 assert((uint32_t)master <
551 ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
552 if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK))
553 {
554 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_LK1_MASK;
555 }
556 else
557 {
558 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_LK1_MASK;
559 }
560 }
561
562 /*!
563 * @brief Sets the master domain assignment as valid or invalid.
564 *
565 * This function sets the master domain assignment as valid or invalid.
566 *
567 * @param base TRDC peripheral base address.
568 * @param master Which master to configure.
569 * @param regNum Which register to configure, processor master can have more than one register for the MDAC
570 * configuration.
571 * @param assignIndex Index for the domain assignment register.
572 * @param valid True to set valid, false to set invalid.
573 */
TRDC_SetMasterDomainAssignmentValid(TRDC_Type * base,uint8_t master,uint8_t regNum,bool valid)574 static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid)
575 {
576 /* Make sure in the master range. */
577 assert((uint32_t)master <
578 ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
579 if (valid)
580 {
581 if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK))
582 {
583 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_VLD_MASK;
584 }
585 else
586 {
587 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_VLD_MASK;
588 }
589 }
590 else
591 {
592 if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK))
593 {
594 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] &= ~TRDC_MDA_W_DFMT0_VLD_MASK;
595 }
596 else
597 {
598 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] &= ~TRDC_MDA_W_DFMT1_VLD_MASK;
599 }
600 }
601 }
602
603 /*!
604 * @brief Gets the default master domain assignment for the processor bus master.
605 *
606 * This function gets the default master domain assignment for the processor bus master.
607 * It should only be used for the processor bus masters, such as CORE0. This function
608 * sets the assignment as follows:
609 *
610 * @code
611 * assignment->domainId = 0U;
612 * assignment->domainIdSelect = kTRDC_DidMda;
613 * assignment->lock = 0U;
614 * @endcode
615 *
616 * @param domainAssignment Pointer to the assignment structure.
617 */
618 void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment);
619
620 /*!
621 * @brief Gets the default master domain assignment for non-processor bus master.
622 *
623 * This function gets the default master domain assignment for non-processor bus master.
624 * It should only be used for the non-processor bus masters, such as DMA. This function
625 * sets the assignment as follows:
626 *
627 * @code
628 * assignment->domainId = 0U;
629 * assignment->privilegeAttr = kTRDC_ForceUser;
630 * assignment->secureAttr = kTRDC_ForceSecure;
631 * assignment->bypassDomainId = 0U;
632 * assignment->lock = 0U;
633 * @endcode
634 *
635 * @param domainAssignment Pointer to the assignment structure.
636 */
637 void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment);
638
639 /*!
640 * @brief Sets the processor bus master domain assignment.
641 *
642 * This function sets the processor master domain assignment as valid.
643 * One bus master might have multiple domain assignment registers. The parameter
644 * \p assignIndex specifies which assignment register to set.
645 *
646 * Example: Set domain assignment for core 0.
647 *
648 * @code
649 * trdc_processor_domain_assignment_t processorAssignment;
650 *
651 * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);
652 *
653 * processorAssignment.domainId = 0;
654 * processorAssignment.xxx = xxx;
655 * TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);
656 * @endcode
657 *
658 * @param base TRDC peripheral base address.
659 * @param master Which master to configure, refer to trdc_master_t in processor header file.
660 * @param regNum Which register to configure, processor master can have more than one register for the MDAC
661 * configuration.
662 * @param domainAssignment Pointer to the assignment structure.
663 */
664 void TRDC_SetProcessorDomainAssignment(TRDC_Type *base,
665 uint8_t master,
666 uint8_t regNum,
667 const trdc_processor_domain_assignment_t *domainAssignment);
668
669 /*!
670 * @brief Sets the non-processor bus master domain assignment.
671 *
672 * This function sets the non-processor master domain assignment as valid.
673 * One bus master might have multiple domain assignment registers. The parameter
674 * \p assignIndex specifies which assignment register to set.
675 *
676 * Example: Set domain assignment for DMA0.
677 * @code
678 * trdc_non_processor_domain_assignment_t nonProcessorAssignment;
679 *
680 * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
681 * nonProcessorAssignment.domainId = 1;
682 * nonProcessorAssignment.xxx = xxx;
683 *
684 * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);
685 * @endcode
686 *
687 * @param base TRDC peripheral base address.
688 * @param master Which master to configure, refer to trdc_master_t in processor header file.
689 * @param domainAssignment Pointer to the assignment structure.
690 */
691 void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base,
692 uint8_t master,
693 const trdc_non_processor_domain_assignment_t *domainAssignment);
694
695 /*!
696 * @brief Gets the bit map of the bus master(s) that is(are) sourcing a PID register.
697 *
698 * This function sets the non-processor master domain assignment as valid.
699 *
700 * @param base TRDC peripheral base address.
701 * @return the bit map of the master(s). Bit 1 sets indicates bus master 1.
702 */
TRDC_GetActiveMasterPidMap(TRDC_Type * base)703 static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base)
704 {
705 return ((uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG3 << 32U) | (uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG2;
706 }
707
708 /*!
709 * @brief Sets the current Process identifier(PID) for processor core.
710 *
711 * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains.
712 * Secure privileged software saves and restores the PID as part of any context switch.
713 * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register
714 * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3]
715 * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding
716 * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information
717 * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality.
718 *
719 * @param base TRDC peripheral base address.
720 * @param master Which processor master to configure, refer to trdc_master_t in processor header file.
721 * @param pidConfig Pointer to the configuration structure.
722 */
723 void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig);
724 /*! @} */
725 #endif
726
727 #if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
728 /*!
729 * @name TZ-M congiguration
730 * @{
731 */
732 /*!
733 * @brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.
734 *
735 * @code
736 * config->lockSecureVTOR = false;
737 * config->lockNonsecureVTOR = false;
738 * config->lockSecureMPU = false;
739 * config->lockNonsecureMPU = false;
740 * config->lockSAU = false;
741 * @endcode
742 *
743 * @param domainAssignment Pointer to the configuration structure.
744 */
745 void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration);
746
747 /*!
748 * @brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.
749 *
750 * Example: Lock the secure and non-secure MPU registers.
751 *
752 * @code
753 * trdc_idau_config_t idauConfiguration;
754 *
755 * TRDC_GetDefaultIDAUConfig(&idauConfiguration);
756 *
757 * idauConfiguration.lockSecureMPU = true;
758 * idauConfiguration.lockNonsecureMPU = true;
759 * TRDC_SetIDAU(TRDC, &idauConfiguration);
760 * @endcode
761 *
762 * @param base TRDC peripheral base address.
763 * @param domainAssignment Pointer to the configuration structure.
764 */
765 void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration);
766 /*! @} */
767 #endif
768
769 #if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW
770 /*!
771 * @name FLW(Flash Logical Window) configuration
772 * @{
773 */
774 /*!
775 * @brief Enables/disables the FLW(flash logical window) function.
776 *
777 * @param base TRDC peripheral base address.
778 * @param enable True to enable, false to disable.
779 */
TRDC_EnableFlashLogicalWindow(TRDC_Type * base,bool enable)780 static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)
781 {
782 if (enable)
783 {
784 TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_V_MASK;
785 }
786 else
787 {
788 TRDC_FLW_BASE(base)->TRDC_FLW_CTL &= ~TRDC_TRDC_FLW_CTL_V_MASK;
789 }
790 }
791
792 /*!
793 * @brief Locks FLW registers. Once locked the registers can noy be updated until next reset.
794 *
795 * @param base TRDC peripheral base address.
796 */
TRDC_LockFlashLogicalWindow(TRDC_Type * base)797 static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)
798 {
799 TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_LK_MASK;
800 }
801
802 /*!
803 * @brief Gets the FLW physical base address.
804 *
805 * @param base TRDC peripheral base address.
806 * @return Physical address of the FLW function.
807 */
TRDC_GetFlashLogicalWindowPbase(TRDC_Type * base)808 static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)
809 {
810 return TRDC_FLW_BASE(base)->TRDC_FLW_PBASE;
811 }
812
813 /*!
814 * @brief Sets the FLW size.
815 *
816 * @param base TRDC peripheral base address.
817 * @param size Size of the FLW in unit of 32k bytes.
818 */
TRDC_GetSetFlashLogicalWindowSize(TRDC_Type * base,uint16_t size)819 static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)
820 {
821 TRDC_FLW_BASE(base)->TRDC_FLW_BCNT = size;
822 }
823
824 /*!
825 * @brief Gets the default FLW(Flsh Logical Window) configuration.
826 *
827 * @code
828 * config->blockCount = false;
829 * config->arrayBaseAddr = false;
830 * config->lock = false;
831 * config->enable = false;
832 * @endcode
833 *
834 * @param flwConfiguration Pointer to the configuration structure.
835 */
836 void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration);
837
838 /*!
839 * @brief Sets the FLW function's configuration.
840 *
841 * @code
842 * trdc_flw_config_t flwConfiguration;
843 *
844 * TRDC_GetDefaultIDAUConfig(&flwConfiguration);
845 *
846 * flwConfiguration.blockCount = 32U;
847 * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
848 * TRDC_SetIDAU(TRDC, &flwConfiguration);
849 * @endcode
850 *
851 * @param base TRDC peripheral base address.
852 * @param flwConfiguration Pointer to the configuration structure.
853 */
854 void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration);
855 /*! @} */
856 #endif
857
858 #if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR
859 /*!
860 * @name Domain error check and clear
861 * @{
862 */
863 /*!
864 * @brief Gets and clears the first domain error of the current domain.
865 *
866 * This function gets the first access violation information for the current domain
867 * and clears the pending flag. There might be multiple access violations pending
868 * for the current domain. This function only processes the first error.
869 *
870 * @param base TRDC peripheral base address.
871 * @param error Pointer to the error information.
872 * @return If the access violation is captured, this function returns the kStatus_Success.
873 * The error information can be obtained from the parameter error. If no
874 * access violation is captured, this function returns the kStatus_NoData.
875 */
876 status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error);
877
878 /*!
879 * @brief Gets and clears the first domain error of the specific domain.
880 *
881 * This function gets the first access violation information for the specific domain
882 * and clears the pending flag. There might be multiple access violations pending
883 * for the current domain. This function only processes the first error.
884 *
885 * @param base TRDC peripheral base address.
886 * @param error Pointer to the error information.
887 * @param domainId The error of which domain to get and clear.
888 * @return If the access violation is captured, this function returns the kStatus_Success.
889 * The error information can be obtained from the parameter error. If no
890 * access violation is captured, this function returns the kStatus_NoData.
891 */
892 status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId);
893 /*! @} */
894 #endif
895
896 #if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC
897 /*!
898 * @name MRC configuration
899 * @{
900 */
901 #if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
902 /*!
903 * @brief Sets the TRDC MRC(Memory Region Checkers) global valid.
904 *
905 * Once enabled, it will remain enabled until next reset.
906 *
907 * @param base TRDC peripheral base address.
908 */
TRDC_SetMrcGlobalValid(TRDC_Type * base)909 static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)
910 {
911 TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDR_MASK;
912 }
913 #endif
914
915 /*!
916 * @brief Gets the TRDC MRC(Memory Region Checkers) region number valid.
917 *
918 * @param base TRDC peripheral base address.
919 * @return the region number of the given MRC instance
920 */
TRDC_GetMrcRegionNumber(TRDC_Type * base,uint8_t mrcIdx)921 static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)
922 {
923 return (uint8_t)((TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBCFG & TRDC_MRC_GLBCFG_NRGNS_MASK) >>
924 TRDC_MRC_GLBCFG_NRGNS_SHIFT);
925 }
926
927 /*!
928 * @brief Sets the memory access configuration for one of the access control register of one MRC.
929 *
930 * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
931 *
932 * @code
933 * trdc_memory_access_control_config_t config;
934 *
935 * config.securePrivX = true;
936 * config.securePrivW = true;
937 * config.securePrivR = true;
938 * config.lock = true;
939 * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);
940 * @endcode
941 *
942 * @param base TRDC peripheral base address.
943 * @param config Pointer to the configuration structure.
944 * @param mrcIdx MRC index.
945 * @param regIdx Register number.
946 */
947 void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base,
948 const trdc_memory_access_control_config_t *config,
949 uint8_t mrcIdx,
950 uint8_t regIdx);
951
952 /*!
953 * @brief Enables the update of the selected domians.
954 *
955 * After the domians' update are enabled, their regions' NSE bits can be set or clear.
956 *
957 * @param base TRDC peripheral base address.
958 * @param mrcIdx MRC index.
959 * @param domianMask Bit mask of the domains to be enabled.
960 * @param enable True to enable, false to disable.
961 */
962 void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable);
963
964 /*!
965 * @brief Sets the NSE bits of the selected regions for domains.
966 *
967 * This function sets the NSE bits for the selected regions for the domains whose update are enabled.
968 *
969 * @param base TRDC peripheral base address.
970 * @param mrcIdx MRC index.
971 * @param regionMask Bit mask of the regions whose NSE bits to set.
972 */
973 void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask);
974
975 /*!
976 * @brief Clears the NSE bits of the selected regions for domains.
977 *
978 * This function clears the NSE bits for the selected regions for the domains whose update are enabled.
979 *
980 * @param base TRDC peripheral base address.
981 * @param mrcIdx MRC index.
982 * @param regionMask Bit mask of the regions whose NSE bits to clear.
983 */
984 void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask);
985
986 /*!
987 * @brief Clears the NSE bits for all the regions of the selected domains.
988 *
989 * This function clears the NSE bits for all regions of selected domains whose update are enabled.
990 *
991 * @param base TRDC peripheral base address.
992 * @param mrcIdx MRC index.
993 * @param domainMask Bit mask of the domians whose NSE bits to clear.
994 */
995 void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask);
996
997 /*!
998 * @brief Sets the configuration for one of the region descriptor per domain per MRC instnce.
999 *
1000 * This function sets the configuration for one of the region descriptor, including the start
1001 * and end address of the region, memory access control policy and valid.
1002 *
1003 * @param base TRDC peripheral base address.
1004 * @param config Pointer to region descriptor configuration structure.
1005 */
1006 void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config);
1007 /*! @} */
1008 #endif
1009
1010 #if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
1011 /*!
1012 * @name MBC configuration
1013 * @{
1014 */
1015 #if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
1016 /*!
1017 * @brief Sets the TRDC MBC(Memory Block Checkers) global valid.
1018 *
1019 * Once enabled, it will remain enabled until next reset.
1020 *
1021 * @param base TRDC peripheral base address.
1022 */
TRDC_SetMbcGlobalValid(TRDC_Type * base)1023 static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)
1024 {
1025 TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDB_MASK;
1026 }
1027 #endif
1028
1029 /*!
1030 * @brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).
1031 *
1032 * @param base TRDC peripheral base address.
1033 * @param config Pointer to the structure to get the configuration.
1034 * @param mbcIdx MBC number.
1035 * @param slvIdx Slave number.
1036 */
1037 void TRDC_GetMbcHardwareConfig(TRDC_Type *base,
1038 trdc_slave_memory_hardware_config_t *config,
1039 uint8_t mbcIdx,
1040 uint8_t slvIdx);
1041
1042 /*!
1043 * @brief Sets the NSR update configuration for one of the MBC instance.
1044 *
1045 * After set the NSE configuration, the configured memory area can be updateby NSE set/clear.
1046 *
1047 * @param base TRDC peripheral base address.
1048 * @param config Pointer to NSE update configuration structure.
1049 * @param mbcIdx MBC index.
1050 */
1051 void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx);
1052
1053 /*!
1054 * @brief Sets the NSE bits of the selected configuration words according to NSE update configuration.
1055 *
1056 * This function sets the NSE bits of the word for the configured regio, memory.
1057 *
1058 * @param base TRDC peripheral base address.
1059 * @param mbcIdx MBC index.
1060 * @param bitMask Mask of the bits whose NSE bits to set.
1061 */
1062 void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask);
1063
1064 /*!
1065 * @brief Clears the NSE bits of the selected configuration words according to NSE update configuration.
1066 *
1067 * This function sets the NSE bits of the word for the configured regio, memory.
1068 *
1069 * @param base TRDC peripheral base address.
1070 * @param mbcIdx MBC index.
1071 * @param bitMask Mask of the bits whose NSE bits to clear.
1072 */
1073 void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask);
1074
1075 /*!
1076 * @brief Clears all configuration words' NSE bits of the selected domain and memory.
1077 *
1078 * @param base TRDC peripheral base address.
1079 * @param mbcIdx MBC index.
1080 * @param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.
1081 * @param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits.
1082 */
1083 void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave);
1084
1085 /*!
1086 * @brief Sets the memory access configuration for one of the region descriptor of one MBC.
1087 *
1088 * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
1089 *
1090 * @code
1091 * trdc_memory_access_control_config_t config;
1092 *
1093 * config.securePrivX = true;
1094 * config.securePrivW = true;
1095 * config.securePrivR = true;
1096 * config.lock = true;
1097 * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);
1098 * @endcode
1099 *
1100 * @param base TRDC peripheral base address.
1101 * @param config Pointer to the configuration structure.
1102 * @param mbcIdx MBC index.
1103 * @param rgdIdx Region descriptor number.
1104 */
1105 void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base,
1106 const trdc_memory_access_control_config_t *config,
1107 uint8_t mbcIdx,
1108 uint8_t rgdIdx);
1109
1110 /*!
1111 * @brief Sets the configuration for one of the memory block per domain per MBC instnce.
1112 *
1113 * This function sets the configuration for one of the memory block, including the memory access
1114 * control policy and nse enable.
1115 *
1116 * @param base TRDC peripheral base address.
1117 * @param config Pointer to memory block configuration structure.
1118 */
1119 void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config);
1120 /*! @} */
1121 #endif
1122
1123 #if defined(__cplusplus)
1124 }
1125 #endif
1126
1127 /*!
1128 * @}
1129 */
1130
1131 #endif /* FSL_TRDC_H_ */
1132
