1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_DPU_IRQSTEER_H_
9 #define _FSL_DPU_IRQSTEER_H_
10 
11 #include "fsl_common.h"
12 
13 /*!
14  * @addtogroup dpu_irqsteer
15  * @{
16  */
17 
18 /*******************************************************************************
19  * Definitions
20  ******************************************************************************/
21 
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.dpu_irqsteer"
25 #endif
26 
27 /*! @name Driver version */
28 /*@{*/
29 #define FSL_DPU_IRQSTEER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
30 /*@}*/
31 
32 /* Convert the IRQn to IRQSTEER channel number. */
33 #define DPU_IRQSTEER_INT_SRC_REG_INDEX(irq) (FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT - 1U - (((uint32_t)(irq)) >> 5U))
34 
35 /* Convert the IRQn to control bit index in IRQSTEER channel. */
36 #define DPU_IRQSTEER_INT_SRC_BIT_OFFSET(irq) (((uint32_t)(irq)) & 0x1FU)
37 
38 /*******************************************************************************
39  * API
40  ******************************************************************************/
41 
42 #if defined(__cplusplus)
43 extern "C" {
44 #endif
45 
46 /*!
47  * @brief Enables an interrupt source.
48  *
49  * @param base DPU IRQSTEER peripheral base address.
50  * @param irq Interrupt to be enabled.
51  */
DPU_IRQSTEER_EnableInterrupt(IRQSTEER_Type * base,DPU_IRQSTEER_IRQn_Type irq)52 static inline void DPU_IRQSTEER_EnableInterrupt(IRQSTEER_Type *base, DPU_IRQSTEER_IRQn_Type irq)
53 {
54     base->CHn_MASK[DPU_IRQSTEER_INT_SRC_REG_INDEX(irq)] |= (1U << ((uint32_t)DPU_IRQSTEER_INT_SRC_BIT_OFFSET(irq)));
55 }
56 
57 /*!
58  * @brief Disables an interrupt source.
59  *
60  * @param base DPU IRQSTEER peripheral base address.
61  * @param irq Interrupt to be disabled.
62  */
DPU_IRQSTEER_DisableInterrupt(IRQSTEER_Type * base,DPU_IRQSTEER_IRQn_Type irq)63 static inline void DPU_IRQSTEER_DisableInterrupt(IRQSTEER_Type *base, DPU_IRQSTEER_IRQn_Type irq)
64 {
65     base->CHn_MASK[DPU_IRQSTEER_INT_SRC_REG_INDEX(irq)] &= ~(1U << ((uint32_t)DPU_IRQSTEER_INT_SRC_BIT_OFFSET(irq)));
66 }
67 
68 /*!
69  * @brief Checks the status of one specific DPU IRQSTEER interrupt.
70  *
71  * @param base DPU IRQSTEER peripheral base address.
72  * @param irq Interrupt source status to be checked. The interrupt must be an IRQSTEER source.
73  * @return The interrupt status. "true" means interrupt set. "false" means not.
74  */
DPU_IRQSTEER_IsInterruptSet(IRQSTEER_Type * base,DPU_IRQSTEER_IRQn_Type irq)75 static inline bool DPU_IRQSTEER_IsInterruptSet(IRQSTEER_Type *base, DPU_IRQSTEER_IRQn_Type irq)
76 {
77     if ((base->CHn_STATUS[DPU_IRQSTEER_INT_SRC_REG_INDEX(irq)] &
78          (1U << ((uint32_t)DPU_IRQSTEER_INT_SRC_BIT_OFFSET(irq)))) != 0U)
79     {
80         return true;
81     }
82     else
83     {
84         return false;
85     }
86 }
87 
88 #if defined(__cplusplus)
89 }
90 #endif
91 
92 /*! @} */
93 
94 #endif /* _FSL_DPU_IRQSTEER_H_ */
95