1 /*
2 * Copyright 2022 - 2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_CACHE_H_
9 #define FSL_CACHE_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup xcache
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief cache driver version. */
25 #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
26 /*! @} */
27
28 /*! @brief cache line size. */
29 #define XCACHE_LINESIZE_BYTE (FSL_FEATURE_XCACHE_LINESIZE_BYTE)
30
31 /*******************************************************************************
32 * API
33 ******************************************************************************/
34
35 #if defined(__cplusplus)
36 extern "C" {
37 #endif
38
39 /*!
40 * @name cache control for XCACHE
41 *@{
42 */
43
44 /*!
45 * brief Returns an instance number given physical memory address.
46 *
47 * param address The physical memory address.
48 * @return XCACHE instance number starting from 0.
49 */
50 uint32_t XCACHE_GetInstanceByAddr(uint32_t address);
51
52 /*!
53 * @brief Enables the cache.
54 *
55 * @param base XCACHE peripheral base address.
56 *
57 */
58 void XCACHE_EnableCache(XCACHE_Type *base);
59
60 /*!
61 * @brief Disables the cache.
62 *
63 * @param base XCACHE peripheral base address.
64 *
65 */
66 void XCACHE_DisableCache(XCACHE_Type *base);
67
68 /*!
69 * @brief Invalidates the cache.
70 *
71 * @param base XCACHE peripheral base address.
72 *
73 */
74 void XCACHE_InvalidateCache(XCACHE_Type *base);
75
76 /*!
77 * @brief Invalidates cache by range.
78 *
79 * @param address The physical address of cache.
80 * @param size_byte size of the memory to be invalidated, should be larger than 0, better to align with cache line size.
81 * @note Address and size should be aligned to "XCACHE_LINESIZE_BYTE".
82 * The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if
83 * startAddr is not aligned. For the size_byte, application should make sure the
84 * alignment or make sure the right operation order if the size_byte is not aligned.
85 */
86 void XCACHE_InvalidateCacheByRange(uint32_t address, uint32_t size_byte);
87
88 /*!
89 * @brief Cleans the cache.
90 *
91 * @param base XCACHE peripheral base address.
92 *
93 */
94 void XCACHE_CleanCache(XCACHE_Type *base);
95
96 /*!
97 * @brief Cleans cache by range.
98 *
99 * @param address The physical address of cache.
100 * @param size_byte size of the memory to be cleaned, should be larger than 0, better to align with cache line size.
101 * @note Address and size should be aligned to "XCACHE_LINESIZE_BYTE".
102 * The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if
103 * startAddr is not aligned. For the size_byte, application should make sure the
104 * alignment or make sure the right operation order if the size_byte is not aligned.
105 */
106 void XCACHE_CleanCacheByRange(uint32_t address, uint32_t size_byte);
107
108 /*!
109 * @brief Cleans and invalidates the cache.
110 *
111 * @param base XCACHE peripheral base address.
112 *
113 */
114 void XCACHE_CleanInvalidateCache(XCACHE_Type *base);
115
116 /*!
117 * @brief Cleans and invalidate cache by range.
118 *
119 * @param address The physical address of cache.
120 * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0,
121 better to align with cache line size.
122 * @note Address and size should be aligned to "XCACHE_LINESIZE_BYTE".
123 * The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if
124 * startAddr is not aligned. For the size_byte, application should make sure the
125 * alignment or make sure the right operation order if the size_byte is not aligned.
126 */
127 void XCACHE_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
128
129 #if !((defined(FSL_FEATURE_XCACHE_HAS_NO_WRITE_BUF)) && (FSL_FEATURE_XCACHE_HAS_NO_WRITE_BUF))
130 /*!
131 * @brief Enables/disables the write buffer.
132 *
133 * @param base XCACHE peripheral base address.
134 * @param enable The enable or disable flag.
135 * true - enable the write buffer.
136 * false - disable the write buffer.
137 */
138 void XCACHE_EnableWriteBuffer(XCACHE_Type *base, bool enable);
139 #endif
140
141 /*! @} */
142
143 /*!
144 * @name Unified Cache Control for all caches
145 *@{
146 */
147
148 /*!
149 * @brief Invalidates instruction cache by range.
150 *
151 * @param address The physical address.
152 * @param size_byte size of the memory to be invalidated, should be larger than 0, better to align with cache line size.
153 * @note Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit
154 * FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
155 * size if startAddr is not aligned. For the size_byte, application should make sure the
156 * alignment or make sure the right operation order if the size_byte is not aligned.
157 */
ICACHE_InvalidateByRange(uint32_t address,uint32_t size_byte)158 static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
159 {
160 XCACHE_InvalidateCacheByRange(address, size_byte);
161 }
162
163 /*!
164 * @brief Invalidates data cache by range.
165 *
166 * @param address The physical address.
167 * @param size_byte size of the memory to be invalidated, should be larger than 0, better to align with cache line size.
168 * @note Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit
169 * FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
170 * size if startAddr is not aligned. For the size_byte, application should make sure the
171 * alignment or make sure the right operation order if the size_byte is not aligned.
172 */
DCACHE_InvalidateByRange(uint32_t address,uint32_t size_byte)173 static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
174 {
175 XCACHE_InvalidateCacheByRange(address, size_byte);
176 }
177
178 /*!
179 * @brief Clean data cache by range.
180 *
181 * @param address The physical address.
182 * @param size_byte size of the memory to be cleaned, should be larger than 0, better to align with cache line size.
183 * @note Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit
184 * FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
185 * size if startAddr is not aligned. For the size_byte, application should make sure the
186 * alignment or make sure the right operation order if the size_byte is not aligned.
187 */
DCACHE_CleanByRange(uint32_t address,uint32_t size_byte)188 static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
189 {
190 XCACHE_CleanCacheByRange(address, size_byte);
191 }
192
193 /*!
194 * @brief Cleans and Invalidates data cache by range.
195 *
196 * @param address The physical address.
197 * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0,
198 better to align with cache line size.
199 * @note Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit
200 * FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
201 * size if startAddr is not aligned. For the size_byte, application should make sure the
202 * alignment or make sure the right operation order if the size_byte is not aligned.
203 */
DCACHE_CleanInvalidateByRange(uint32_t address,uint32_t size_byte)204 static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
205 {
206 XCACHE_CleanInvalidateCacheByRange(address, size_byte);
207 }
208
209 /*! @} */
210
211 #if defined(__cplusplus)
212 }
213 #endif
214
215 /*! @}*/
216
217 #endif /* FSL_CACHE_H_*/
218
