1 /* 2 ** ################################################################### 3 ** Version: rev. 2.5, 2015-06-08 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2013-11-22) 20 ** Initial version. 21 ** - rev. 1.1 (2014-01-30) 22 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 23 ** - rev. 2.0 (2014-11-26) 24 ** update of SystemInit() imlementation 25 ** Module access macro module_BASES replaced by module_BASE_PTRS. 26 ** Register accessor macros added to the memory map. 27 ** MCG - bit LOLS in MCG_S register renamed to LOLS0. 28 ** DAC0 registers removed. 29 ** - rev. 2.1 (2015-01-21) 30 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 31 ** - rev. 2.2 (2015-05-19) 32 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 33 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 34 ** Added features for PORT and PDB. 35 ** - rev. 2.3 (2015-05-25) 36 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 37 ** - rev. 2.4 (2015-05-27) 38 ** Several USB features added. 39 ** - rev. 2.5 (2015-06-08) 40 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 41 ** 42 ** ################################################################### 43 */ 44 45 #ifndef _MKW24D5_FEATURES_H_ 46 #define _MKW24D5_FEATURES_H_ 47 48 /* SOC module features */ 49 50 /* @brief ADC16 availability on the SoC. */ 51 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 52 /* @brief MMCAU availability on the SoC. */ 53 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 54 /* @brief CMP availability on the SoC. */ 55 #define FSL_FEATURE_SOC_CMP_COUNT (2) 56 /* @brief CMT availability on the SoC. */ 57 #define FSL_FEATURE_SOC_CMT_COUNT (1) 58 /* @brief CRC availability on the SoC. */ 59 #define FSL_FEATURE_SOC_CRC_COUNT (1) 60 /* @brief EDMA availability on the SoC. */ 61 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 62 /* @brief DMAMUX availability on the SoC. */ 63 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 64 /* @brief DSPI availability on the SoC. */ 65 #define FSL_FEATURE_SOC_DSPI_COUNT (2) 66 /* @brief EWM availability on the SoC. */ 67 #define FSL_FEATURE_SOC_EWM_COUNT (1) 68 /* @brief FMC availability on the SoC. */ 69 #define FSL_FEATURE_SOC_FMC_COUNT (1) 70 /* @brief FTFL availability on the SoC. */ 71 #define FSL_FEATURE_SOC_FTFL_COUNT (1) 72 /* @brief FTM availability on the SoC. */ 73 #define FSL_FEATURE_SOC_FTM_COUNT (3) 74 /* @brief GPIO availability on the SoC. */ 75 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 76 /* @brief I2C availability on the SoC. */ 77 #define FSL_FEATURE_SOC_I2C_COUNT (2) 78 /* @brief I2S availability on the SoC. */ 79 #define FSL_FEATURE_SOC_I2S_COUNT (1) 80 /* @brief LLWU availability on the SoC. */ 81 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 82 /* @brief LPTMR availability on the SoC. */ 83 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 84 /* @brief MCG availability on the SoC. */ 85 #define FSL_FEATURE_SOC_MCG_COUNT (1) 86 /* @brief MCM availability on the SoC. */ 87 #define FSL_FEATURE_SOC_MCM_COUNT (1) 88 /* @brief OSC availability on the SoC. */ 89 #define FSL_FEATURE_SOC_OSC_COUNT (1) 90 /* @brief PDB availability on the SoC. */ 91 #define FSL_FEATURE_SOC_PDB_COUNT (1) 92 /* @brief PIT availability on the SoC. */ 93 #define FSL_FEATURE_SOC_PIT_COUNT (1) 94 /* @brief PMC availability on the SoC. */ 95 #define FSL_FEATURE_SOC_PMC_COUNT (1) 96 /* @brief PORT availability on the SoC. */ 97 #define FSL_FEATURE_SOC_PORT_COUNT (5) 98 /* @brief RCM availability on the SoC. */ 99 #define FSL_FEATURE_SOC_RCM_COUNT (1) 100 /* @brief RFSYS availability on the SoC. */ 101 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 102 /* @brief RNG availability on the SoC. */ 103 #define FSL_FEATURE_SOC_RNG_COUNT (1) 104 /* @brief RTC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_RTC_COUNT (1) 106 /* @brief SIM availability on the SoC. */ 107 #define FSL_FEATURE_SOC_SIM_COUNT (1) 108 /* @brief SMC availability on the SoC. */ 109 #define FSL_FEATURE_SOC_SMC_COUNT (1) 110 /* @brief UART availability on the SoC. */ 111 #define FSL_FEATURE_SOC_UART_COUNT (3) 112 /* @brief USB availability on the SoC. */ 113 #define FSL_FEATURE_SOC_USB_COUNT (1) 114 /* @brief USBDCD availability on the SoC. */ 115 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 116 /* @brief WDOG availability on the SoC. */ 117 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 118 119 /* ADC16 module features */ 120 121 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 122 #define FSL_FEATURE_ADC16_HAS_PGA (0) 123 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 124 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 125 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 126 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 127 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 128 #define FSL_FEATURE_ADC16_HAS_DMA (1) 129 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 130 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 131 /* @brief Has FIFO (bit SC4[AFDEP]). */ 132 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 133 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 134 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 135 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 136 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 137 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 138 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 139 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 140 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 141 /* @brief Has HW averaging (bit SC3[AVGE]). */ 142 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 143 /* @brief Has offset correction (register OFS). */ 144 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 145 /* @brief Maximum ADC resolution. */ 146 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 147 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 148 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 149 150 /* CMP module features */ 151 152 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 153 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) 154 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 155 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 156 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 157 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 158 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 159 #define FSL_FEATURE_CMP_HAS_DMA (1) 160 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 161 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) 162 /* @brief Has DAC Test function in CMP (register DACTEST). */ 163 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 164 165 /* CRC module features */ 166 167 /* @brief Has data register with name CRC */ 168 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 169 170 /* EDMA module features */ 171 172 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 173 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 174 /* @brief Total number of DMA channels on all modules. */ 175 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) 176 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 177 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 178 /* @brief Has DMA_Error interrupt vector. */ 179 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 180 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 181 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) 182 /* @brief Channel IRQ entry shared offset. */ 183 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 184 /* @brief If 8 bytes transfer supported. */ 185 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 186 /* @brief If 16 bytes transfer supported. */ 187 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 188 189 /* DMAMUX module features */ 190 191 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 192 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 193 /* @brief Total number of DMA channels on all modules. */ 194 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16) 195 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 196 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 197 /* @brief Register CHCFGn width. */ 198 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 199 200 /* EWM module features */ 201 202 /* @brief Has clock select (register CLKCTRL). */ 203 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 204 /* @brief Has clock prescaler (register CLKPRESCALER). */ 205 #define FSL_FEATURE_EWM_HAS_PRESCALER (0) 206 207 /* FLASH module features */ 208 209 /* @brief Is of type FTFA. */ 210 #define FSL_FEATURE_FLASH_IS_FTFA (0) 211 /* @brief Is of type FTFE. */ 212 #define FSL_FEATURE_FLASH_IS_FTFE (0) 213 /* @brief Is of type FTFL. */ 214 #define FSL_FEATURE_FLASH_IS_FTFL (1) 215 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 216 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 217 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 218 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 219 /* @brief Has EEPROM region protection (register FEPROT). */ 220 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 221 /* @brief Has data flash region protection (register FDPROT). */ 222 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 223 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 224 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 225 /* @brief Has flash cache control in FMC module. */ 226 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 227 /* @brief Has flash cache control in MCM module. */ 228 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 229 /* @brief Has flash cache control in MSCM module. */ 230 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 231 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 232 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 233 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 234 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 235 /* @brief P-Flash start address. */ 236 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 237 /* @brief P-Flash block count. */ 238 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 239 /* @brief P-Flash block size. */ 240 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 241 /* @brief P-Flash sector size. */ 242 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 243 /* @brief P-Flash write unit size. */ 244 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 245 /* @brief P-Flash data path width. */ 246 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 247 /* @brief P-Flash block swap feature. */ 248 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) 249 /* @brief P-Flash protection region count. */ 250 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 251 /* @brief Has FlexNVM memory. */ 252 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 253 /* @brief Has FlexNVM alias. */ 254 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 255 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 256 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 257 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 258 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 259 /* @brief FlexNVM block count. */ 260 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 261 /* @brief FlexNVM block size. */ 262 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 263 /* @brief FlexNVM sector size. */ 264 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 265 /* @brief FlexNVM write unit size. */ 266 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 267 /* @brief FlexNVM data path width. */ 268 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 269 /* @brief Has FlexRAM memory. */ 270 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 271 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 272 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 273 /* @brief FlexRAM size. */ 274 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 275 /* @brief Has 0x00 Read 1s Block command. */ 276 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 277 /* @brief Has 0x01 Read 1s Section command. */ 278 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 279 /* @brief Has 0x02 Program Check command. */ 280 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 281 /* @brief Has 0x03 Read Resource command. */ 282 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 283 /* @brief Has 0x06 Program Longword command. */ 284 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 285 /* @brief Has 0x07 Program Phrase command. */ 286 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 287 /* @brief Has 0x08 Erase Flash Block command. */ 288 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 289 /* @brief Has 0x09 Erase Flash Sector command. */ 290 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 291 /* @brief Has 0x0B Program Section command. */ 292 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 293 /* @brief Has 0x40 Read 1s All Blocks command. */ 294 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 295 /* @brief Has 0x41 Read Once command. */ 296 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 297 /* @brief Has 0x43 Program Once command. */ 298 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 299 /* @brief Has 0x44 Erase All Blocks command. */ 300 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 301 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 302 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 303 /* @brief Has 0x46 Swap Control command. */ 304 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) 305 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 306 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 307 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 308 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 309 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 310 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 311 /* @brief Has 0x80 Program Partition command. */ 312 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 313 /* @brief Has 0x81 Set FlexRAM Function command. */ 314 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 315 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 316 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 317 /* @brief P-Flash Erase sector command address alignment. */ 318 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 319 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 320 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 321 /* @brief P-Flash Read resource command address alignment. */ 322 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 323 /* @brief P-Flash Program check command address alignment. */ 324 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 325 /* @brief P-Flash Program check command address alignment. */ 326 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (8) 327 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 328 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 329 /* @brief FlexNVM Erase sector command address alignment. */ 330 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 331 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 332 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 333 /* @brief FlexNVM Read resource command address alignment. */ 334 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 335 /* @brief FlexNVM Program check command address alignment. */ 336 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 337 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 338 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 339 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 340 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 341 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 342 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 343 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 344 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 345 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 346 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 347 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 348 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 349 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 350 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 351 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 352 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 353 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 354 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 355 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 356 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 357 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 358 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 359 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 361 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 363 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 365 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 366 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 367 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 368 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 369 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 370 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 371 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 372 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 373 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 374 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 375 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 376 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 377 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 378 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 379 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 381 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 383 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 385 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 387 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 389 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 391 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 393 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 395 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 397 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 398 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 399 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 400 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 401 402 /* FTM module features */ 403 404 /* @brief Number of channels. */ 405 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 406 (((x) == FTM0) ? (8) : \ 407 (((x) == FTM1) ? (2) : \ 408 (((x) == FTM2) ? (2) : (-1)))) 409 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 410 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 411 /* @brief Has extended deadtime value. */ 412 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 413 /* @brief Enable pwm output for the module. */ 414 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 415 /* @brief Has half-cycle reload for the module. */ 416 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 417 /* @brief Has reload interrupt. */ 418 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 419 /* @brief Has reload initialization trigger. */ 420 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 421 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 422 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 423 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 424 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 425 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 426 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 427 /* @brief Has no QDCTRL. */ 428 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 429 /* @brief If instance has only TPM function. */ 430 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 431 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 432 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0) 433 434 /* GPIO module features */ 435 436 /* @brief Has GPIO attribute checker register (GACR). */ 437 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 438 439 /* I2C module features */ 440 441 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 442 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 443 /* @brief Maximum supported baud rate in kilobit per second. */ 444 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 445 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 446 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 447 /* @brief Has DMA support (register bit C1[DMAEN]). */ 448 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 449 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 450 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0) 451 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 452 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 453 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 454 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0) 455 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 456 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) 457 /* @brief Has control of the drive capability of the I2C pins. */ 458 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 459 /* @brief Has double buffering support (register S2). */ 460 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 461 /* @brief Has double buffer enable. */ 462 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 463 464 /* SAI module features */ 465 466 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 467 #define FSL_FEATURE_SAI_HAS_FIFO (1) 468 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 469 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) 470 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 471 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (1) 472 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 473 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16) 474 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 475 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 476 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 477 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) 478 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 479 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) 480 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 481 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) 482 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 483 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 484 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 485 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 486 /* @brief Ihe interrupt source number */ 487 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 488 /* @brief Has register of MCR. */ 489 #define FSL_FEATURE_SAI_HAS_MCR (1) 490 /* @brief Has register of MDR */ 491 #define FSL_FEATURE_SAI_HAS_MDR (1) 492 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 493 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 494 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 495 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 496 497 /* LLWU module features */ 498 499 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 500 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 501 /* @brief Has pins 8-15 connected to LLWU device. */ 502 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 503 /* @brief Maximum number of internal modules connected to LLWU device. */ 504 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 505 /* @brief Number of digital filters. */ 506 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 507 /* @brief Has MF register. */ 508 #define FSL_FEATURE_LLWU_HAS_MF (0) 509 /* @brief Has PF register. */ 510 #define FSL_FEATURE_LLWU_HAS_PF (0) 511 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 512 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) 513 /* @brief Has no internal module wakeup flag register. */ 514 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 515 /* @brief Has external pin 0 connected to LLWU device. */ 516 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 517 /* @brief Index of port of external pin. */ 518 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 519 /* @brief Number of external pin port on specified port. */ 520 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 521 /* @brief Has external pin 1 connected to LLWU device. */ 522 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 523 /* @brief Index of port of external pin. */ 524 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 525 /* @brief Number of external pin port on specified port. */ 526 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 527 /* @brief Has external pin 2 connected to LLWU device. */ 528 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 529 /* @brief Index of port of external pin. */ 530 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 531 /* @brief Number of external pin port on specified port. */ 532 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 533 /* @brief Has external pin 3 connected to LLWU device. */ 534 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 535 /* @brief Index of port of external pin. */ 536 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 537 /* @brief Number of external pin port on specified port. */ 538 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 539 /* @brief Has external pin 4 connected to LLWU device. */ 540 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 541 /* @brief Index of port of external pin. */ 542 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 543 /* @brief Number of external pin port on specified port. */ 544 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 545 /* @brief Has external pin 5 connected to LLWU device. */ 546 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (0) 547 /* @brief Index of port of external pin. */ 548 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (0) 549 /* @brief Number of external pin port on specified port. */ 550 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 551 /* @brief Has external pin 6 connected to LLWU device. */ 552 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 553 /* @brief Index of port of external pin. */ 554 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 555 /* @brief Number of external pin port on specified port. */ 556 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 557 /* @brief Has external pin 7 connected to LLWU device. */ 558 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 559 /* @brief Index of port of external pin. */ 560 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 561 /* @brief Number of external pin port on specified port. */ 562 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 563 /* @brief Has external pin 8 connected to LLWU device. */ 564 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 565 /* @brief Index of port of external pin. */ 566 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 567 /* @brief Number of external pin port on specified port. */ 568 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 569 /* @brief Has external pin 9 connected to LLWU device. */ 570 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 571 /* @brief Index of port of external pin. */ 572 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 573 /* @brief Number of external pin port on specified port. */ 574 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 575 /* @brief Has external pin 10 connected to LLWU device. */ 576 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 577 /* @brief Index of port of external pin. */ 578 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 579 /* @brief Number of external pin port on specified port. */ 580 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 581 /* @brief Has external pin 11 connected to LLWU device. */ 582 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 583 /* @brief Index of port of external pin. */ 584 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 585 /* @brief Number of external pin port on specified port. */ 586 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 587 /* @brief Has external pin 12 connected to LLWU device. */ 588 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 589 /* @brief Index of port of external pin. */ 590 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 591 /* @brief Number of external pin port on specified port. */ 592 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 593 /* @brief Has external pin 13 connected to LLWU device. */ 594 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 595 /* @brief Index of port of external pin. */ 596 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 597 /* @brief Number of external pin port on specified port. */ 598 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 599 /* @brief Has external pin 14 connected to LLWU device. */ 600 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 601 /* @brief Index of port of external pin. */ 602 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 603 /* @brief Number of external pin port on specified port. */ 604 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 605 /* @brief Has external pin 15 connected to LLWU device. */ 606 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 607 /* @brief Index of port of external pin. */ 608 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 609 /* @brief Number of external pin port on specified port. */ 610 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 611 /* @brief Has external pin 16 connected to LLWU device. */ 612 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 613 /* @brief Index of port of external pin. */ 614 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 615 /* @brief Number of external pin port on specified port. */ 616 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 617 /* @brief Has external pin 17 connected to LLWU device. */ 618 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 619 /* @brief Index of port of external pin. */ 620 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 621 /* @brief Number of external pin port on specified port. */ 622 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 623 /* @brief Has external pin 18 connected to LLWU device. */ 624 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 625 /* @brief Index of port of external pin. */ 626 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 627 /* @brief Number of external pin port on specified port. */ 628 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 629 /* @brief Has external pin 19 connected to LLWU device. */ 630 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 631 /* @brief Index of port of external pin. */ 632 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 633 /* @brief Number of external pin port on specified port. */ 634 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 635 /* @brief Has external pin 20 connected to LLWU device. */ 636 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 637 /* @brief Index of port of external pin. */ 638 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 639 /* @brief Number of external pin port on specified port. */ 640 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 641 /* @brief Has external pin 21 connected to LLWU device. */ 642 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 643 /* @brief Index of port of external pin. */ 644 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 645 /* @brief Number of external pin port on specified port. */ 646 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 647 /* @brief Has external pin 22 connected to LLWU device. */ 648 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 649 /* @brief Index of port of external pin. */ 650 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 651 /* @brief Number of external pin port on specified port. */ 652 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 653 /* @brief Has external pin 23 connected to LLWU device. */ 654 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 655 /* @brief Index of port of external pin. */ 656 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 657 /* @brief Number of external pin port on specified port. */ 658 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 659 /* @brief Has external pin 24 connected to LLWU device. */ 660 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 661 /* @brief Index of port of external pin. */ 662 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 663 /* @brief Number of external pin port on specified port. */ 664 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 665 /* @brief Has external pin 25 connected to LLWU device. */ 666 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 667 /* @brief Index of port of external pin. */ 668 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 669 /* @brief Number of external pin port on specified port. */ 670 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 671 /* @brief Has external pin 26 connected to LLWU device. */ 672 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 673 /* @brief Index of port of external pin. */ 674 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 675 /* @brief Number of external pin port on specified port. */ 676 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 677 /* @brief Has external pin 27 connected to LLWU device. */ 678 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 679 /* @brief Index of port of external pin. */ 680 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 681 /* @brief Number of external pin port on specified port. */ 682 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 683 /* @brief Has external pin 28 connected to LLWU device. */ 684 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 685 /* @brief Index of port of external pin. */ 686 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 687 /* @brief Number of external pin port on specified port. */ 688 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 689 /* @brief Has external pin 29 connected to LLWU device. */ 690 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 691 /* @brief Index of port of external pin. */ 692 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 693 /* @brief Number of external pin port on specified port. */ 694 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 695 /* @brief Has external pin 30 connected to LLWU device. */ 696 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 697 /* @brief Index of port of external pin. */ 698 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 699 /* @brief Number of external pin port on specified port. */ 700 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 701 /* @brief Has external pin 31 connected to LLWU device. */ 702 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 703 /* @brief Index of port of external pin. */ 704 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 705 /* @brief Number of external pin port on specified port. */ 706 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 707 /* @brief Has internal module 0 connected to LLWU device. */ 708 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 709 /* @brief Has internal module 1 connected to LLWU device. */ 710 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 711 /* @brief Has internal module 2 connected to LLWU device. */ 712 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 713 /* @brief Has internal module 3 connected to LLWU device. */ 714 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 715 /* @brief Has internal module 4 connected to LLWU device. */ 716 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 717 /* @brief Has internal module 5 connected to LLWU device. */ 718 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 719 /* @brief Has internal module 6 connected to LLWU device. */ 720 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 721 /* @brief Has internal module 7 connected to LLWU device. */ 722 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 723 /* @brief Has Version ID Register (LLWU_VERID). */ 724 #define FSL_FEATURE_LLWU_HAS_VERID (0) 725 /* @brief Has Parameter Register (LLWU_PARAM). */ 726 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 727 /* @brief Width of registers of the LLWU. */ 728 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 729 /* @brief Has DMA Enable register (LLWU_DE). */ 730 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 731 732 /* LPTMR module features */ 733 734 /* @brief Has shared interrupt handler with another LPTMR module. */ 735 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 736 /* @brief Whether LPTMR counter is 32 bits width. */ 737 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 738 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 739 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 740 741 /* MCG module features */ 742 743 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 744 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 745 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 746 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 747 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 748 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 749 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 750 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 751 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 752 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 753 /* @brief The PLL clock is divided by 2 before VCO divider. */ 754 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 755 /* @brief FRDIV supports 1280. */ 756 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 757 /* @brief FRDIV supports 1536. */ 758 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 759 /* @brief MCGFFCLK divider. */ 760 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 761 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 762 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 763 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 764 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 765 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 766 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 767 /* @brief Has 48MHz internal oscillator. */ 768 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 769 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 770 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 771 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 772 #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) 773 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 774 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 775 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 776 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 777 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 778 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 779 /* @brief TBD */ 780 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 781 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 782 #define FSL_FEATURE_MCG_HAS_PLL (1) 783 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 784 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 785 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 786 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 787 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 788 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 789 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 790 #define FSL_FEATURE_MCG_HAS_FLL (1) 791 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 792 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 793 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 794 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 795 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 796 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 797 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 798 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 799 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 800 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 801 /* @brief Has external clock monitor (register bit C6[CME]). */ 802 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 803 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 804 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 805 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 806 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 807 /* @brief Has PEI mode or PBI mode. */ 808 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 809 /* @brief Reset clock mode is BLPI. */ 810 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 811 812 /* interrupt module features */ 813 814 /* @brief Lowest interrupt request number. */ 815 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 816 /* @brief Highest interrupt request number. */ 817 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (64) 818 819 /* OSC module features */ 820 821 /* @brief Has OSC1 external oscillator. */ 822 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 823 /* @brief Has OSC0 external oscillator. */ 824 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 825 /* @brief Has OSC external oscillator (without index). */ 826 #define FSL_FEATURE_OSC_HAS_OSC (1) 827 /* @brief Number of OSC external oscillators. */ 828 #define FSL_FEATURE_OSC_OSC_COUNT (1) 829 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 830 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 831 832 /* PDB module features */ 833 834 /* @brief Has DAC support. */ 835 #define FSL_FEATURE_PDB_HAS_DAC (1) 836 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 837 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 838 /* @brief PDB channel number). */ 839 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 840 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 841 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 842 /* @brief DAC interval trigger number). */ 843 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 844 /* @brief Pulse out number). */ 845 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 846 847 /* PIT module features */ 848 849 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 850 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 851 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 852 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 853 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 854 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 855 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 856 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 857 /* @brief Has timer enable control. */ 858 #define FSL_FEATURE_PIT_HAS_MDIS (1) 859 860 /* PMC module features */ 861 862 /* @brief Has Bandgap Enable In VLPx Operation support. */ 863 #define FSL_FEATURE_PMC_HAS_BGEN (1) 864 /* @brief Has Bandgap Buffer Enable. */ 865 #define FSL_FEATURE_PMC_HAS_BGBE (1) 866 /* @brief Has Bandgap Buffer Drive Select. */ 867 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 868 /* @brief Has Low-Voltage Detect Voltage Select support. */ 869 #define FSL_FEATURE_PMC_HAS_LVDV (1) 870 /* @brief Has Low-Voltage Warning Voltage Select support. */ 871 #define FSL_FEATURE_PMC_HAS_LVWV (1) 872 /* @brief Has LPO. */ 873 #define FSL_FEATURE_PMC_HAS_LPO (0) 874 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 875 #define FSL_FEATURE_PMC_HAS_VLPO (0) 876 /* @brief Has acknowledge isolation support. */ 877 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 878 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 879 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 880 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 881 #define FSL_FEATURE_PMC_HAS_REGONS (1) 882 /* @brief Has PMC_HVDSC1. */ 883 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 884 /* @brief Has PMC_PARAM. */ 885 #define FSL_FEATURE_PMC_HAS_PARAM (0) 886 /* @brief Has PMC_VERID. */ 887 #define FSL_FEATURE_PMC_HAS_VERID (0) 888 889 /* PORT module features */ 890 891 /* @brief Has control lock (register bit PCR[LK]). */ 892 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 893 /* @brief Has open drain control (register bit PCR[ODE]). */ 894 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 895 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 896 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 897 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 898 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 899 /* @brief Has pull resistor selection available. */ 900 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 901 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 902 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 903 /* @brief Has slew rate control (register bit PCR[SRE]). */ 904 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 905 /* @brief Has passive filter (register bit field PCR[PFE]). */ 906 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 907 /* @brief Has drive strength control (register bit PCR[DSE]). */ 908 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 909 /* @brief Has separate drive strength register (HDRVE). */ 910 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 911 /* @brief Has glitch filter (register IOFLT). */ 912 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 913 /* @brief Defines width of PCR[MUX] field. */ 914 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 915 /* @brief Has dedicated interrupt vector. */ 916 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 917 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 918 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 919 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 920 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 921 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 922 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 923 924 /* RCM module features */ 925 926 /* @brief Has Loss-of-Lock Reset support. */ 927 #define FSL_FEATURE_RCM_HAS_LOL (1) 928 /* @brief Has Loss-of-Clock Reset support. */ 929 #define FSL_FEATURE_RCM_HAS_LOC (1) 930 /* @brief Has JTAG generated Reset support. */ 931 #define FSL_FEATURE_RCM_HAS_JTAG (1) 932 /* @brief Has EzPort generated Reset support. */ 933 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 934 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 935 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 936 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 937 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 938 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 939 #define FSL_FEATURE_RCM_HAS_SSRS (0) 940 /* @brief Has Version ID Register (RCM_VERID). */ 941 #define FSL_FEATURE_RCM_HAS_VERID (0) 942 /* @brief Has Parameter Register (RCM_PARAM). */ 943 #define FSL_FEATURE_RCM_HAS_PARAM (0) 944 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 945 #define FSL_FEATURE_RCM_HAS_SRIE (0) 946 /* @brief Width of registers of the RCM. */ 947 #define FSL_FEATURE_RCM_REG_WIDTH (8) 948 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 949 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 950 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 951 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 952 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 953 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 954 955 /* RTC module features */ 956 957 /* @brief Has wakeup pin. */ 958 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 959 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 960 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 961 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 962 #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) 963 /* @brief Has read/write access control (registers WAR and RAR). */ 964 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 965 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 966 #define FSL_FEATURE_RTC_HAS_SECURITY (1) 967 /* @brief Has RTC_CLKIN available. */ 968 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 969 /* @brief Has prescaler adjust for LPO. */ 970 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 971 /* @brief Has Clock Pin Enable field. */ 972 #define FSL_FEATURE_RTC_HAS_CPE (0) 973 /* @brief Has Timer Seconds Interrupt Configuration field. */ 974 #define FSL_FEATURE_RTC_HAS_TSIC (0) 975 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 976 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 977 /* @brief Has Tamper Interrupt Register (register TIR). */ 978 #define FSL_FEATURE_RTC_HAS_TIR (0) 979 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 980 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 981 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 982 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 983 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 984 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 985 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 986 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 987 /* @brief Has Tamper Detect Register (register TDR). */ 988 #define FSL_FEATURE_RTC_HAS_TDR (0) 989 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 990 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 991 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 992 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 993 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 994 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 995 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 996 #define FSL_FEATURE_RTC_HAS_TTSR (1) 997 /* @brief Has Pin Configuration Register (register PCR). */ 998 #define FSL_FEATURE_RTC_HAS_PCR (0) 999 1000 /* SIM module features */ 1001 1002 /* @brief Has USB FS divider. */ 1003 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1004 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1005 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) 1006 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1007 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1008 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1009 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1010 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1011 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1012 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1013 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1014 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1015 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1016 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1017 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1018 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1019 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1020 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1021 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) 1022 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1023 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1024 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1025 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1026 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1027 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1028 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1029 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1030 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1031 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1032 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1033 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1034 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1035 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1036 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1037 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1038 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1039 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1040 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1041 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1042 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1043 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1044 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1045 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1046 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1047 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1048 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1049 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1050 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1051 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1052 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1053 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1054 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1055 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1056 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1057 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1058 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1059 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1060 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1061 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1062 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1063 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1064 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1065 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1066 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1067 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1068 /* @brief Has FTM module(s) configuration. */ 1069 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1070 /* @brief Number of FTM modules. */ 1071 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) 1072 /* @brief Number of FTM triggers with selectable source. */ 1073 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1074 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1075 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1076 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1077 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1078 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1079 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1080 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1081 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1082 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1083 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1084 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1085 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1086 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1087 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1088 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1089 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1090 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1091 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1092 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1093 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1094 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1095 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1096 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1097 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1098 /* @brief Has TPM module(s) configuration. */ 1099 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1100 /* @brief The highest TPM module index. */ 1101 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1102 /* @brief Has TPM module with index 0. */ 1103 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1104 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1105 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1106 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1107 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1108 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1109 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1110 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1111 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1112 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1113 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1114 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1115 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1116 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1117 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1118 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1119 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1120 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1121 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1122 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1123 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1124 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1125 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1126 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1127 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1128 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1129 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1130 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1131 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1132 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1133 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1134 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1135 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1136 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1137 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1138 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1139 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1140 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1141 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1142 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1143 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1144 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1145 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1146 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1147 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1148 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1149 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1150 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1151 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1152 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1153 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1154 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1155 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1156 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1157 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1158 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1159 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1160 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1161 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1162 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1163 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1164 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1165 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1166 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1167 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1168 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1169 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1170 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1171 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1172 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1173 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1174 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1175 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1176 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1177 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1178 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1179 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1180 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1181 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1182 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1183 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1184 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1185 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1186 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1187 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) 1188 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1189 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1190 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1191 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1192 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1193 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1194 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1195 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1196 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1197 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1198 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1199 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1200 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1201 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1202 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1203 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1204 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1205 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) 1206 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1207 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) 1208 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1209 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1210 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1211 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1212 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1213 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1214 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1215 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1216 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1217 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1218 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1219 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) 1220 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1221 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) 1222 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1223 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) 1224 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1225 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1226 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1227 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1228 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1229 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1230 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1231 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1232 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1233 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) 1234 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1235 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) 1236 /* @brief Has miscellanious control register (register MCR). */ 1237 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1238 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1239 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1240 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1241 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1242 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1243 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1244 /* @brief Has UIDH registers. */ 1245 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1246 /* @brief Has UIDM registers. */ 1247 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1248 1249 /* SMC module features */ 1250 1251 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1252 #define FSL_FEATURE_SMC_HAS_PSTOPO (0) 1253 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1254 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1255 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1256 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1257 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1258 #define FSL_FEATURE_SMC_HAS_LPWUI (1) 1259 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1260 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1261 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1262 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) 1263 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1264 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1265 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1266 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1267 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1268 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1269 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1270 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1271 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1272 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1273 /* @brief Has stop submode. */ 1274 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1275 /* @brief Has stop submode 0(VLLS0). */ 1276 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1277 /* @brief Has stop submode 1(VLLS1). */ 1278 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1279 /* @brief Has stop submode 2(VLLS2). */ 1280 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1281 /* @brief Has SMC_PARAM. */ 1282 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1283 /* @brief Has SMC_VERID. */ 1284 #define FSL_FEATURE_SMC_HAS_VERID (0) 1285 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1286 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1287 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1288 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1289 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1290 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1291 /* @brief Width of SMC registers. */ 1292 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1293 1294 /* DSPI module features */ 1295 1296 /* @brief Receive/transmit FIFO size in number of items. */ 1297 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1298 /* @brief Maximum transfer data width in bits. */ 1299 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1300 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1301 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (5) 1302 /* @brief Number of chip select pins. */ 1303 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) 1304 /* @brief Number of CTAR registers. */ 1305 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1306 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1307 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 1308 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1309 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1310 /* @brief Has 16-bit data transfer support. */ 1311 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1312 /* @brief Has separate DMA RX and TX requests. */ 1313 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1314 1315 /* SysTick module features */ 1316 1317 /* @brief Systick has external reference clock. */ 1318 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1319 /* @brief Systick external reference clock is core clock divided by this value. */ 1320 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1321 1322 /* UART module features */ 1323 1324 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1325 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1326 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1327 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1328 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1329 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1330 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1331 #define FSL_FEATURE_UART_HAS_FIFO (1) 1332 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1333 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1334 /* @brief Infrared (modulation) is supported. */ 1335 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1336 /* @brief 2 bits long stop bit is available. */ 1337 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1338 /* @brief If 10-bit mode is supported. */ 1339 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1340 /* @brief Baud rate fine adjustment is available. */ 1341 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1342 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1343 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1344 /* @brief Baud rate oversampling is available. */ 1345 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1346 /* @brief Baud rate oversampling is available. */ 1347 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1348 /* @brief Peripheral type. */ 1349 #define FSL_FEATURE_UART_IS_SCI (0) 1350 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1351 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1352 (((x) == UART0) ? (8) : \ 1353 (((x) == UART1) ? (1) : \ 1354 (((x) == UART2) ? (1) : (-1)))) 1355 /* @brief Supports two match addresses to filter incoming frames. */ 1356 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1357 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1358 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1359 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1360 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1361 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1362 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1363 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1364 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1365 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1366 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1367 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1368 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1369 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1370 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1371 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1372 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1373 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1374 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1375 /* @brief Has separate DMA RX and TX requests. */ 1376 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1377 1378 /* USB module features */ 1379 1380 /* @brief KHCI module instance count */ 1381 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1382 /* @brief HOST mode enabled */ 1383 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 1384 /* @brief OTG mode enabled */ 1385 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 1386 /* @brief Size of the USB dedicated RAM */ 1387 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 1388 /* @brief Has KEEP_ALIVE_CTRL register */ 1389 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1390 /* @brief Has the Dynamic SOF threshold compare support */ 1391 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 1392 /* @brief Has the VBUS detect support */ 1393 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 1394 /* @brief Has the IRC48M module clock support */ 1395 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) 1396 /* @brief Number of endpoints supported */ 1397 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1398 /* @brief Has STALL_IL/OL_DIS registers */ 1399 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 1400 /* @brief Has STALL_IH/OH_DIS registers */ 1401 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 1402 1403 /* WDOG module features */ 1404 1405 /* @brief Watchdog is available. */ 1406 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1407 /* @brief Has Wait mode support. */ 1408 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1409 1410 #endif /* _MKW24D5_FEATURES_H_ */ 1411 1412
