1 /*
2 ** ###################################################################
3 **     Processors:          MKW21Z256VHT4
4 **                          MKW21Z512VHT4
5 **
6 **     Compilers:           Keil ARM C/C++ Compiler
7 **                          GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          MCUXpresso Compiler
10 **
11 **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
12 **     Version:             rev. 1.0, 2015-09-23
13 **     Build:               b170112
14 **
15 **     Abstract:
16 **         Provides a system configuration function and a global variable that
17 **         contains the system frequency. It configures the device and initializes
18 **         the oscillator (PLL) that is part of the microcontroller device.
19 **
20 **     Copyright (c) 2016 Freescale Semiconductor, Inc.
21 **     Copyright 2016 - 2017 NXP
22 **     Redistribution and use in source and binary forms, with or without modification,
23 **     are permitted provided that the following conditions are met:
24 **
25 **     o Redistributions of source code must retain the above copyright notice, this list
26 **       of conditions and the following disclaimer.
27 **
28 **     o Redistributions in binary form must reproduce the above copyright notice, this
29 **       list of conditions and the following disclaimer in the documentation and/or
30 **       other materials provided with the distribution.
31 **
32 **     o Neither the name of the copyright holder nor the names of its
33 **       contributors may be used to endorse or promote products derived from this
34 **       software without specific prior written permission.
35 **
36 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
37 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
38 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
39 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
40 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
42 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
43 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
45 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 **
47 **     http:                 www.nxp.com
48 **     mail:                 support@nxp.com
49 **
50 **     Revisions:
51 **     - rev. 1.0 (2015-09-23)
52 **         Initial version.
53 **
54 ** ###################################################################
55 */
56 
57 /*!
58  * @file MKW21Z4
59  * @version 1.0
60  * @date 2015-09-23
61  * @brief Device specific configuration file for MKW21Z4 (implementation file)
62  *
63  * Provides a system configuration function and a global variable that contains
64  * the system frequency. It configures the device and initializes the oscillator
65  * (PLL) that is part of the microcontroller device.
66  */
67 
68 #include <stdint.h>
69 #include "fsl_device_registers.h"
70 
71 
72 
73 /* ----------------------------------------------------------------------------
74    -- Core clock
75    ---------------------------------------------------------------------------- */
76 
77 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
78 
79 /* ----------------------------------------------------------------------------
80    -- SystemInit()
81    ---------------------------------------------------------------------------- */
82 
SystemInit(void)83 void SystemInit (void) {
84 
85 #if (DISABLE_WDOG)
86   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
87   SIM->COPC = (uint32_t)0x00u;
88 #endif /* (DISABLE_WDOG) */
89 
90 }
91 
92 /* ----------------------------------------------------------------------------
93    -- SystemCoreClockUpdate()
94    ---------------------------------------------------------------------------- */
95 
SystemCoreClockUpdate(void)96 void SystemCoreClockUpdate (void) {
97 
98   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
99   uint16_t Divider;
100 
101   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
102     /* FLL is selected */
103     if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
104       /* External reference clock is selected */
105       if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
106         MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
107       } else {
108         MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
109       }
110       if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
111         switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
112         case 0x38U:
113           Divider = 1536U;
114           break;
115         case 0x30U:
116           Divider = 1280U;
117           break;
118         default:
119           Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
120           break;
121         }
122       } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
123         Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
124       }
125       MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
126     } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
127       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
128     } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
129     /* Select correct multiplier to calculate the MCG output clock  */
130     switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
131       case 0x00U:
132         MCGOUTClock *= 640U;
133         break;
134       case 0x20U:
135         MCGOUTClock *= 1280U;
136         break;
137       case 0x40U:
138         MCGOUTClock *= 1920U;
139         break;
140       case 0x60U:
141         MCGOUTClock *= 2560U;
142         break;
143       case 0x80U:
144         MCGOUTClock *= 732U;
145         break;
146       case 0xA0U:
147         MCGOUTClock *= 1464U;
148         break;
149       case 0xC0U:
150         MCGOUTClock *= 2197U;
151         break;
152       case 0xE0U:
153         MCGOUTClock *= 2929U;
154         break;
155       default:
156         break;
157     }
158   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
159     /* Internal reference clock is selected */
160     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
161       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
162     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
163       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
164       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
165     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
166   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
167     /* External reference clock is selected */
168     if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
169       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
170     } else {
171       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
172     }
173   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
174     /* Reserved value */
175     return;
176   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
177   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
178 
179 }
180