1 /* 2 ** ################################################################### 3 ** Version: rev. 1.12, 2015-06-08 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2013-11-01) 20 ** Initial version. 21 ** - rev. 1.1 (2013-12-20) 22 ** Update according to reference manual rev. 0.6, 23 ** - rev. 1.2 (2014-01-13) 24 ** Update according to reference manual rev. 0.61, 25 ** - rev. 1.3 (2014-01-30) 26 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 27 ** - rev. 1.4 (2014-02-10) 28 ** The declaration of clock configurations has been moved to separate header file system_MKV31F51212.h 29 ** - rev. 1.5 (2014-05-06) 30 ** Update according to reference manual rev. 1.0, 31 ** Update of system and startup files. 32 ** Module access macro module_BASES replaced by module_BASE_PTRS. 33 ** - rev. 1.6 (2014-08-28) 34 ** Update of system files - default clock configuration changed. 35 ** Update of startup files - possibility to override DefaultISR added. 36 ** - rev. 1.7 (2014-10-14) 37 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. 38 ** - rev. 1.8 (2015-01-21) 39 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 40 ** - rev. 1.9 (2015-02-19) 41 ** Renamed interrupt vector LLW to LLWU. 42 ** - rev. 1.10 (2015-05-19) 43 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 44 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 45 ** Added features for PORT and PDB. 46 ** - rev. 1.11 (2015-05-25) 47 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 48 ** - rev. 1.12 (2015-06-08) 49 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 50 ** 51 ** ################################################################### 52 */ 53 54 #ifndef _MKV31F51212_FEATURES_H_ 55 #define _MKV31F51212_FEATURES_H_ 56 57 /* SOC module features */ 58 59 /* @brief ADC16 availability on the SoC. */ 60 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 61 /* @brief CMP availability on the SoC. */ 62 #define FSL_FEATURE_SOC_CMP_COUNT (2) 63 /* @brief CRC availability on the SoC. */ 64 #define FSL_FEATURE_SOC_CRC_COUNT (1) 65 /* @brief DAC availability on the SoC. */ 66 #define FSL_FEATURE_SOC_DAC_COUNT (2) 67 /* @brief EDMA availability on the SoC. */ 68 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 69 /* @brief DMAMUX availability on the SoC. */ 70 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 71 /* @brief DSPI availability on the SoC. */ 72 #define FSL_FEATURE_SOC_DSPI_COUNT (2) 73 /* @brief EWM availability on the SoC. */ 74 #define FSL_FEATURE_SOC_EWM_COUNT (1) 75 /* @brief FB availability on the SoC. */ 76 #define FSL_FEATURE_SOC_FB_COUNT (1) 77 /* @brief FMC availability on the SoC. */ 78 #define FSL_FEATURE_SOC_FMC_COUNT (1) 79 /* @brief FTFA availability on the SoC. */ 80 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 81 /* @brief FTM availability on the SoC. */ 82 #define FSL_FEATURE_SOC_FTM_COUNT (4) 83 /* @brief GPIO availability on the SoC. */ 84 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 85 /* @brief I2C availability on the SoC. */ 86 #define FSL_FEATURE_SOC_I2C_COUNT (2) 87 /* @brief LLWU availability on the SoC. */ 88 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 89 /* @brief LPTMR availability on the SoC. */ 90 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 91 /* @brief LPUART availability on the SoC. */ 92 #define FSL_FEATURE_SOC_LPUART_COUNT (1) 93 /* @brief MCG availability on the SoC. */ 94 #define FSL_FEATURE_SOC_MCG_COUNT (1) 95 /* @brief MCM availability on the SoC. */ 96 #define FSL_FEATURE_SOC_MCM_COUNT (1) 97 /* @brief OSC availability on the SoC. */ 98 #define FSL_FEATURE_SOC_OSC_COUNT (1) 99 /* @brief PDB availability on the SoC. */ 100 #define FSL_FEATURE_SOC_PDB_COUNT (1) 101 /* @brief PIT availability on the SoC. */ 102 #define FSL_FEATURE_SOC_PIT_COUNT (1) 103 /* @brief PMC availability on the SoC. */ 104 #define FSL_FEATURE_SOC_PMC_COUNT (1) 105 /* @brief PORT availability on the SoC. */ 106 #define FSL_FEATURE_SOC_PORT_COUNT (5) 107 /* @brief RCM availability on the SoC. */ 108 #define FSL_FEATURE_SOC_RCM_COUNT (1) 109 /* @brief RFSYS availability on the SoC. */ 110 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 111 /* @brief RFVBAT availability on the SoC. */ 112 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 113 /* @brief RNG availability on the SoC. */ 114 #define FSL_FEATURE_SOC_RNG_COUNT (1) 115 /* @brief SIM availability on the SoC. */ 116 #define FSL_FEATURE_SOC_SIM_COUNT (1) 117 /* @brief SMC availability on the SoC. */ 118 #define FSL_FEATURE_SOC_SMC_COUNT (1) 119 /* @brief UART availability on the SoC. */ 120 #define FSL_FEATURE_SOC_UART_COUNT (3) 121 /* @brief VREF availability on the SoC. */ 122 #define FSL_FEATURE_SOC_VREF_COUNT (1) 123 /* @brief WDOG availability on the SoC. */ 124 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 125 126 /* ADC16 module features */ 127 128 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 129 #define FSL_FEATURE_ADC16_HAS_PGA (0) 130 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 131 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 132 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 133 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 134 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 135 #define FSL_FEATURE_ADC16_HAS_DMA (1) 136 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 137 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 138 /* @brief Has FIFO (bit SC4[AFDEP]). */ 139 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 140 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 141 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 142 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 143 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 144 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 145 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 146 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 147 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 148 /* @brief Has HW averaging (bit SC3[AVGE]). */ 149 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 150 /* @brief Has offset correction (register OFS). */ 151 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 152 /* @brief Maximum ADC resolution. */ 153 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 154 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 155 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 156 157 /* CMP module features */ 158 159 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 160 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 161 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 162 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 163 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 164 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 165 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 166 #define FSL_FEATURE_CMP_HAS_DMA (1) 167 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 168 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 169 /* @brief Has DAC Test function in CMP (register DACTEST). */ 170 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 171 172 /* CRC module features */ 173 174 /* @brief Has data register with name CRC */ 175 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 176 177 /* DAC module features */ 178 179 /* @brief Define the size of hardware buffer */ 180 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 181 /* @brief Define whether the buffer supports watermark event detection or not. */ 182 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 183 /* @brief Define whether the buffer supports watermark selection detection or not. */ 184 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 185 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 186 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 187 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 188 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 189 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 190 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 191 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 192 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 193 /* @brief Define whether FIFO buffer mode is available or not. */ 194 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 195 /* @brief Define whether swing buffer mode is available or not.. */ 196 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 197 198 /* EDMA module features */ 199 200 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 201 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 202 /* @brief Total number of DMA channels on all modules. */ 203 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) 204 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 205 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 206 /* @brief Has DMA_Error interrupt vector. */ 207 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 208 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 209 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) 210 /* @brief Channel IRQ entry shared offset. */ 211 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 212 /* @brief If 8 bytes transfer supported. */ 213 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 214 /* @brief If 16 bytes transfer supported. */ 215 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 216 217 /* DMAMUX module features */ 218 219 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 220 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 221 /* @brief Total number of DMA channels on all modules. */ 222 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16) 223 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 224 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 225 /* @brief Register CHCFGn width. */ 226 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 227 228 /* EWM module features */ 229 230 /* @brief Has clock select (register CLKCTRL). */ 231 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 232 /* @brief Has clock prescaler (register CLKPRESCALER). */ 233 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 234 235 /* FLEXBUS module features */ 236 237 /* No feature definitions */ 238 239 /* FLASH module features */ 240 241 /* @brief Is of type FTFA. */ 242 #define FSL_FEATURE_FLASH_IS_FTFA (1) 243 /* @brief Is of type FTFE. */ 244 #define FSL_FEATURE_FLASH_IS_FTFE (0) 245 /* @brief Is of type FTFL. */ 246 #define FSL_FEATURE_FLASH_IS_FTFL (0) 247 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 248 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 249 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 250 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 251 /* @brief Has EEPROM region protection (register FEPROT). */ 252 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 253 /* @brief Has data flash region protection (register FDPROT). */ 254 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 255 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 256 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 257 /* @brief Has flash cache control in FMC module. */ 258 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 259 /* @brief Has flash cache control in MCM module. */ 260 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 261 /* @brief Has flash cache control in MSCM module. */ 262 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 263 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 264 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 265 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 266 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 267 /* @brief P-Flash start address. */ 268 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 269 /* @brief P-Flash block count. */ 270 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 271 /* @brief P-Flash block size. */ 272 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 273 /* @brief P-Flash sector size. */ 274 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 275 /* @brief P-Flash write unit size. */ 276 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 277 /* @brief P-Flash data path width. */ 278 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 279 /* @brief P-Flash block swap feature. */ 280 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 281 /* @brief P-Flash protection region count. */ 282 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 283 /* @brief Has FlexNVM memory. */ 284 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 285 /* @brief Has FlexNVM alias. */ 286 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 287 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 288 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 289 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 290 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 291 /* @brief FlexNVM block count. */ 292 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 293 /* @brief FlexNVM block size. */ 294 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 295 /* @brief FlexNVM sector size. */ 296 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 297 /* @brief FlexNVM write unit size. */ 298 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 299 /* @brief FlexNVM data path width. */ 300 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 301 /* @brief Has FlexRAM memory. */ 302 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 303 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 304 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 305 /* @brief FlexRAM size. */ 306 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 307 /* @brief Has 0x00 Read 1s Block command. */ 308 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 309 /* @brief Has 0x01 Read 1s Section command. */ 310 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 311 /* @brief Has 0x02 Program Check command. */ 312 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 313 /* @brief Has 0x03 Read Resource command. */ 314 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 315 /* @brief Has 0x06 Program Longword command. */ 316 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 317 /* @brief Has 0x07 Program Phrase command. */ 318 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 319 /* @brief Has 0x08 Erase Flash Block command. */ 320 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 321 /* @brief Has 0x09 Erase Flash Sector command. */ 322 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 323 /* @brief Has 0x0B Program Section command. */ 324 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 325 /* @brief Has 0x40 Read 1s All Blocks command. */ 326 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 327 /* @brief Has 0x41 Read Once command. */ 328 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 329 /* @brief Has 0x43 Program Once command. */ 330 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 331 /* @brief Has 0x44 Erase All Blocks command. */ 332 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 333 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 334 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 335 /* @brief Has 0x46 Swap Control command. */ 336 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 337 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 338 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 339 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 340 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 341 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 342 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 343 /* @brief Has 0x80 Program Partition command. */ 344 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 345 /* @brief Has 0x81 Set FlexRAM Function command. */ 346 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 347 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 348 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 349 /* @brief P-Flash Erase sector command address alignment. */ 350 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 351 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 352 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 353 /* @brief P-Flash Read resource command address alignment. */ 354 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 355 /* @brief P-Flash Program check command address alignment. */ 356 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 357 /* @brief P-Flash Program check command address alignment. */ 358 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 359 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 360 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 361 /* @brief FlexNVM Erase sector command address alignment. */ 362 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 363 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 364 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 365 /* @brief FlexNVM Read resource command address alignment. */ 366 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 367 /* @brief FlexNVM Program check command address alignment. */ 368 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 369 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 370 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 371 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 372 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 373 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 374 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 375 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 376 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 377 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 378 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 379 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 381 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 383 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 385 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 387 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 389 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 391 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 392 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 393 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 394 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 395 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 396 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 397 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 398 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 399 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 400 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 401 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 402 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 403 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 404 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 405 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 406 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 407 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 408 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 409 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 410 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 411 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 412 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 413 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 414 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 415 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 416 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 417 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 418 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 419 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 420 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 421 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 422 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 423 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 424 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 425 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 426 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 427 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 428 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 429 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 430 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 431 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 432 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 433 434 /* FTM module features */ 435 436 /* @brief Number of channels. */ 437 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 438 (((x) == FTM0) ? (8) : \ 439 (((x) == FTM1) ? (2) : \ 440 (((x) == FTM2) ? (2) : \ 441 (((x) == FTM3) ? (8) : (-1))))) 442 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 443 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 444 /* @brief Has extended deadtime value. */ 445 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 446 /* @brief Enable pwm output for the module. */ 447 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 448 /* @brief Has half-cycle reload for the module. */ 449 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 450 /* @brief Has reload interrupt. */ 451 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 452 /* @brief Has reload initialization trigger. */ 453 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 454 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 455 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 456 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 457 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 458 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 459 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 460 /* @brief Has no QDCTRL. */ 461 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 462 /* @brief If instance has only TPM function. */ 463 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 464 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 465 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0) 466 467 /* GPIO module features */ 468 469 /* @brief Has GPIO attribute checker register (GACR). */ 470 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 471 472 /* I2C module features */ 473 474 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 475 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 476 /* @brief Maximum supported baud rate in kilobit per second. */ 477 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 478 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 479 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 480 /* @brief Has DMA support (register bit C1[DMAEN]). */ 481 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 482 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 483 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 484 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 485 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 486 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 487 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 488 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 489 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 490 /* @brief Has control of the drive capability of the I2C pins. */ 491 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 492 /* @brief Has double buffering support (register S2). */ 493 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 494 /* @brief Has double buffer enable. */ 495 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 496 497 /* LLWU module features */ 498 499 #if defined(CPU_MKV31F512VLH12) 500 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 501 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 502 /* @brief Has pins 8-15 connected to LLWU device. */ 503 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 504 /* @brief Maximum number of internal modules connected to LLWU device. */ 505 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 506 /* @brief Number of digital filters. */ 507 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 508 /* @brief Has MF register. */ 509 #define FSL_FEATURE_LLWU_HAS_MF (0) 510 /* @brief Has PF register. */ 511 #define FSL_FEATURE_LLWU_HAS_PF (0) 512 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 513 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 514 /* @brief Has no internal module wakeup flag register. */ 515 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 516 /* @brief Has external pin 0 connected to LLWU device. */ 517 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 518 /* @brief Index of port of external pin. */ 519 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 520 /* @brief Number of external pin port on specified port. */ 521 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 522 /* @brief Has external pin 1 connected to LLWU device. */ 523 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 524 /* @brief Index of port of external pin. */ 525 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 526 /* @brief Number of external pin port on specified port. */ 527 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 528 /* @brief Has external pin 2 connected to LLWU device. */ 529 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 530 /* @brief Index of port of external pin. */ 531 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 532 /* @brief Number of external pin port on specified port. */ 533 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 534 /* @brief Has external pin 3 connected to LLWU device. */ 535 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 536 /* @brief Index of port of external pin. */ 537 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 538 /* @brief Number of external pin port on specified port. */ 539 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 540 /* @brief Has external pin 4 connected to LLWU device. */ 541 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 542 /* @brief Index of port of external pin. */ 543 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 544 /* @brief Number of external pin port on specified port. */ 545 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 546 /* @brief Has external pin 5 connected to LLWU device. */ 547 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 548 /* @brief Index of port of external pin. */ 549 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 550 /* @brief Number of external pin port on specified port. */ 551 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 552 /* @brief Has external pin 6 connected to LLWU device. */ 553 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 554 /* @brief Index of port of external pin. */ 555 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 556 /* @brief Number of external pin port on specified port. */ 557 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 558 /* @brief Has external pin 7 connected to LLWU device. */ 559 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 560 /* @brief Index of port of external pin. */ 561 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 562 /* @brief Number of external pin port on specified port. */ 563 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 564 /* @brief Has external pin 8 connected to LLWU device. */ 565 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 566 /* @brief Index of port of external pin. */ 567 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 568 /* @brief Number of external pin port on specified port. */ 569 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 570 /* @brief Has external pin 9 connected to LLWU device. */ 571 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 572 /* @brief Index of port of external pin. */ 573 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 574 /* @brief Number of external pin port on specified port. */ 575 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 576 /* @brief Has external pin 10 connected to LLWU device. */ 577 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 578 /* @brief Index of port of external pin. */ 579 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 580 /* @brief Number of external pin port on specified port. */ 581 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 582 /* @brief Has external pin 11 connected to LLWU device. */ 583 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 584 /* @brief Index of port of external pin. */ 585 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 586 /* @brief Number of external pin port on specified port. */ 587 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 588 /* @brief Has external pin 12 connected to LLWU device. */ 589 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 590 /* @brief Index of port of external pin. */ 591 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 592 /* @brief Number of external pin port on specified port. */ 593 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 594 /* @brief Has external pin 13 connected to LLWU device. */ 595 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 596 /* @brief Index of port of external pin. */ 597 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 598 /* @brief Number of external pin port on specified port. */ 599 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 600 /* @brief Has external pin 14 connected to LLWU device. */ 601 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 602 /* @brief Index of port of external pin. */ 603 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 604 /* @brief Number of external pin port on specified port. */ 605 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 606 /* @brief Has external pin 15 connected to LLWU device. */ 607 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 608 /* @brief Index of port of external pin. */ 609 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 610 /* @brief Number of external pin port on specified port. */ 611 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 612 /* @brief Has external pin 16 connected to LLWU device. */ 613 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 614 /* @brief Index of port of external pin. */ 615 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 616 /* @brief Number of external pin port on specified port. */ 617 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 618 /* @brief Has external pin 17 connected to LLWU device. */ 619 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 620 /* @brief Index of port of external pin. */ 621 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 622 /* @brief Number of external pin port on specified port. */ 623 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 624 /* @brief Has external pin 18 connected to LLWU device. */ 625 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 626 /* @brief Index of port of external pin. */ 627 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 628 /* @brief Number of external pin port on specified port. */ 629 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 630 /* @brief Has external pin 19 connected to LLWU device. */ 631 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 632 /* @brief Index of port of external pin. */ 633 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 634 /* @brief Number of external pin port on specified port. */ 635 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 636 /* @brief Has external pin 20 connected to LLWU device. */ 637 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 638 /* @brief Index of port of external pin. */ 639 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 640 /* @brief Number of external pin port on specified port. */ 641 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 642 /* @brief Has external pin 21 connected to LLWU device. */ 643 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 644 /* @brief Index of port of external pin. */ 645 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 646 /* @brief Number of external pin port on specified port. */ 647 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 648 /* @brief Has external pin 22 connected to LLWU device. */ 649 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 650 /* @brief Index of port of external pin. */ 651 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 652 /* @brief Number of external pin port on specified port. */ 653 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 654 /* @brief Has external pin 23 connected to LLWU device. */ 655 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 656 /* @brief Index of port of external pin. */ 657 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 658 /* @brief Number of external pin port on specified port. */ 659 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 660 /* @brief Has external pin 24 connected to LLWU device. */ 661 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 662 /* @brief Index of port of external pin. */ 663 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 664 /* @brief Number of external pin port on specified port. */ 665 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 666 /* @brief Has external pin 25 connected to LLWU device. */ 667 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 668 /* @brief Index of port of external pin. */ 669 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 670 /* @brief Number of external pin port on specified port. */ 671 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 672 /* @brief Has external pin 26 connected to LLWU device. */ 673 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 674 /* @brief Index of port of external pin. */ 675 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 676 /* @brief Number of external pin port on specified port. */ 677 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 678 /* @brief Has external pin 27 connected to LLWU device. */ 679 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 680 /* @brief Index of port of external pin. */ 681 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 682 /* @brief Number of external pin port on specified port. */ 683 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 684 /* @brief Has external pin 28 connected to LLWU device. */ 685 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 686 /* @brief Index of port of external pin. */ 687 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 688 /* @brief Number of external pin port on specified port. */ 689 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 690 /* @brief Has external pin 29 connected to LLWU device. */ 691 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 692 /* @brief Index of port of external pin. */ 693 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 694 /* @brief Number of external pin port on specified port. */ 695 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 696 /* @brief Has external pin 30 connected to LLWU device. */ 697 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 698 /* @brief Index of port of external pin. */ 699 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 700 /* @brief Number of external pin port on specified port. */ 701 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 702 /* @brief Has external pin 31 connected to LLWU device. */ 703 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 704 /* @brief Index of port of external pin. */ 705 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 706 /* @brief Number of external pin port on specified port. */ 707 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 708 /* @brief Has internal module 0 connected to LLWU device. */ 709 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 710 /* @brief Has internal module 1 connected to LLWU device. */ 711 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 712 /* @brief Has internal module 2 connected to LLWU device. */ 713 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 714 /* @brief Has internal module 3 connected to LLWU device. */ 715 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 716 /* @brief Has internal module 4 connected to LLWU device. */ 717 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 718 /* @brief Has internal module 5 connected to LLWU device. */ 719 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 720 /* @brief Has internal module 6 connected to LLWU device. */ 721 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 722 /* @brief Has internal module 7 connected to LLWU device. */ 723 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 724 /* @brief Has Version ID Register (LLWU_VERID). */ 725 #define FSL_FEATURE_LLWU_HAS_VERID (0) 726 /* @brief Has Parameter Register (LLWU_PARAM). */ 727 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 728 /* @brief Width of registers of the LLWU. */ 729 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 730 /* @brief Has DMA Enable register (LLWU_DE). */ 731 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 732 #elif defined(CPU_MKV31F512VLL12) 733 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 734 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 735 /* @brief Has pins 8-15 connected to LLWU device. */ 736 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 737 /* @brief Maximum number of internal modules connected to LLWU device. */ 738 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 739 /* @brief Number of digital filters. */ 740 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 741 /* @brief Has MF register. */ 742 #define FSL_FEATURE_LLWU_HAS_MF (0) 743 /* @brief Has PF register. */ 744 #define FSL_FEATURE_LLWU_HAS_PF (0) 745 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 746 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 747 /* @brief Has no internal module wakeup flag register. */ 748 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 749 /* @brief Has external pin 0 connected to LLWU device. */ 750 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 751 /* @brief Index of port of external pin. */ 752 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 753 /* @brief Number of external pin port on specified port. */ 754 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 755 /* @brief Has external pin 1 connected to LLWU device. */ 756 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 757 /* @brief Index of port of external pin. */ 758 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 759 /* @brief Number of external pin port on specified port. */ 760 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 761 /* @brief Has external pin 2 connected to LLWU device. */ 762 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 763 /* @brief Index of port of external pin. */ 764 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 765 /* @brief Number of external pin port on specified port. */ 766 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 767 /* @brief Has external pin 3 connected to LLWU device. */ 768 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 769 /* @brief Index of port of external pin. */ 770 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 771 /* @brief Number of external pin port on specified port. */ 772 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 773 /* @brief Has external pin 4 connected to LLWU device. */ 774 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 775 /* @brief Index of port of external pin. */ 776 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 777 /* @brief Number of external pin port on specified port. */ 778 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 779 /* @brief Has external pin 5 connected to LLWU device. */ 780 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 781 /* @brief Index of port of external pin. */ 782 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 783 /* @brief Number of external pin port on specified port. */ 784 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 785 /* @brief Has external pin 6 connected to LLWU device. */ 786 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 787 /* @brief Index of port of external pin. */ 788 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 789 /* @brief Number of external pin port on specified port. */ 790 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 791 /* @brief Has external pin 7 connected to LLWU device. */ 792 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 793 /* @brief Index of port of external pin. */ 794 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 795 /* @brief Number of external pin port on specified port. */ 796 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 797 /* @brief Has external pin 8 connected to LLWU device. */ 798 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 799 /* @brief Index of port of external pin. */ 800 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 801 /* @brief Number of external pin port on specified port. */ 802 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 803 /* @brief Has external pin 9 connected to LLWU device. */ 804 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 805 /* @brief Index of port of external pin. */ 806 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 807 /* @brief Number of external pin port on specified port. */ 808 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 809 /* @brief Has external pin 10 connected to LLWU device. */ 810 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 811 /* @brief Index of port of external pin. */ 812 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 813 /* @brief Number of external pin port on specified port. */ 814 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 815 /* @brief Has external pin 11 connected to LLWU device. */ 816 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 817 /* @brief Index of port of external pin. */ 818 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 819 /* @brief Number of external pin port on specified port. */ 820 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 821 /* @brief Has external pin 12 connected to LLWU device. */ 822 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 823 /* @brief Index of port of external pin. */ 824 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 825 /* @brief Number of external pin port on specified port. */ 826 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 827 /* @brief Has external pin 13 connected to LLWU device. */ 828 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 829 /* @brief Index of port of external pin. */ 830 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 831 /* @brief Number of external pin port on specified port. */ 832 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 833 /* @brief Has external pin 14 connected to LLWU device. */ 834 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 835 /* @brief Index of port of external pin. */ 836 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 837 /* @brief Number of external pin port on specified port. */ 838 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 839 /* @brief Has external pin 15 connected to LLWU device. */ 840 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 841 /* @brief Index of port of external pin. */ 842 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 843 /* @brief Number of external pin port on specified port. */ 844 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 845 /* @brief Has external pin 16 connected to LLWU device. */ 846 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 847 /* @brief Index of port of external pin. */ 848 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 849 /* @brief Number of external pin port on specified port. */ 850 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 851 /* @brief Has external pin 17 connected to LLWU device. */ 852 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 853 /* @brief Index of port of external pin. */ 854 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 855 /* @brief Number of external pin port on specified port. */ 856 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 857 /* @brief Has external pin 18 connected to LLWU device. */ 858 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 859 /* @brief Index of port of external pin. */ 860 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 861 /* @brief Number of external pin port on specified port. */ 862 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 863 /* @brief Has external pin 19 connected to LLWU device. */ 864 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 865 /* @brief Index of port of external pin. */ 866 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 867 /* @brief Number of external pin port on specified port. */ 868 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 869 /* @brief Has external pin 20 connected to LLWU device. */ 870 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 871 /* @brief Index of port of external pin. */ 872 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 873 /* @brief Number of external pin port on specified port. */ 874 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 875 /* @brief Has external pin 21 connected to LLWU device. */ 876 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 877 /* @brief Index of port of external pin. */ 878 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 879 /* @brief Number of external pin port on specified port. */ 880 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 881 /* @brief Has external pin 22 connected to LLWU device. */ 882 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 883 /* @brief Index of port of external pin. */ 884 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 885 /* @brief Number of external pin port on specified port. */ 886 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 887 /* @brief Has external pin 23 connected to LLWU device. */ 888 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 889 /* @brief Index of port of external pin. */ 890 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 891 /* @brief Number of external pin port on specified port. */ 892 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 893 /* @brief Has external pin 24 connected to LLWU device. */ 894 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 895 /* @brief Index of port of external pin. */ 896 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 897 /* @brief Number of external pin port on specified port. */ 898 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 899 /* @brief Has external pin 25 connected to LLWU device. */ 900 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 901 /* @brief Index of port of external pin. */ 902 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 903 /* @brief Number of external pin port on specified port. */ 904 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 905 /* @brief Has external pin 26 connected to LLWU device. */ 906 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 907 /* @brief Index of port of external pin. */ 908 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 909 /* @brief Number of external pin port on specified port. */ 910 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 911 /* @brief Has external pin 27 connected to LLWU device. */ 912 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 913 /* @brief Index of port of external pin. */ 914 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 915 /* @brief Number of external pin port on specified port. */ 916 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 917 /* @brief Has external pin 28 connected to LLWU device. */ 918 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 919 /* @brief Index of port of external pin. */ 920 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 921 /* @brief Number of external pin port on specified port. */ 922 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 923 /* @brief Has external pin 29 connected to LLWU device. */ 924 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 925 /* @brief Index of port of external pin. */ 926 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 927 /* @brief Number of external pin port on specified port. */ 928 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 929 /* @brief Has external pin 30 connected to LLWU device. */ 930 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 931 /* @brief Index of port of external pin. */ 932 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 933 /* @brief Number of external pin port on specified port. */ 934 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 935 /* @brief Has external pin 31 connected to LLWU device. */ 936 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 937 /* @brief Index of port of external pin. */ 938 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 939 /* @brief Number of external pin port on specified port. */ 940 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 941 /* @brief Has internal module 0 connected to LLWU device. */ 942 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 943 /* @brief Has internal module 1 connected to LLWU device. */ 944 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 945 /* @brief Has internal module 2 connected to LLWU device. */ 946 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 947 /* @brief Has internal module 3 connected to LLWU device. */ 948 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 949 /* @brief Has internal module 4 connected to LLWU device. */ 950 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 951 /* @brief Has internal module 5 connected to LLWU device. */ 952 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 953 /* @brief Has internal module 6 connected to LLWU device. */ 954 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 955 /* @brief Has internal module 7 connected to LLWU device. */ 956 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 957 /* @brief Has Version ID Register (LLWU_VERID). */ 958 #define FSL_FEATURE_LLWU_HAS_VERID (0) 959 /* @brief Has Parameter Register (LLWU_PARAM). */ 960 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 961 /* @brief Width of registers of the LLWU. */ 962 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 963 /* @brief Has DMA Enable register (LLWU_DE). */ 964 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 965 #endif /* defined(CPU_MKV31F512VLH12) */ 966 967 /* LPTMR module features */ 968 969 /* @brief Has shared interrupt handler with another LPTMR module. */ 970 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 971 /* @brief Whether LPTMR counter is 32 bits width. */ 972 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 973 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 974 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 975 976 /* LPUART module features */ 977 978 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 979 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 980 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 981 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 982 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 983 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 984 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 985 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 986 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 987 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 988 /* @brief Has 32-bit register MODIR */ 989 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 990 /* @brief Hardware flow control (RTS, CTS) is supported. */ 991 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 992 /* @brief Infrared (modulation) is supported. */ 993 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 994 /* @brief 2 bits long stop bit is available. */ 995 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 996 /* @brief If 10-bit mode is supported. */ 997 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 998 /* @brief If 7-bit mode is supported. */ 999 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 1000 /* @brief Baud rate fine adjustment is available. */ 1001 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 1002 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1003 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 1004 /* @brief Baud rate oversampling is available. */ 1005 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 1006 /* @brief Baud rate oversampling is available. */ 1007 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 1008 /* @brief Peripheral type. */ 1009 #define FSL_FEATURE_LPUART_IS_SCI (1) 1010 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1011 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 1012 /* @brief Supports two match addresses to filter incoming frames. */ 1013 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 1014 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1015 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 1016 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1017 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 1018 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1019 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 1020 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1021 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 1022 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1023 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1024 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1025 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1026 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1027 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1028 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1029 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1030 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1031 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1032 /* @brief Has separate DMA RX and TX requests. */ 1033 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1034 /* @brief Has separate RX and TX interrupts. */ 1035 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1036 /* @brief Has LPAURT_PARAM. */ 1037 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 1038 /* @brief Has LPUART_VERID. */ 1039 #define FSL_FEATURE_LPUART_HAS_VERID (0) 1040 /* @brief Has LPUART_GLOBAL. */ 1041 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 1042 /* @brief Has LPUART_PINCFG. */ 1043 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 1044 1045 /* MCG module features */ 1046 1047 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1048 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1049 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1050 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 1051 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1052 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 1053 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1054 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 1055 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1056 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 1057 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1058 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1059 /* @brief FRDIV supports 1280. */ 1060 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1061 /* @brief FRDIV supports 1536. */ 1062 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1063 /* @brief MCGFFCLK divider. */ 1064 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1065 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1066 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1067 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1068 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1069 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1070 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1071 /* @brief Has 48MHz internal oscillator. */ 1072 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 1073 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1074 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1075 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1076 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1077 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1078 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1079 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1080 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1081 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1082 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1083 /* @brief TBD */ 1084 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1085 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1086 #define FSL_FEATURE_MCG_HAS_PLL (1) 1087 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1088 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1089 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1090 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1091 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1092 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1093 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1094 #define FSL_FEATURE_MCG_HAS_FLL (1) 1095 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1096 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1097 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1098 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1099 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1100 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1101 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1102 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1103 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1104 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1105 /* @brief Has external clock monitor (register bit C6[CME]). */ 1106 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1107 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1108 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1109 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1110 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1111 /* @brief Has PEI mode or PBI mode. */ 1112 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1113 /* @brief Reset clock mode is BLPI. */ 1114 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1115 1116 /* interrupt module features */ 1117 1118 /* @brief Lowest interrupt request number. */ 1119 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1120 /* @brief Highest interrupt request number. */ 1121 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) 1122 1123 /* OSC module features */ 1124 1125 /* @brief Has OSC1 external oscillator. */ 1126 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1127 /* @brief Has OSC0 external oscillator. */ 1128 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1129 /* @brief Has OSC external oscillator (without index). */ 1130 #define FSL_FEATURE_OSC_HAS_OSC (1) 1131 /* @brief Number of OSC external oscillators. */ 1132 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1133 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1134 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 1135 1136 /* PDB module features */ 1137 1138 /* @brief Has DAC support. */ 1139 #define FSL_FEATURE_PDB_HAS_DAC (1) 1140 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1141 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1142 /* @brief PDB channel number). */ 1143 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1144 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1145 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1146 /* @brief DAC interval trigger number). */ 1147 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (2) 1148 /* @brief Pulse out number). */ 1149 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1150 1151 /* PIT module features */ 1152 1153 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1154 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1155 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1156 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 1157 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1158 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1159 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1160 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1161 /* @brief Has timer enable control. */ 1162 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1163 1164 /* PMC module features */ 1165 1166 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1167 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1168 /* @brief Has Bandgap Buffer Enable. */ 1169 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1170 /* @brief Has Bandgap Buffer Drive Select. */ 1171 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1172 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1173 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1174 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1175 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1176 /* @brief Has LPO. */ 1177 #define FSL_FEATURE_PMC_HAS_LPO (0) 1178 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1179 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1180 /* @brief Has acknowledge isolation support. */ 1181 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1182 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1183 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1184 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1185 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1186 /* @brief Has PMC_HVDSC1. */ 1187 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1188 /* @brief Has PMC_PARAM. */ 1189 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1190 /* @brief Has PMC_VERID. */ 1191 #define FSL_FEATURE_PMC_HAS_VERID (0) 1192 1193 /* PORT module features */ 1194 1195 /* @brief Has control lock (register bit PCR[LK]). */ 1196 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1197 /* @brief Has open drain control (register bit PCR[ODE]). */ 1198 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1199 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1200 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1201 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1202 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1203 /* @brief Has pull resistor selection available. */ 1204 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1205 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1206 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1207 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1208 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1209 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1210 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1211 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1212 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1213 /* @brief Has separate drive strength register (HDRVE). */ 1214 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1215 /* @brief Has glitch filter (register IOFLT). */ 1216 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1217 /* @brief Defines width of PCR[MUX] field. */ 1218 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1219 /* @brief Has dedicated interrupt vector. */ 1220 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1221 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1222 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1223 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1224 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1225 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1226 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1227 1228 /* RCM module features */ 1229 1230 /* @brief Has Loss-of-Lock Reset support. */ 1231 #define FSL_FEATURE_RCM_HAS_LOL (1) 1232 /* @brief Has Loss-of-Clock Reset support. */ 1233 #define FSL_FEATURE_RCM_HAS_LOC (1) 1234 /* @brief Has JTAG generated Reset support. */ 1235 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1236 /* @brief Has EzPort generated Reset support. */ 1237 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 1238 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1239 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 1240 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1241 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1242 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1243 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1244 /* @brief Has Version ID Register (RCM_VERID). */ 1245 #define FSL_FEATURE_RCM_HAS_VERID (0) 1246 /* @brief Has Parameter Register (RCM_PARAM). */ 1247 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1248 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1249 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1250 /* @brief Width of registers of the RCM. */ 1251 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1252 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1253 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1254 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1255 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1256 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1257 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1258 1259 /* SIM module features */ 1260 1261 /* @brief Has USB FS divider. */ 1262 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1263 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1264 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1265 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1266 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1267 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1268 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) 1269 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1270 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1271 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1272 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1273 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1274 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1275 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1276 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1277 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1278 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1279 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1280 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1281 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1282 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1283 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1284 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1285 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1286 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1287 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1288 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1289 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1290 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) 1291 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1292 #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) 1293 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1294 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1295 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1296 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1297 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1298 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1299 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1300 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1301 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1302 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1303 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1304 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1305 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1306 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1307 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1308 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1309 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1310 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1311 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1312 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1313 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1314 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1315 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1316 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1317 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1318 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1319 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1320 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1321 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1322 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1323 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1324 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1325 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1326 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1327 /* @brief Has FTM module(s) configuration. */ 1328 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1329 /* @brief Number of FTM modules. */ 1330 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1331 /* @brief Number of FTM triggers with selectable source. */ 1332 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1333 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1334 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1335 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1336 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1337 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1338 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1339 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1340 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1341 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1342 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1343 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1344 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1345 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1346 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1347 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1348 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1349 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1350 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1351 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1352 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1353 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1354 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1355 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1356 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1357 /* @brief Has TPM module(s) configuration. */ 1358 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1359 /* @brief The highest TPM module index. */ 1360 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1361 /* @brief Has TPM module with index 0. */ 1362 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1363 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1364 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1365 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1366 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1367 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1368 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1369 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1370 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1371 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1372 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1373 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1374 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1375 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1376 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1377 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1378 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1379 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1380 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1381 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1382 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1383 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1384 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1385 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1386 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1387 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1388 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1389 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1390 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1391 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1392 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1393 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1394 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1395 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1396 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1397 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1398 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1399 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1400 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) 1401 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1402 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1403 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1404 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1405 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1406 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1407 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1408 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1409 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1410 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1411 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1412 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1413 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1414 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1415 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1416 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1417 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1418 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) 1419 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1420 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1421 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1422 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1423 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1424 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1425 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1426 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1427 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1428 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1429 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1430 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1431 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1432 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1433 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1434 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1435 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1436 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1437 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1438 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1439 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1440 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1441 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1442 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1443 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1444 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1445 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1446 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1447 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1448 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1449 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1450 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1451 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1452 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1453 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1454 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1455 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1456 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1457 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1458 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1459 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1460 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1461 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1462 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) 1463 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1464 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1465 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1466 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1467 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1468 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1469 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1470 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1471 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1472 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1473 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1474 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1475 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1476 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1477 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1478 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1479 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1480 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1481 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1482 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1483 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1484 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1485 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1486 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1487 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1488 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1489 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1490 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1491 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1492 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1493 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1494 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1495 /* @brief Has miscellanious control register (register MCR). */ 1496 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1497 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1498 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1499 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1500 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1501 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1502 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1503 /* @brief Has UIDH registers. */ 1504 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1505 /* @brief Has UIDM registers. */ 1506 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1507 1508 /* SMC module features */ 1509 1510 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1511 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1512 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1513 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1514 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1515 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1516 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1517 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1518 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1519 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1520 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1521 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1522 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1523 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1524 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1525 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1526 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1527 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1528 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1529 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1530 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1531 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1532 /* @brief Has stop submode. */ 1533 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1534 /* @brief Has stop submode 0(VLLS0). */ 1535 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1536 /* @brief Has stop submode 1(VLLS1). */ 1537 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1538 /* @brief Has stop submode 2(VLLS2). */ 1539 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1540 /* @brief Has SMC_PARAM. */ 1541 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1542 /* @brief Has SMC_VERID. */ 1543 #define FSL_FEATURE_SMC_HAS_VERID (0) 1544 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1545 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1546 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1547 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1548 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1549 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1550 /* @brief Width of SMC registers. */ 1551 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1552 1553 /* DSPI module features */ 1554 1555 #if defined(CPU_MKV31F512VLH12) 1556 /* @brief Receive/transmit FIFO size in number of items. */ 1557 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1558 (((x) == SPI0) ? (4) : \ 1559 (((x) == SPI1) ? (1) : (-1))) 1560 /* @brief Maximum transfer data width in bits. */ 1561 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1562 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1563 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1564 /* @brief Number of chip select pins. */ 1565 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) 1566 /* @brief Number of CTAR registers. */ 1567 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1568 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1569 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1570 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1571 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1572 /* @brief Has 16-bit data transfer support. */ 1573 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1574 /* @brief Has separate DMA RX and TX requests. */ 1575 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1576 (((x) == SPI0) ? (1) : \ 1577 (((x) == SPI1) ? (0) : (-1))) 1578 #elif defined(CPU_MKV31F512VLL12) 1579 /* @brief Receive/transmit FIFO size in number of items. */ 1580 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1581 (((x) == SPI0) ? (4) : \ 1582 (((x) == SPI1) ? (1) : (-1))) 1583 /* @brief Maximum transfer data width in bits. */ 1584 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1585 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1586 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1587 /* @brief Number of chip select pins. */ 1588 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1589 /* @brief Number of CTAR registers. */ 1590 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1591 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1592 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1593 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1594 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1595 /* @brief Has 16-bit data transfer support. */ 1596 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1597 /* @brief Has separate DMA RX and TX requests. */ 1598 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1599 (((x) == SPI0) ? (1) : \ 1600 (((x) == SPI1) ? (0) : (-1))) 1601 #endif /* defined(CPU_MKV31F512VLH12) */ 1602 1603 /* SysTick module features */ 1604 1605 /* @brief Systick has external reference clock. */ 1606 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1607 /* @brief Systick external reference clock is core clock divided by this value. */ 1608 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1609 1610 /* UART module features */ 1611 1612 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1613 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1614 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1615 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1616 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1617 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1618 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1619 #define FSL_FEATURE_UART_HAS_FIFO (1) 1620 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1621 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1622 /* @brief Infrared (modulation) is supported. */ 1623 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1624 /* @brief 2 bits long stop bit is available. */ 1625 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1626 /* @brief If 10-bit mode is supported. */ 1627 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1628 /* @brief Baud rate fine adjustment is available. */ 1629 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1630 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1631 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1632 /* @brief Baud rate oversampling is available. */ 1633 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1634 /* @brief Baud rate oversampling is available. */ 1635 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1636 /* @brief Peripheral type. */ 1637 #define FSL_FEATURE_UART_IS_SCI (0) 1638 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1639 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1640 (((x) == UART0) ? (8) : \ 1641 (((x) == UART1) ? (1) : \ 1642 (((x) == UART2) ? (1) : (-1)))) 1643 /* @brief Supports two match addresses to filter incoming frames. */ 1644 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1645 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1646 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1647 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1648 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1649 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1650 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1651 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1652 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1653 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1654 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1655 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1656 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1657 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1658 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1659 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1660 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1661 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1662 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1663 /* @brief Has separate DMA RX and TX requests. */ 1664 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1665 1666 /* VREF module features */ 1667 1668 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1669 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1670 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1671 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1672 /* @brief If high/low buffer mode supported */ 1673 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1674 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1675 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1676 /* @brief Has VREF_TRM4. */ 1677 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1678 1679 /* WDOG module features */ 1680 1681 /* @brief Watchdog is available. */ 1682 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1683 /* @brief Has Wait mode support. */ 1684 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1685 1686 #endif /* _MKV31F51212_FEATURES_H_ */ 1687 1688
