1 /*
2 ** ###################################################################
3 ** Processors: MKV31F128VLH10
4 ** MKV31F128VLL10
5 **
6 ** Compilers: Freescale C/C++ for Embedded ARM
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** Keil ARM C/C++ Compiler
10 ** MCUXpresso Compiler
11 **
12 ** Reference manual: KV31P100M100SF9RM, Rev. 1, April 25, 2014
13 ** Version: rev. 1.6, 2015-02-19
14 ** Build: b181105
15 **
16 ** Abstract:
17 ** Provides a system configuration function and a global variable that
18 ** contains the system frequency. It configures the device and initializes
19 ** the oscillator (PLL) that is part of the microcontroller device.
20 **
21 ** Copyright 2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2018 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2013-11-01)
32 ** Initial version.
33 ** - rev. 1.1 (2013-12-20)
34 ** Update according to reference manual rev. 0.1,
35 ** - rev. 1.2 (2014-02-10)
36 ** The declaration of clock configurations has been moved to separate header file system_MKV21F12810.h
37 ** - rev. 1.3 (2014-05-06)
38 ** Update according to reference manual rev. 1.0,
39 ** Update of system and startup files.
40 ** Module access macro module_BASES replaced by module_BASE_PTRS.
41 ** - rev. 1.4 (2014-08-28)
42 ** Update of system files - default clock configuration changed.
43 ** Update of startup files - possibility to override DefaultISR added.
44 ** - rev. 1.5 (2014-10-14)
45 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
46 ** - rev. 1.6 (2015-02-19)
47 ** Renamed interrupt vector LLW to LLWU.
48 **
49 ** ###################################################################
50 */
51
52 /*!
53 * @file MKV31F12810
54 * @version 1.6
55 * @date 2015-02-19
56 * @brief Device specific configuration file for MKV31F12810 (implementation
57 * file)
58 *
59 * Provides a system configuration function and a global variable that contains
60 * the system frequency. It configures the device and initializes the oscillator
61 * (PLL) that is part of the microcontroller device.
62 */
63
64 #include <stdint.h>
65 #include "fsl_device_registers.h"
66
67
68
69 /* ----------------------------------------------------------------------------
70 -- Core clock
71 ---------------------------------------------------------------------------- */
72
73 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
74
75 /* ----------------------------------------------------------------------------
76 -- SystemInit()
77 ---------------------------------------------------------------------------- */
78
SystemInit(void)79 void SystemInit (void) {
80 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
81 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
82 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
83
84 #if (DISABLE_WDOG)
85 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
86 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
87 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
88 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
89 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
90 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
91 WDOG_STCTRLH_WAITEN_MASK |
92 WDOG_STCTRLH_STOPEN_MASK |
93 WDOG_STCTRLH_ALLOWUPDATE_MASK |
94 WDOG_STCTRLH_CLKSRC_MASK |
95 0x0100U;
96 #endif /* (DISABLE_WDOG) */
97
98 SystemInitHook();
99 }
100
101 /* ----------------------------------------------------------------------------
102 -- SystemCoreClockUpdate()
103 ---------------------------------------------------------------------------- */
104
SystemCoreClockUpdate(void)105 void SystemCoreClockUpdate (void) {
106
107 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
108 uint16_t Divider;
109 uint8_t tmpC7 = 0;
110
111 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
112 /* FLL is selected */
113 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
114 /* External reference clock is selected */
115 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
116 case 0x00U:
117 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
118 break;
119 case 0x02U:
120 default:
121 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
122 break;
123 }
124 tmpC7 = MCG->C7;
125 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
126 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
127 case 0x38U:
128 Divider = 1536U;
129 break;
130 case 0x30U:
131 Divider = 1280U;
132 break;
133 default:
134 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
135 break;
136 }
137 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
138 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
139 }
140 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
141 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
142 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
143 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
144 /* Select correct multiplier to calculate the MCG output clock */
145 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
146 case 0x00U:
147 MCGOUTClock *= 640U;
148 break;
149 case 0x20U:
150 MCGOUTClock *= 1280U;
151 break;
152 case 0x40U:
153 MCGOUTClock *= 1920U;
154 break;
155 case 0x60U:
156 MCGOUTClock *= 2560U;
157 break;
158 case 0x80U:
159 MCGOUTClock *= 732U;
160 break;
161 case 0xA0U:
162 MCGOUTClock *= 1464U;
163 break;
164 case 0xC0U:
165 MCGOUTClock *= 2197U;
166 break;
167 case 0xE0U:
168 MCGOUTClock *= 2929U;
169 break;
170 default:
171 MCGOUTClock *= 640U;
172 break;
173 }
174 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
175 /* Internal reference clock is selected */
176 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
177 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
178 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
179 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
180 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
181 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
182 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
183 /* External reference clock is selected */
184 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
185 case 0x00U:
186 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
187 break;
188 case 0x02U:
189 default:
190 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
191 break;
192 }
193 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
194 /* Reserved value */
195 return;
196 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
197 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
198 }
199
200 /* ----------------------------------------------------------------------------
201 -- SystemInitHook()
202 ---------------------------------------------------------------------------- */
203
SystemInitHook(void)204 __attribute__ ((weak)) void SystemInitHook (void) {
205 /* Void implementation of the weak function. */
206 }
207
