1 /* 2 ** ################################################################### 3 ** Version: rev. 1.11, 2015-06-08 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2013-11-01) 20 ** Initial version. 21 ** - rev. 1.1 (2013-12-20) 22 ** Update according to reference manual rev. 0.1, 23 ** - rev. 1.2 (2014-01-30) 24 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 25 ** - rev. 1.3 (2014-02-10) 26 ** The declaration of clock configurations has been moved to separate header file system_MKV21F12810.h 27 ** - rev. 1.4 (2014-05-06) 28 ** Update according to reference manual rev. 1.0, 29 ** Update of system and startup files. 30 ** Module access macro module_BASES replaced by module_BASE_PTRS. 31 ** - rev. 1.5 (2014-08-28) 32 ** Update of system files - default clock configuration changed. 33 ** Update of startup files - possibility to override DefaultISR added. 34 ** - rev. 1.6 (2014-10-14) 35 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. 36 ** - rev. 1.7 (2015-01-21) 37 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 38 ** - rev. 1.8 (2015-02-19) 39 ** Renamed interrupt vector LLW to LLWU. 40 ** - rev. 1.9 (2015-05-19) 41 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 42 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 43 ** Added features for PORT and PDB. 44 ** - rev. 1.10 (2015-05-25) 45 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 46 ** - rev. 1.11 (2015-06-08) 47 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 48 ** 49 ** ################################################################### 50 */ 51 52 #ifndef _MKV31F12810_FEATURES_H_ 53 #define _MKV31F12810_FEATURES_H_ 54 55 /* SOC module features */ 56 57 /* @brief ADC16 availability on the SoC. */ 58 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 59 /* @brief CMP availability on the SoC. */ 60 #define FSL_FEATURE_SOC_CMP_COUNT (2) 61 /* @brief CRC availability on the SoC. */ 62 #define FSL_FEATURE_SOC_CRC_COUNT (1) 63 /* @brief DAC availability on the SoC. */ 64 #define FSL_FEATURE_SOC_DAC_COUNT (1) 65 /* @brief EDMA availability on the SoC. */ 66 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 67 /* @brief DMAMUX availability on the SoC. */ 68 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 69 /* @brief DSPI availability on the SoC. */ 70 #define FSL_FEATURE_SOC_DSPI_COUNT (2) 71 /* @brief EWM availability on the SoC. */ 72 #define FSL_FEATURE_SOC_EWM_COUNT (1) 73 /* @brief FMC availability on the SoC. */ 74 #define FSL_FEATURE_SOC_FMC_COUNT (1) 75 /* @brief FTFA availability on the SoC. */ 76 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 77 /* @brief FTM availability on the SoC. */ 78 #define FSL_FEATURE_SOC_FTM_COUNT (3) 79 /* @brief GPIO availability on the SoC. */ 80 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 81 /* @brief I2C availability on the SoC. */ 82 #define FSL_FEATURE_SOC_I2C_COUNT (2) 83 /* @brief LLWU availability on the SoC. */ 84 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 85 /* @brief LPTMR availability on the SoC. */ 86 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 87 /* @brief LPUART availability on the SoC. */ 88 #define FSL_FEATURE_SOC_LPUART_COUNT (1) 89 /* @brief MCG availability on the SoC. */ 90 #define FSL_FEATURE_SOC_MCG_COUNT (1) 91 /* @brief MCM availability on the SoC. */ 92 #define FSL_FEATURE_SOC_MCM_COUNT (1) 93 /* @brief OSC availability on the SoC. */ 94 #define FSL_FEATURE_SOC_OSC_COUNT (1) 95 /* @brief PDB availability on the SoC. */ 96 #define FSL_FEATURE_SOC_PDB_COUNT (1) 97 /* @brief PIT availability on the SoC. */ 98 #define FSL_FEATURE_SOC_PIT_COUNT (1) 99 /* @brief PMC availability on the SoC. */ 100 #define FSL_FEATURE_SOC_PMC_COUNT (1) 101 /* @brief PORT availability on the SoC. */ 102 #define FSL_FEATURE_SOC_PORT_COUNT (5) 103 /* @brief RCM availability on the SoC. */ 104 #define FSL_FEATURE_SOC_RCM_COUNT (1) 105 /* @brief RFSYS availability on the SoC. */ 106 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 107 /* @brief RFVBAT availability on the SoC. */ 108 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 109 /* @brief SIM availability on the SoC. */ 110 #define FSL_FEATURE_SOC_SIM_COUNT (1) 111 /* @brief SMC availability on the SoC. */ 112 #define FSL_FEATURE_SOC_SMC_COUNT (1) 113 /* @brief UART availability on the SoC. */ 114 #define FSL_FEATURE_SOC_UART_COUNT (3) 115 /* @brief VREF availability on the SoC. */ 116 #define FSL_FEATURE_SOC_VREF_COUNT (1) 117 /* @brief WDOG availability on the SoC. */ 118 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 119 120 /* ADC16 module features */ 121 122 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 123 #define FSL_FEATURE_ADC16_HAS_PGA (0) 124 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 125 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 126 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 127 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 128 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 129 #define FSL_FEATURE_ADC16_HAS_DMA (1) 130 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 131 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 132 /* @brief Has FIFO (bit SC4[AFDEP]). */ 133 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 134 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 135 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 136 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 137 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 138 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 139 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 140 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 141 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 142 /* @brief Has HW averaging (bit SC3[AVGE]). */ 143 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 144 /* @brief Has offset correction (register OFS). */ 145 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 146 /* @brief Maximum ADC resolution. */ 147 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 148 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 149 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 150 151 /* CMP module features */ 152 153 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 154 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 155 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 156 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 157 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 158 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 159 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 160 #define FSL_FEATURE_CMP_HAS_DMA (1) 161 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 162 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 163 /* @brief Has DAC Test function in CMP (register DACTEST). */ 164 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 165 166 /* CRC module features */ 167 168 /* @brief Has data register with name CRC */ 169 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 170 171 /* DAC module features */ 172 173 /* @brief Define the size of hardware buffer */ 174 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 175 /* @brief Define whether the buffer supports watermark event detection or not. */ 176 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 177 /* @brief Define whether the buffer supports watermark selection detection or not. */ 178 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 179 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 180 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 181 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 182 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 183 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 184 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 185 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 186 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 187 /* @brief Define whether FIFO buffer mode is available or not. */ 188 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 189 /* @brief Define whether swing buffer mode is available or not.. */ 190 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 191 192 /* EDMA module features */ 193 194 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 195 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) 196 /* @brief Total number of DMA channels on all modules. */ 197 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (4) 198 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 199 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 200 /* @brief Has DMA_Error interrupt vector. */ 201 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 202 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 203 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) 204 /* @brief Channel IRQ entry shared offset. */ 205 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 206 /* @brief If 8 bytes transfer supported. */ 207 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 208 /* @brief If 16 bytes transfer supported. */ 209 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 210 211 /* DMAMUX module features */ 212 213 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 214 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 215 /* @brief Total number of DMA channels on all modules. */ 216 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4) 217 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 218 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 219 /* @brief Register CHCFGn width. */ 220 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 221 222 /* EWM module features */ 223 224 /* @brief Has clock select (register CLKCTRL). */ 225 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 226 /* @brief Has clock prescaler (register CLKPRESCALER). */ 227 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 228 229 /* FLASH module features */ 230 231 /* @brief Is of type FTFA. */ 232 #define FSL_FEATURE_FLASH_IS_FTFA (1) 233 /* @brief Is of type FTFE. */ 234 #define FSL_FEATURE_FLASH_IS_FTFE (0) 235 /* @brief Is of type FTFL. */ 236 #define FSL_FEATURE_FLASH_IS_FTFL (0) 237 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 238 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 239 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 240 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 241 /* @brief Has EEPROM region protection (register FEPROT). */ 242 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 243 /* @brief Has data flash region protection (register FDPROT). */ 244 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 245 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 246 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 247 /* @brief Has flash cache control in FMC module. */ 248 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 249 /* @brief Has flash cache control in MCM module. */ 250 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 251 /* @brief Has flash cache control in MSCM module. */ 252 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 253 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 254 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 255 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 256 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 257 /* @brief P-Flash start address. */ 258 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 259 /* @brief P-Flash block count. */ 260 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 261 /* @brief P-Flash block size. */ 262 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 263 /* @brief P-Flash sector size. */ 264 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 265 /* @brief P-Flash write unit size. */ 266 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 267 /* @brief P-Flash data path width. */ 268 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 269 /* @brief P-Flash block swap feature. */ 270 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 271 /* @brief P-Flash protection region count. */ 272 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 273 /* @brief Has FlexNVM memory. */ 274 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 275 /* @brief Has FlexNVM alias. */ 276 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 277 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 278 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 279 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 280 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 281 /* @brief FlexNVM block count. */ 282 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 283 /* @brief FlexNVM block size. */ 284 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 285 /* @brief FlexNVM sector size. */ 286 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 287 /* @brief FlexNVM write unit size. */ 288 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 289 /* @brief FlexNVM data path width. */ 290 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 291 /* @brief Has FlexRAM memory. */ 292 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 293 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 294 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 295 /* @brief FlexRAM size. */ 296 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 297 /* @brief Has 0x00 Read 1s Block command. */ 298 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 299 /* @brief Has 0x01 Read 1s Section command. */ 300 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 301 /* @brief Has 0x02 Program Check command. */ 302 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 303 /* @brief Has 0x03 Read Resource command. */ 304 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 305 /* @brief Has 0x06 Program Longword command. */ 306 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 307 /* @brief Has 0x07 Program Phrase command. */ 308 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 309 /* @brief Has 0x08 Erase Flash Block command. */ 310 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 311 /* @brief Has 0x09 Erase Flash Sector command. */ 312 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 313 /* @brief Has 0x0B Program Section command. */ 314 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 315 /* @brief Has 0x40 Read 1s All Blocks command. */ 316 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 317 /* @brief Has 0x41 Read Once command. */ 318 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 319 /* @brief Has 0x43 Program Once command. */ 320 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 321 /* @brief Has 0x44 Erase All Blocks command. */ 322 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 323 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 324 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 325 /* @brief Has 0x46 Swap Control command. */ 326 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 327 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 328 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 329 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 330 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 331 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 332 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 333 /* @brief Has 0x80 Program Partition command. */ 334 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 335 /* @brief Has 0x81 Set FlexRAM Function command. */ 336 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 337 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 338 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 339 /* @brief P-Flash Erase sector command address alignment. */ 340 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 341 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 342 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 343 /* @brief P-Flash Read resource command address alignment. */ 344 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 345 /* @brief P-Flash Program check command address alignment. */ 346 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 347 /* @brief P-Flash Program check command address alignment. */ 348 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 349 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 350 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 351 /* @brief FlexNVM Erase sector command address alignment. */ 352 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 353 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 354 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 355 /* @brief FlexNVM Read resource command address alignment. */ 356 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 357 /* @brief FlexNVM Program check command address alignment. */ 358 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 359 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 361 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 363 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 365 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 366 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 367 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 368 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 369 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 370 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 371 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 372 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 373 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 374 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 375 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 376 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 377 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 378 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 379 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 381 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 383 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 385 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 387 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 389 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 391 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 393 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 395 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 397 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 398 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 399 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 400 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 401 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 402 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 403 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 404 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 405 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 406 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 407 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 408 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 409 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 410 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 411 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 412 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 413 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 414 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 415 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 416 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 417 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 418 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 419 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 420 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 421 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 422 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 423 424 /* FTM module features */ 425 426 /* @brief Number of channels. */ 427 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 428 (((x) == FTM0) ? (8) : \ 429 (((x) == FTM1) ? (2) : \ 430 (((x) == FTM2) ? (2) : (-1)))) 431 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 432 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 433 /* @brief Has extended deadtime value. */ 434 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 435 /* @brief Enable pwm output for the module. */ 436 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 437 /* @brief Has half-cycle reload for the module. */ 438 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 439 /* @brief Has reload interrupt. */ 440 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 441 /* @brief Has reload initialization trigger. */ 442 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 443 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 444 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 445 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 446 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 447 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 448 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 449 /* @brief Has no QDCTRL. */ 450 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 451 /* @brief If instance has only TPM function. */ 452 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 453 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 454 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0) 455 456 /* GPIO module features */ 457 458 /* @brief Has GPIO attribute checker register (GACR). */ 459 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 460 461 /* I2C module features */ 462 463 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 464 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 465 /* @brief Maximum supported baud rate in kilobit per second. */ 466 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 467 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 468 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 469 /* @brief Has DMA support (register bit C1[DMAEN]). */ 470 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 471 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 472 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 473 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 474 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 475 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 476 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 477 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 478 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 479 /* @brief Has control of the drive capability of the I2C pins. */ 480 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 481 /* @brief Has double buffering support (register S2). */ 482 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 483 /* @brief Has double buffer enable. */ 484 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 485 486 /* LLWU module features */ 487 488 #if defined(CPU_MKV31F128VLH10) 489 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 490 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 491 /* @brief Has pins 8-15 connected to LLWU device. */ 492 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 493 /* @brief Maximum number of internal modules connected to LLWU device. */ 494 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 495 /* @brief Number of digital filters. */ 496 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 497 /* @brief Has MF register. */ 498 #define FSL_FEATURE_LLWU_HAS_MF (0) 499 /* @brief Has PF register. */ 500 #define FSL_FEATURE_LLWU_HAS_PF (0) 501 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 502 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 503 /* @brief Has no internal module wakeup flag register. */ 504 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 505 /* @brief Has external pin 0 connected to LLWU device. */ 506 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 507 /* @brief Index of port of external pin. */ 508 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 509 /* @brief Number of external pin port on specified port. */ 510 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 511 /* @brief Has external pin 1 connected to LLWU device. */ 512 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 513 /* @brief Index of port of external pin. */ 514 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 515 /* @brief Number of external pin port on specified port. */ 516 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 517 /* @brief Has external pin 2 connected to LLWU device. */ 518 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 519 /* @brief Index of port of external pin. */ 520 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 521 /* @brief Number of external pin port on specified port. */ 522 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 523 /* @brief Has external pin 3 connected to LLWU device. */ 524 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 525 /* @brief Index of port of external pin. */ 526 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 527 /* @brief Number of external pin port on specified port. */ 528 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 529 /* @brief Has external pin 4 connected to LLWU device. */ 530 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 531 /* @brief Index of port of external pin. */ 532 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 533 /* @brief Number of external pin port on specified port. */ 534 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 535 /* @brief Has external pin 5 connected to LLWU device. */ 536 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 537 /* @brief Index of port of external pin. */ 538 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 539 /* @brief Number of external pin port on specified port. */ 540 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 541 /* @brief Has external pin 6 connected to LLWU device. */ 542 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 543 /* @brief Index of port of external pin. */ 544 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 545 /* @brief Number of external pin port on specified port. */ 546 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 547 /* @brief Has external pin 7 connected to LLWU device. */ 548 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 549 /* @brief Index of port of external pin. */ 550 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 551 /* @brief Number of external pin port on specified port. */ 552 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 553 /* @brief Has external pin 8 connected to LLWU device. */ 554 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 555 /* @brief Index of port of external pin. */ 556 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 557 /* @brief Number of external pin port on specified port. */ 558 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 559 /* @brief Has external pin 9 connected to LLWU device. */ 560 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 561 /* @brief Index of port of external pin. */ 562 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 563 /* @brief Number of external pin port on specified port. */ 564 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 565 /* @brief Has external pin 10 connected to LLWU device. */ 566 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 567 /* @brief Index of port of external pin. */ 568 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 569 /* @brief Number of external pin port on specified port. */ 570 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 571 /* @brief Has external pin 11 connected to LLWU device. */ 572 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 573 /* @brief Index of port of external pin. */ 574 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 575 /* @brief Number of external pin port on specified port. */ 576 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 577 /* @brief Has external pin 12 connected to LLWU device. */ 578 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 579 /* @brief Index of port of external pin. */ 580 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 581 /* @brief Number of external pin port on specified port. */ 582 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 583 /* @brief Has external pin 13 connected to LLWU device. */ 584 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 585 /* @brief Index of port of external pin. */ 586 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 587 /* @brief Number of external pin port on specified port. */ 588 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 589 /* @brief Has external pin 14 connected to LLWU device. */ 590 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 591 /* @brief Index of port of external pin. */ 592 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 593 /* @brief Number of external pin port on specified port. */ 594 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 595 /* @brief Has external pin 15 connected to LLWU device. */ 596 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 597 /* @brief Index of port of external pin. */ 598 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 599 /* @brief Number of external pin port on specified port. */ 600 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 601 /* @brief Has external pin 16 connected to LLWU device. */ 602 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 603 /* @brief Index of port of external pin. */ 604 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 605 /* @brief Number of external pin port on specified port. */ 606 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 607 /* @brief Has external pin 17 connected to LLWU device. */ 608 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 609 /* @brief Index of port of external pin. */ 610 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 611 /* @brief Number of external pin port on specified port. */ 612 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 613 /* @brief Has external pin 18 connected to LLWU device. */ 614 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 615 /* @brief Index of port of external pin. */ 616 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 617 /* @brief Number of external pin port on specified port. */ 618 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 619 /* @brief Has external pin 19 connected to LLWU device. */ 620 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 621 /* @brief Index of port of external pin. */ 622 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 623 /* @brief Number of external pin port on specified port. */ 624 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 625 /* @brief Has external pin 20 connected to LLWU device. */ 626 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 627 /* @brief Index of port of external pin. */ 628 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 629 /* @brief Number of external pin port on specified port. */ 630 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 631 /* @brief Has external pin 21 connected to LLWU device. */ 632 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 633 /* @brief Index of port of external pin. */ 634 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 635 /* @brief Number of external pin port on specified port. */ 636 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 637 /* @brief Has external pin 22 connected to LLWU device. */ 638 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 639 /* @brief Index of port of external pin. */ 640 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 641 /* @brief Number of external pin port on specified port. */ 642 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 643 /* @brief Has external pin 23 connected to LLWU device. */ 644 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 645 /* @brief Index of port of external pin. */ 646 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 647 /* @brief Number of external pin port on specified port. */ 648 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 649 /* @brief Has external pin 24 connected to LLWU device. */ 650 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 651 /* @brief Index of port of external pin. */ 652 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 653 /* @brief Number of external pin port on specified port. */ 654 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 655 /* @brief Has external pin 25 connected to LLWU device. */ 656 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 657 /* @brief Index of port of external pin. */ 658 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 659 /* @brief Number of external pin port on specified port. */ 660 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 661 /* @brief Has external pin 26 connected to LLWU device. */ 662 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 663 /* @brief Index of port of external pin. */ 664 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 665 /* @brief Number of external pin port on specified port. */ 666 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 667 /* @brief Has external pin 27 connected to LLWU device. */ 668 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 669 /* @brief Index of port of external pin. */ 670 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 671 /* @brief Number of external pin port on specified port. */ 672 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 673 /* @brief Has external pin 28 connected to LLWU device. */ 674 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 675 /* @brief Index of port of external pin. */ 676 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 677 /* @brief Number of external pin port on specified port. */ 678 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 679 /* @brief Has external pin 29 connected to LLWU device. */ 680 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 681 /* @brief Index of port of external pin. */ 682 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 683 /* @brief Number of external pin port on specified port. */ 684 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 685 /* @brief Has external pin 30 connected to LLWU device. */ 686 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 687 /* @brief Index of port of external pin. */ 688 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 689 /* @brief Number of external pin port on specified port. */ 690 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 691 /* @brief Has external pin 31 connected to LLWU device. */ 692 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 693 /* @brief Index of port of external pin. */ 694 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 695 /* @brief Number of external pin port on specified port. */ 696 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 697 /* @brief Has internal module 0 connected to LLWU device. */ 698 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 699 /* @brief Has internal module 1 connected to LLWU device. */ 700 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 701 /* @brief Has internal module 2 connected to LLWU device. */ 702 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 703 /* @brief Has internal module 3 connected to LLWU device. */ 704 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 705 /* @brief Has internal module 4 connected to LLWU device. */ 706 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 707 /* @brief Has internal module 5 connected to LLWU device. */ 708 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 709 /* @brief Has internal module 6 connected to LLWU device. */ 710 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 711 /* @brief Has internal module 7 connected to LLWU device. */ 712 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 713 /* @brief Has Version ID Register (LLWU_VERID). */ 714 #define FSL_FEATURE_LLWU_HAS_VERID (0) 715 /* @brief Has Parameter Register (LLWU_PARAM). */ 716 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 717 /* @brief Width of registers of the LLWU. */ 718 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 719 /* @brief Has DMA Enable register (LLWU_DE). */ 720 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 721 #elif defined(CPU_MKV31F128VLL10) 722 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 723 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 724 /* @brief Has pins 8-15 connected to LLWU device. */ 725 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 726 /* @brief Maximum number of internal modules connected to LLWU device. */ 727 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 728 /* @brief Number of digital filters. */ 729 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 730 /* @brief Has MF register. */ 731 #define FSL_FEATURE_LLWU_HAS_MF (0) 732 /* @brief Has PF register. */ 733 #define FSL_FEATURE_LLWU_HAS_PF (0) 734 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 735 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 736 /* @brief Has no internal module wakeup flag register. */ 737 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 738 /* @brief Has external pin 0 connected to LLWU device. */ 739 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 740 /* @brief Index of port of external pin. */ 741 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 742 /* @brief Number of external pin port on specified port. */ 743 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 744 /* @brief Has external pin 1 connected to LLWU device. */ 745 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 746 /* @brief Index of port of external pin. */ 747 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 748 /* @brief Number of external pin port on specified port. */ 749 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 750 /* @brief Has external pin 2 connected to LLWU device. */ 751 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 752 /* @brief Index of port of external pin. */ 753 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 754 /* @brief Number of external pin port on specified port. */ 755 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 756 /* @brief Has external pin 3 connected to LLWU device. */ 757 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 758 /* @brief Index of port of external pin. */ 759 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 760 /* @brief Number of external pin port on specified port. */ 761 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 762 /* @brief Has external pin 4 connected to LLWU device. */ 763 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 764 /* @brief Index of port of external pin. */ 765 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 766 /* @brief Number of external pin port on specified port. */ 767 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 768 /* @brief Has external pin 5 connected to LLWU device. */ 769 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 770 /* @brief Index of port of external pin. */ 771 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 772 /* @brief Number of external pin port on specified port. */ 773 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 774 /* @brief Has external pin 6 connected to LLWU device. */ 775 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 776 /* @brief Index of port of external pin. */ 777 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 778 /* @brief Number of external pin port on specified port. */ 779 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 780 /* @brief Has external pin 7 connected to LLWU device. */ 781 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 782 /* @brief Index of port of external pin. */ 783 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 784 /* @brief Number of external pin port on specified port. */ 785 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 786 /* @brief Has external pin 8 connected to LLWU device. */ 787 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 788 /* @brief Index of port of external pin. */ 789 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 790 /* @brief Number of external pin port on specified port. */ 791 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 792 /* @brief Has external pin 9 connected to LLWU device. */ 793 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 794 /* @brief Index of port of external pin. */ 795 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 796 /* @brief Number of external pin port on specified port. */ 797 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 798 /* @brief Has external pin 10 connected to LLWU device. */ 799 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 800 /* @brief Index of port of external pin. */ 801 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 802 /* @brief Number of external pin port on specified port. */ 803 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 804 /* @brief Has external pin 11 connected to LLWU device. */ 805 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 806 /* @brief Index of port of external pin. */ 807 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 808 /* @brief Number of external pin port on specified port. */ 809 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 810 /* @brief Has external pin 12 connected to LLWU device. */ 811 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 812 /* @brief Index of port of external pin. */ 813 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 814 /* @brief Number of external pin port on specified port. */ 815 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 816 /* @brief Has external pin 13 connected to LLWU device. */ 817 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 818 /* @brief Index of port of external pin. */ 819 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 820 /* @brief Number of external pin port on specified port. */ 821 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 822 /* @brief Has external pin 14 connected to LLWU device. */ 823 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 824 /* @brief Index of port of external pin. */ 825 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 826 /* @brief Number of external pin port on specified port. */ 827 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 828 /* @brief Has external pin 15 connected to LLWU device. */ 829 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 830 /* @brief Index of port of external pin. */ 831 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 832 /* @brief Number of external pin port on specified port. */ 833 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 834 /* @brief Has external pin 16 connected to LLWU device. */ 835 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 836 /* @brief Index of port of external pin. */ 837 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 838 /* @brief Number of external pin port on specified port. */ 839 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 840 /* @brief Has external pin 17 connected to LLWU device. */ 841 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 842 /* @brief Index of port of external pin. */ 843 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 844 /* @brief Number of external pin port on specified port. */ 845 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 846 /* @brief Has external pin 18 connected to LLWU device. */ 847 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 848 /* @brief Index of port of external pin. */ 849 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 850 /* @brief Number of external pin port on specified port. */ 851 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 852 /* @brief Has external pin 19 connected to LLWU device. */ 853 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 854 /* @brief Index of port of external pin. */ 855 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 856 /* @brief Number of external pin port on specified port. */ 857 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 858 /* @brief Has external pin 20 connected to LLWU device. */ 859 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 860 /* @brief Index of port of external pin. */ 861 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 862 /* @brief Number of external pin port on specified port. */ 863 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 864 /* @brief Has external pin 21 connected to LLWU device. */ 865 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 866 /* @brief Index of port of external pin. */ 867 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 868 /* @brief Number of external pin port on specified port. */ 869 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 870 /* @brief Has external pin 22 connected to LLWU device. */ 871 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 872 /* @brief Index of port of external pin. */ 873 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 874 /* @brief Number of external pin port on specified port. */ 875 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 876 /* @brief Has external pin 23 connected to LLWU device. */ 877 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 878 /* @brief Index of port of external pin. */ 879 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 880 /* @brief Number of external pin port on specified port. */ 881 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 882 /* @brief Has external pin 24 connected to LLWU device. */ 883 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 884 /* @brief Index of port of external pin. */ 885 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 886 /* @brief Number of external pin port on specified port. */ 887 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 888 /* @brief Has external pin 25 connected to LLWU device. */ 889 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 890 /* @brief Index of port of external pin. */ 891 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 892 /* @brief Number of external pin port on specified port. */ 893 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 894 /* @brief Has external pin 26 connected to LLWU device. */ 895 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 896 /* @brief Index of port of external pin. */ 897 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 898 /* @brief Number of external pin port on specified port. */ 899 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 900 /* @brief Has external pin 27 connected to LLWU device. */ 901 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 902 /* @brief Index of port of external pin. */ 903 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 904 /* @brief Number of external pin port on specified port. */ 905 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 906 /* @brief Has external pin 28 connected to LLWU device. */ 907 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 908 /* @brief Index of port of external pin. */ 909 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 910 /* @brief Number of external pin port on specified port. */ 911 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 912 /* @brief Has external pin 29 connected to LLWU device. */ 913 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 914 /* @brief Index of port of external pin. */ 915 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 916 /* @brief Number of external pin port on specified port. */ 917 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 918 /* @brief Has external pin 30 connected to LLWU device. */ 919 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 920 /* @brief Index of port of external pin. */ 921 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 922 /* @brief Number of external pin port on specified port. */ 923 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 924 /* @brief Has external pin 31 connected to LLWU device. */ 925 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 926 /* @brief Index of port of external pin. */ 927 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 928 /* @brief Number of external pin port on specified port. */ 929 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 930 /* @brief Has internal module 0 connected to LLWU device. */ 931 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 932 /* @brief Has internal module 1 connected to LLWU device. */ 933 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 934 /* @brief Has internal module 2 connected to LLWU device. */ 935 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 936 /* @brief Has internal module 3 connected to LLWU device. */ 937 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 938 /* @brief Has internal module 4 connected to LLWU device. */ 939 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 940 /* @brief Has internal module 5 connected to LLWU device. */ 941 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 942 /* @brief Has internal module 6 connected to LLWU device. */ 943 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 944 /* @brief Has internal module 7 connected to LLWU device. */ 945 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 946 /* @brief Has Version ID Register (LLWU_VERID). */ 947 #define FSL_FEATURE_LLWU_HAS_VERID (0) 948 /* @brief Has Parameter Register (LLWU_PARAM). */ 949 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 950 /* @brief Width of registers of the LLWU. */ 951 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 952 /* @brief Has DMA Enable register (LLWU_DE). */ 953 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 954 #endif /* defined(CPU_MKV31F128VLH10) */ 955 956 /* LPTMR module features */ 957 958 /* @brief Has shared interrupt handler with another LPTMR module. */ 959 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 960 /* @brief Whether LPTMR counter is 32 bits width. */ 961 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 962 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 963 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 964 965 /* LPUART module features */ 966 967 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 968 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 969 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 970 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 971 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 972 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 973 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 974 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 975 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 976 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 977 /* @brief Has 32-bit register MODIR */ 978 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 979 /* @brief Hardware flow control (RTS, CTS) is supported. */ 980 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 981 /* @brief Infrared (modulation) is supported. */ 982 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 983 /* @brief 2 bits long stop bit is available. */ 984 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 985 /* @brief If 10-bit mode is supported. */ 986 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 987 /* @brief If 7-bit mode is supported. */ 988 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 989 /* @brief Baud rate fine adjustment is available. */ 990 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 991 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 992 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 993 /* @brief Baud rate oversampling is available. */ 994 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 995 /* @brief Baud rate oversampling is available. */ 996 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 997 /* @brief Peripheral type. */ 998 #define FSL_FEATURE_LPUART_IS_SCI (1) 999 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1000 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 1001 /* @brief Supports two match addresses to filter incoming frames. */ 1002 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 1003 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1004 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 1005 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1006 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 1007 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1008 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 1009 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1010 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 1011 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1012 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1013 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1014 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1015 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1016 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1017 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1018 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1019 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1020 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1021 /* @brief Has separate DMA RX and TX requests. */ 1022 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1023 /* @brief Has separate RX and TX interrupts. */ 1024 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1025 /* @brief Has LPAURT_PARAM. */ 1026 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 1027 /* @brief Has LPUART_VERID. */ 1028 #define FSL_FEATURE_LPUART_HAS_VERID (0) 1029 /* @brief Has LPUART_GLOBAL. */ 1030 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 1031 /* @brief Has LPUART_PINCFG. */ 1032 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 1033 1034 /* MCG module features */ 1035 1036 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1037 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) 1038 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1039 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) 1040 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1041 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) 1042 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1043 #define FSL_FEATURE_MCG_PLL_REF_MIN (0) 1044 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1045 #define FSL_FEATURE_MCG_PLL_REF_MAX (0) 1046 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1047 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1048 /* @brief FRDIV supports 1280. */ 1049 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1050 /* @brief FRDIV supports 1536. */ 1051 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1052 /* @brief MCGFFCLK divider. */ 1053 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1054 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1055 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1056 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1057 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1058 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1059 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1060 /* @brief Has 48MHz internal oscillator. */ 1061 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 1062 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1063 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1064 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1065 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1066 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1067 #define FSL_FEATURE_MCG_HAS_LOLRE (0) 1068 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1069 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1070 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1071 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1072 /* @brief TBD */ 1073 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1074 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1075 #define FSL_FEATURE_MCG_HAS_PLL (0) 1076 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1077 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) 1078 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1079 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) 1080 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1081 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1082 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1083 #define FSL_FEATURE_MCG_HAS_FLL (1) 1084 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1085 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1086 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1087 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1088 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1089 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) 1090 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1091 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1092 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1093 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1094 /* @brief Has external clock monitor (register bit C6[CME]). */ 1095 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1096 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1097 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1098 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1099 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1100 /* @brief Has PEI mode or PBI mode. */ 1101 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1102 /* @brief Reset clock mode is BLPI. */ 1103 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1104 1105 /* interrupt module features */ 1106 1107 /* @brief Lowest interrupt request number. */ 1108 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1109 /* @brief Highest interrupt request number. */ 1110 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) 1111 1112 /* OSC module features */ 1113 1114 /* @brief Has OSC1 external oscillator. */ 1115 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1116 /* @brief Has OSC0 external oscillator. */ 1117 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1118 /* @brief Has OSC external oscillator (without index). */ 1119 #define FSL_FEATURE_OSC_HAS_OSC (1) 1120 /* @brief Number of OSC external oscillators. */ 1121 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1122 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1123 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 1124 1125 /* PDB module features */ 1126 1127 /* @brief Has DAC support. */ 1128 #define FSL_FEATURE_PDB_HAS_DAC (1) 1129 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1130 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1131 /* @brief PDB channel number). */ 1132 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1133 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1134 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1135 /* @brief DAC interval trigger number). */ 1136 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 1137 /* @brief Pulse out number). */ 1138 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1139 1140 /* PIT module features */ 1141 1142 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1143 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1144 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1145 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 1146 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1147 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1148 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1149 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1150 /* @brief Has timer enable control. */ 1151 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1152 1153 /* PMC module features */ 1154 1155 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1156 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1157 /* @brief Has Bandgap Buffer Enable. */ 1158 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1159 /* @brief Has Bandgap Buffer Drive Select. */ 1160 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1161 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1162 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1163 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1164 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1165 /* @brief Has LPO. */ 1166 #define FSL_FEATURE_PMC_HAS_LPO (0) 1167 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1168 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1169 /* @brief Has acknowledge isolation support. */ 1170 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1171 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1172 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1173 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1174 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1175 /* @brief Has PMC_HVDSC1. */ 1176 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1177 /* @brief Has PMC_PARAM. */ 1178 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1179 /* @brief Has PMC_VERID. */ 1180 #define FSL_FEATURE_PMC_HAS_VERID (0) 1181 1182 /* PORT module features */ 1183 1184 /* @brief Has control lock (register bit PCR[LK]). */ 1185 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1186 /* @brief Has open drain control (register bit PCR[ODE]). */ 1187 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1188 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1189 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1190 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1191 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1192 /* @brief Has pull resistor selection available. */ 1193 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1194 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1195 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1196 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1197 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1198 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1199 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1200 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1201 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1202 /* @brief Has separate drive strength register (HDRVE). */ 1203 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1204 /* @brief Has glitch filter (register IOFLT). */ 1205 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1206 /* @brief Defines width of PCR[MUX] field. */ 1207 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1208 /* @brief Has dedicated interrupt vector. */ 1209 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1210 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1211 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1212 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1213 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1214 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1215 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1216 1217 /* RCM module features */ 1218 1219 /* @brief Has Loss-of-Lock Reset support. */ 1220 #define FSL_FEATURE_RCM_HAS_LOL (0) 1221 /* @brief Has Loss-of-Clock Reset support. */ 1222 #define FSL_FEATURE_RCM_HAS_LOC (1) 1223 /* @brief Has JTAG generated Reset support. */ 1224 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1225 /* @brief Has EzPort generated Reset support. */ 1226 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 1227 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1228 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 1229 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1230 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1231 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1232 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1233 /* @brief Has Version ID Register (RCM_VERID). */ 1234 #define FSL_FEATURE_RCM_HAS_VERID (0) 1235 /* @brief Has Parameter Register (RCM_PARAM). */ 1236 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1237 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1238 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1239 /* @brief Width of registers of the RCM. */ 1240 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1241 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1242 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1243 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1244 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1245 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1246 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1247 1248 /* SIM module features */ 1249 1250 /* @brief Has USB FS divider. */ 1251 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1252 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1253 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1254 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1255 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1256 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1257 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) 1258 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1259 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1260 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1261 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1262 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1263 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1264 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1265 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1266 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1267 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1268 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1269 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1270 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1271 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1272 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1273 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1274 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1275 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1276 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1277 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1278 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1279 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) 1280 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1281 #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) 1282 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1283 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1284 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1285 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1286 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1287 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1288 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1289 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1290 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1291 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1292 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1293 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1294 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1295 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1296 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1297 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1298 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1299 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1300 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1301 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1302 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1303 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1304 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1305 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1306 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1307 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1308 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1309 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1310 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1311 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1312 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1313 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1314 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1315 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1316 /* @brief Has FTM module(s) configuration. */ 1317 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1318 /* @brief Number of FTM modules. */ 1319 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) 1320 /* @brief Number of FTM triggers with selectable source. */ 1321 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1322 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1323 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1324 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1325 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1326 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1327 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1328 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1329 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1330 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1331 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1332 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1333 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1334 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1335 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1336 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1337 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1338 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1339 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1340 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1341 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1342 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1343 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1344 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1345 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1346 /* @brief Has TPM module(s) configuration. */ 1347 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1348 /* @brief The highest TPM module index. */ 1349 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1350 /* @brief Has TPM module with index 0. */ 1351 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1352 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1353 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1354 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1355 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1356 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1357 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1358 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1359 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1360 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1361 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1362 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1363 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1364 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1365 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1366 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1367 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1368 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1369 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1370 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1371 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1372 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1373 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1374 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1375 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1376 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1377 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1378 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1379 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1380 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1381 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1382 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1383 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1384 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1385 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1386 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1387 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1388 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1389 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) 1390 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1391 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1392 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1393 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1394 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1395 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1396 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1397 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1398 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1399 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1400 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1401 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1402 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1403 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1404 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1405 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1406 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1407 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) 1408 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1409 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1410 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1411 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1412 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1413 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1414 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1415 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1416 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1417 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1418 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1419 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1420 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1421 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1422 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1423 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1424 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1425 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1426 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1427 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1428 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1429 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1430 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1431 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1432 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1433 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1434 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1435 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1436 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1437 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1438 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1439 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1440 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1441 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1442 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1443 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1444 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1445 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1446 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1447 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1448 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1449 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1450 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1451 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) 1452 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1453 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1454 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1455 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1456 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1457 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1458 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1459 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1460 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1461 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1462 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1463 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1464 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1465 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1466 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1467 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1468 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1469 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1470 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1471 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1472 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1473 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1474 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1475 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1476 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1477 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1478 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1479 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1480 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1481 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1482 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1483 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1484 /* @brief Has miscellanious control register (register MCR). */ 1485 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1486 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1487 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1488 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1489 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1490 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1491 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1492 /* @brief Has UIDH registers. */ 1493 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1494 /* @brief Has UIDM registers. */ 1495 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1496 1497 /* SMC module features */ 1498 1499 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1500 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1501 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1502 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1503 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1504 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1505 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1506 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1507 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1508 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1509 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1510 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1511 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1512 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1513 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1514 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1515 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1516 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1517 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1518 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1519 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1520 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1521 /* @brief Has stop submode. */ 1522 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1523 /* @brief Has stop submode 0(VLLS0). */ 1524 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1525 /* @brief Has stop submode 1(VLLS1). */ 1526 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1527 /* @brief Has stop submode 2(VLLS2). */ 1528 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1529 /* @brief Has SMC_PARAM. */ 1530 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1531 /* @brief Has SMC_VERID. */ 1532 #define FSL_FEATURE_SMC_HAS_VERID (0) 1533 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1534 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1535 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1536 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1537 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1538 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1539 /* @brief Width of SMC registers. */ 1540 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1541 1542 /* DSPI module features */ 1543 1544 #if defined(CPU_MKV31F128VLH10) 1545 /* @brief Receive/transmit FIFO size in number of items. */ 1546 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1547 (((x) == SPI0) ? (4) : \ 1548 (((x) == SPI1) ? (1) : (-1))) 1549 /* @brief Maximum transfer data width in bits. */ 1550 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1551 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1552 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1553 /* @brief Number of chip select pins. */ 1554 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) 1555 /* @brief Number of CTAR registers. */ 1556 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1557 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1558 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1559 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1560 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1561 /* @brief Has 16-bit data transfer support. */ 1562 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1563 /* @brief Has separate DMA RX and TX requests. */ 1564 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1565 (((x) == SPI0) ? (1) : \ 1566 (((x) == SPI1) ? (0) : (-1))) 1567 #elif defined(CPU_MKV31F128VLL10) 1568 /* @brief Receive/transmit FIFO size in number of items. */ 1569 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1570 (((x) == SPI0) ? (4) : \ 1571 (((x) == SPI1) ? (1) : (-1))) 1572 /* @brief Maximum transfer data width in bits. */ 1573 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1574 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1575 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1576 /* @brief Number of chip select pins. */ 1577 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1578 /* @brief Number of CTAR registers. */ 1579 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1580 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1581 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1582 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1583 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1584 /* @brief Has 16-bit data transfer support. */ 1585 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1586 /* @brief Has separate DMA RX and TX requests. */ 1587 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1588 (((x) == SPI0) ? (1) : \ 1589 (((x) == SPI1) ? (0) : (-1))) 1590 #endif /* defined(CPU_MKV31F128VLH10) */ 1591 1592 /* SysTick module features */ 1593 1594 /* @brief Systick has external reference clock. */ 1595 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1596 /* @brief Systick external reference clock is core clock divided by this value. */ 1597 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1598 1599 /* UART module features */ 1600 1601 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1602 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1603 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1604 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1605 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1606 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1607 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1608 #define FSL_FEATURE_UART_HAS_FIFO (1) 1609 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1610 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1611 /* @brief Infrared (modulation) is supported. */ 1612 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1613 /* @brief 2 bits long stop bit is available. */ 1614 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1615 /* @brief If 10-bit mode is supported. */ 1616 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1617 /* @brief Baud rate fine adjustment is available. */ 1618 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1619 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1620 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1621 /* @brief Baud rate oversampling is available. */ 1622 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1623 /* @brief Baud rate oversampling is available. */ 1624 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1625 /* @brief Peripheral type. */ 1626 #define FSL_FEATURE_UART_IS_SCI (0) 1627 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1628 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1629 (((x) == UART0) ? (8) : \ 1630 (((x) == UART1) ? (1) : \ 1631 (((x) == UART2) ? (1) : (-1)))) 1632 /* @brief Supports two match addresses to filter incoming frames. */ 1633 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1634 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1635 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1636 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1637 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1638 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1639 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1640 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1641 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1642 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1643 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1644 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1645 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1646 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1647 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1648 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1649 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1650 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1651 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1652 /* @brief Has separate DMA RX and TX requests. */ 1653 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1654 1655 /* VREF module features */ 1656 1657 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1658 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1659 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1660 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1661 /* @brief If high/low buffer mode supported */ 1662 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1663 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1664 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1665 /* @brief Has VREF_TRM4. */ 1666 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1667 1668 /* WDOG module features */ 1669 1670 /* @brief Watchdog is available. */ 1671 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1672 /* @brief Has Wait mode support. */ 1673 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1674 1675 #endif /* _MKV31F12810_FEATURES_H_ */ 1676 1677
