1 /* 2 ** ################################################################### 3 ** Version: rev. 1.3, 2015-06-08 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2014-12-14) 20 ** Initial version. 21 ** - rev. 1.1 (2015-01-21) 22 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 23 ** - rev. 1.2 (2015-05-25) 24 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 25 ** - rev. 1.3 (2015-06-08) 26 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 27 ** 28 ** ################################################################### 29 */ 30 31 #ifndef _MKV10Z1287_FEATURES_H_ 32 #define _MKV10Z1287_FEATURES_H_ 33 34 /* SOC module features */ 35 36 /* @brief ADC16 availability on the SoC. */ 37 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 38 /* @brief CMP availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CMP_COUNT (2) 40 /* @brief CRC availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CRC_COUNT (1) 42 /* @brief DAC availability on the SoC. */ 43 #define FSL_FEATURE_SOC_DAC_COUNT (1) 44 /* @brief EDMA availability on the SoC. */ 45 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 46 /* @brief DMAMUX availability on the SoC. */ 47 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 48 /* @brief DSPI availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DSPI_COUNT (1) 50 /* @brief EWM availability on the SoC. */ 51 #define FSL_FEATURE_SOC_EWM_COUNT (1) 52 /* @brief FGPIO availability on the SoC. */ 53 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 54 /* @brief FTFA availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 56 /* @brief FTM availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FTM_COUNT (6) 58 /* @brief GPIO availability on the SoC. */ 59 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 60 /* @brief I2C availability on the SoC. */ 61 #define FSL_FEATURE_SOC_I2C_COUNT (1) 62 /* @brief LLWU availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 64 /* @brief LPTMR availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 66 /* @brief MCG availability on the SoC. */ 67 #define FSL_FEATURE_SOC_MCG_COUNT (1) 68 /* @brief MCM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MCM_COUNT (1) 70 /* @brief MMDVSQ availability on the SoC. */ 71 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) 72 /* @brief MTB availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MTB_COUNT (1) 74 /* @brief MTBDWT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 76 /* @brief OSC availability on the SoC. */ 77 #define FSL_FEATURE_SOC_OSC_COUNT (1) 78 /* @brief PDB availability on the SoC. */ 79 #define FSL_FEATURE_SOC_PDB_COUNT (2) 80 /* @brief PMC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_PMC_COUNT (1) 82 /* @brief PORT availability on the SoC. */ 83 #define FSL_FEATURE_SOC_PORT_COUNT (5) 84 /* @brief RCM availability on the SoC. */ 85 #define FSL_FEATURE_SOC_RCM_COUNT (1) 86 /* @brief ROM availability on the SoC. */ 87 #define FSL_FEATURE_SOC_ROM_COUNT (1) 88 /* @brief SIM availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SIM_COUNT (1) 90 /* @brief SMC availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SMC_COUNT (1) 92 /* @brief UART availability on the SoC. */ 93 #define FSL_FEATURE_SOC_UART_COUNT (2) 94 /* @brief WDOG availability on the SoC. */ 95 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 96 97 /* ADC16 module features */ 98 99 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 100 #define FSL_FEATURE_ADC16_HAS_PGA (0) 101 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 102 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 103 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 104 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 105 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 106 #define FSL_FEATURE_ADC16_HAS_DMA (1) 107 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 108 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 109 /* @brief Has FIFO (bit SC4[AFDEP]). */ 110 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 111 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 112 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 113 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 114 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (0) 115 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 116 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 117 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 118 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 119 /* @brief Has HW averaging (bit SC3[AVGE]). */ 120 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 121 /* @brief Has offset correction (register OFS). */ 122 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 123 /* @brief Maximum ADC resolution. */ 124 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 125 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 126 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 127 128 /* CMP module features */ 129 130 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 131 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 132 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 133 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 134 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 135 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 136 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 137 #define FSL_FEATURE_CMP_HAS_DMA (1) 138 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 139 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 140 /* @brief Has DAC Test function in CMP (register DACTEST). */ 141 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 142 143 /* CRC module features */ 144 145 /* @brief Has data register with name CRC */ 146 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 147 148 /* DAC module features */ 149 150 /* @brief Define the size of hardware buffer */ 151 #define FSL_FEATURE_DAC_BUFFER_SIZE (2) 152 /* @brief Define whether the buffer supports watermark event detection or not. */ 153 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 154 /* @brief Define whether the buffer supports watermark selection detection or not. */ 155 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0) 156 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 157 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0) 158 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 159 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0) 160 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 161 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0) 162 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 163 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0) 164 /* @brief Define whether FIFO buffer mode is available or not. */ 165 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 166 /* @brief Define whether swing buffer mode is available or not.. */ 167 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) 168 169 /* EDMA module features */ 170 171 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 172 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) 173 /* @brief Total number of DMA channels on all modules. */ 174 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8) 175 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 176 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 177 /* @brief Has DMA_Error interrupt vector. */ 178 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 179 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 180 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8) 181 /* @brief Channel IRQ entry shared offset. */ 182 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4) 183 /* @brief If 8 bytes transfer supported. */ 184 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 185 /* @brief If 16 bytes transfer supported. */ 186 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 187 188 /* DMAMUX module features */ 189 190 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 191 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8) 192 /* @brief Total number of DMA channels on all modules. */ 193 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (8) 194 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 195 #define FSL_FEATURE_DMAMUX_HAS_TRIG (0) 196 /* @brief Register CHCFGn width. */ 197 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 198 199 /* EWM module features */ 200 201 /* @brief Has clock select (register CLKCTRL). */ 202 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 203 /* @brief Has clock prescaler (register CLKPRESCALER). */ 204 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 205 206 /* FGPIO module features */ 207 208 /* No feature definitions */ 209 210 /* FLASH module features */ 211 212 #if defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || defined(CPU_MKV10Z128VLH7) 213 /* @brief Is of type FTFA. */ 214 #define FSL_FEATURE_FLASH_IS_FTFA (1) 215 /* @brief Is of type FTFE. */ 216 #define FSL_FEATURE_FLASH_IS_FTFE (0) 217 /* @brief Is of type FTFL. */ 218 #define FSL_FEATURE_FLASH_IS_FTFL (0) 219 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 220 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 221 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 222 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 223 /* @brief Has EEPROM region protection (register FEPROT). */ 224 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 225 /* @brief Has data flash region protection (register FDPROT). */ 226 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 227 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 228 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 229 /* @brief Has flash cache control in FMC module. */ 230 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 231 /* @brief Has flash cache control in MCM module. */ 232 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 233 /* @brief Has flash cache control in MSCM module. */ 234 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 235 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 236 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 237 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 238 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 239 /* @brief P-Flash start address. */ 240 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 241 /* @brief P-Flash block count. */ 242 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 243 /* @brief P-Flash block size. */ 244 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 245 /* @brief P-Flash sector size. */ 246 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 247 /* @brief P-Flash write unit size. */ 248 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 249 /* @brief P-Flash data path width. */ 250 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 251 /* @brief P-Flash block swap feature. */ 252 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 253 /* @brief P-Flash protection region count. */ 254 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 255 /* @brief Has FlexNVM memory. */ 256 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 257 /* @brief Has FlexNVM alias. */ 258 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 259 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 260 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 261 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 262 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 263 /* @brief FlexNVM block count. */ 264 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 265 /* @brief FlexNVM block size. */ 266 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 267 /* @brief FlexNVM sector size. */ 268 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 269 /* @brief FlexNVM write unit size. */ 270 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 271 /* @brief FlexNVM data path width. */ 272 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 273 /* @brief Has FlexRAM memory. */ 274 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 275 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 276 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 277 /* @brief FlexRAM size. */ 278 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 279 /* @brief Has 0x00 Read 1s Block command. */ 280 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 281 /* @brief Has 0x01 Read 1s Section command. */ 282 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 283 /* @brief Has 0x02 Program Check command. */ 284 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 285 /* @brief Has 0x03 Read Resource command. */ 286 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 287 /* @brief Has 0x06 Program Longword command. */ 288 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 289 /* @brief Has 0x07 Program Phrase command. */ 290 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 291 /* @brief Has 0x08 Erase Flash Block command. */ 292 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 293 /* @brief Has 0x09 Erase Flash Sector command. */ 294 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 295 /* @brief Has 0x0B Program Section command. */ 296 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 297 /* @brief Has 0x40 Read 1s All Blocks command. */ 298 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 299 /* @brief Has 0x41 Read Once command. */ 300 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 301 /* @brief Has 0x43 Program Once command. */ 302 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 303 /* @brief Has 0x44 Erase All Blocks command. */ 304 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 305 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 306 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 307 /* @brief Has 0x46 Swap Control command. */ 308 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 309 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 310 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 311 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 312 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 313 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 314 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 315 /* @brief Has 0x80 Program Partition command. */ 316 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 317 /* @brief Has 0x81 Set FlexRAM Function command. */ 318 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 319 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 320 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 321 /* @brief P-Flash Erase sector command address alignment. */ 322 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 323 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 324 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 325 /* @brief P-Flash Read resource command address alignment. */ 326 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 327 /* @brief P-Flash Program check command address alignment. */ 328 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 329 /* @brief P-Flash Program check command address alignment. */ 330 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 331 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 332 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 333 /* @brief FlexNVM Erase sector command address alignment. */ 334 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 335 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 336 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 337 /* @brief FlexNVM Read resource command address alignment. */ 338 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 339 /* @brief FlexNVM Program check command address alignment. */ 340 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 341 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 342 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 343 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 344 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 345 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 346 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 347 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 348 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 349 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 350 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 351 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 352 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 353 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 354 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 355 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 356 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 357 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 358 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 359 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 361 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 363 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 365 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 366 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 367 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 368 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 369 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 370 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 371 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 372 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 373 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 374 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 375 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 376 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 377 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 378 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 379 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 381 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 383 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 385 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 387 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 389 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 391 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 393 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 395 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 397 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 398 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 399 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 400 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 401 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 402 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 403 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 404 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 405 #elif defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7) 406 /* @brief Is of type FTFA. */ 407 #define FSL_FEATURE_FLASH_IS_FTFA (1) 408 /* @brief Is of type FTFE. */ 409 #define FSL_FEATURE_FLASH_IS_FTFE (0) 410 /* @brief Is of type FTFL. */ 411 #define FSL_FEATURE_FLASH_IS_FTFL (0) 412 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 413 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 414 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 415 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 416 /* @brief Has EEPROM region protection (register FEPROT). */ 417 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 418 /* @brief Has data flash region protection (register FDPROT). */ 419 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 420 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 421 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 422 /* @brief Has flash cache control in FMC module. */ 423 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 424 /* @brief Has flash cache control in MCM module. */ 425 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 426 /* @brief Has flash cache control in MSCM module. */ 427 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 428 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 429 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 430 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 431 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 432 /* @brief P-Flash start address. */ 433 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 434 /* @brief P-Flash block count. */ 435 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 436 /* @brief P-Flash block size. */ 437 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 438 /* @brief P-Flash sector size. */ 439 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 440 /* @brief P-Flash write unit size. */ 441 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 442 /* @brief P-Flash data path width. */ 443 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 444 /* @brief P-Flash block swap feature. */ 445 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 446 /* @brief P-Flash protection region count. */ 447 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 448 /* @brief Has FlexNVM memory. */ 449 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 450 /* @brief Has FlexNVM alias. */ 451 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 452 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 453 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 454 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 455 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 456 /* @brief FlexNVM block count. */ 457 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 458 /* @brief FlexNVM block size. */ 459 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 460 /* @brief FlexNVM sector size. */ 461 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 462 /* @brief FlexNVM write unit size. */ 463 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 464 /* @brief FlexNVM data path width. */ 465 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 466 /* @brief Has FlexRAM memory. */ 467 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 468 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 469 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 470 /* @brief FlexRAM size. */ 471 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 472 /* @brief Has 0x00 Read 1s Block command. */ 473 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 474 /* @brief Has 0x01 Read 1s Section command. */ 475 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 476 /* @brief Has 0x02 Program Check command. */ 477 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 478 /* @brief Has 0x03 Read Resource command. */ 479 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 480 /* @brief Has 0x06 Program Longword command. */ 481 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 482 /* @brief Has 0x07 Program Phrase command. */ 483 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 484 /* @brief Has 0x08 Erase Flash Block command. */ 485 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 486 /* @brief Has 0x09 Erase Flash Sector command. */ 487 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 488 /* @brief Has 0x0B Program Section command. */ 489 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 490 /* @brief Has 0x40 Read 1s All Blocks command. */ 491 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 492 /* @brief Has 0x41 Read Once command. */ 493 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 494 /* @brief Has 0x43 Program Once command. */ 495 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 496 /* @brief Has 0x44 Erase All Blocks command. */ 497 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 498 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 499 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 500 /* @brief Has 0x46 Swap Control command. */ 501 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 502 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 503 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 504 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 505 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 506 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 507 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 508 /* @brief Has 0x80 Program Partition command. */ 509 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 510 /* @brief Has 0x81 Set FlexRAM Function command. */ 511 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 512 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 513 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 514 /* @brief P-Flash Erase sector command address alignment. */ 515 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 516 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 517 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 518 /* @brief P-Flash Read resource command address alignment. */ 519 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 520 /* @brief P-Flash Program check command address alignment. */ 521 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 522 /* @brief P-Flash Program check command address alignment. */ 523 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 524 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 525 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 526 /* @brief FlexNVM Erase sector command address alignment. */ 527 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 528 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 529 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 530 /* @brief FlexNVM Read resource command address alignment. */ 531 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 532 /* @brief FlexNVM Program check command address alignment. */ 533 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 534 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 535 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 536 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 537 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 538 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 539 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 540 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 541 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 542 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 543 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 544 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 545 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 546 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 547 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 548 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 549 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 550 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 551 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 552 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 553 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 554 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 555 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 556 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 558 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 560 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 562 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 563 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 564 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 565 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 566 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 567 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 568 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 569 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 570 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 571 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 572 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 573 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 574 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 575 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 576 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 577 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 578 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 579 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 580 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 581 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 582 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 583 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 584 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 585 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 586 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 587 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 588 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 590 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 592 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 594 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 595 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 596 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 597 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 598 #endif /* defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || defined(CPU_MKV10Z128VLH7) */ 599 600 /* FTM module features */ 601 602 /* @brief Number of channels. */ 603 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 604 (((x) == FTM0) ? (6) : \ 605 (((x) == FTM1) ? (2) : \ 606 (((x) == FTM2) ? (2) : \ 607 (((x) == FTM3) ? (6) : \ 608 (((x) == FTM4) ? (2) : \ 609 (((x) == FTM5) ? (2) : (-1))))))) 610 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 611 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 612 /* @brief Has extended deadtime value. */ 613 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 614 /* @brief Enable pwm output for the module. */ 615 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 616 /* @brief Has half-cycle reload for the module. */ 617 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 618 /* @brief Has reload interrupt. */ 619 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 620 /* @brief Has reload initialization trigger. */ 621 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 622 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 623 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 624 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 625 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 626 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 627 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 628 /* @brief Has no QDCTRL. */ 629 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 630 /* @brief If instance has only TPM function. */ 631 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 632 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 633 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0) 634 635 /* GPIO module features */ 636 637 /* @brief Has GPIO attribute checker register (GACR). */ 638 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 639 640 /* I2C module features */ 641 642 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 643 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 644 /* @brief Maximum supported baud rate in kilobit per second. */ 645 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 646 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 647 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 648 /* @brief Has DMA support (register bit C1[DMAEN]). */ 649 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 650 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 651 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 652 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 653 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 654 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 655 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 656 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 657 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 658 /* @brief Has control of the drive capability of the I2C pins. */ 659 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 660 /* @brief Has double buffering support (register S2). */ 661 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 662 /* @brief Has double buffer enable. */ 663 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 664 665 /* LLWU module features */ 666 667 #if defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) 668 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 669 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 670 /* @brief Has pins 8-15 connected to LLWU device. */ 671 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 672 /* @brief Maximum number of internal modules connected to LLWU device. */ 673 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 674 /* @brief Number of digital filters. */ 675 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 676 /* @brief Has MF register. */ 677 #define FSL_FEATURE_LLWU_HAS_MF (1) 678 /* @brief Has PF register. */ 679 #define FSL_FEATURE_LLWU_HAS_PF (1) 680 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 681 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 682 /* @brief Has no internal module wakeup flag register. */ 683 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 684 /* @brief Has external pin 0 connected to LLWU device. */ 685 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 686 /* @brief Index of port of external pin. */ 687 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 688 /* @brief Number of external pin port on specified port. */ 689 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 690 /* @brief Has external pin 1 connected to LLWU device. */ 691 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 692 /* @brief Index of port of external pin. */ 693 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 694 /* @brief Number of external pin port on specified port. */ 695 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 696 /* @brief Has external pin 2 connected to LLWU device. */ 697 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 698 /* @brief Index of port of external pin. */ 699 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 700 /* @brief Number of external pin port on specified port. */ 701 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 702 /* @brief Has external pin 3 connected to LLWU device. */ 703 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 704 /* @brief Index of port of external pin. */ 705 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 706 /* @brief Number of external pin port on specified port. */ 707 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 708 /* @brief Has external pin 4 connected to LLWU device. */ 709 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 710 /* @brief Index of port of external pin. */ 711 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 712 /* @brief Number of external pin port on specified port. */ 713 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 714 /* @brief Has external pin 5 connected to LLWU device. */ 715 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 716 /* @brief Index of port of external pin. */ 717 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 718 /* @brief Number of external pin port on specified port. */ 719 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 720 /* @brief Has external pin 6 connected to LLWU device. */ 721 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 722 /* @brief Index of port of external pin. */ 723 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 724 /* @brief Number of external pin port on specified port. */ 725 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 726 /* @brief Has external pin 7 connected to LLWU device. */ 727 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 728 /* @brief Index of port of external pin. */ 729 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 730 /* @brief Number of external pin port on specified port. */ 731 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 732 /* @brief Has external pin 8 connected to LLWU device. */ 733 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 734 /* @brief Index of port of external pin. */ 735 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 736 /* @brief Number of external pin port on specified port. */ 737 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 738 /* @brief Has external pin 9 connected to LLWU device. */ 739 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 740 /* @brief Index of port of external pin. */ 741 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 742 /* @brief Number of external pin port on specified port. */ 743 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 744 /* @brief Has external pin 10 connected to LLWU device. */ 745 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 746 /* @brief Index of port of external pin. */ 747 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 748 /* @brief Number of external pin port on specified port. */ 749 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 750 /* @brief Has external pin 11 connected to LLWU device. */ 751 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 752 /* @brief Index of port of external pin. */ 753 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 754 /* @brief Number of external pin port on specified port. */ 755 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 756 /* @brief Has external pin 12 connected to LLWU device. */ 757 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 758 /* @brief Index of port of external pin. */ 759 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 760 /* @brief Number of external pin port on specified port. */ 761 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 762 /* @brief Has external pin 13 connected to LLWU device. */ 763 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 764 /* @brief Index of port of external pin. */ 765 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 766 /* @brief Number of external pin port on specified port. */ 767 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 768 /* @brief Has external pin 14 connected to LLWU device. */ 769 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 770 /* @brief Index of port of external pin. */ 771 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 772 /* @brief Number of external pin port on specified port. */ 773 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 774 /* @brief Has external pin 15 connected to LLWU device. */ 775 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 776 /* @brief Index of port of external pin. */ 777 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 778 /* @brief Number of external pin port on specified port. */ 779 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 780 /* @brief Has external pin 16 connected to LLWU device. */ 781 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 782 /* @brief Index of port of external pin. */ 783 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 784 /* @brief Number of external pin port on specified port. */ 785 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 786 /* @brief Has external pin 17 connected to LLWU device. */ 787 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 788 /* @brief Index of port of external pin. */ 789 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 790 /* @brief Number of external pin port on specified port. */ 791 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 792 /* @brief Has external pin 18 connected to LLWU device. */ 793 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 794 /* @brief Index of port of external pin. */ 795 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 796 /* @brief Number of external pin port on specified port. */ 797 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 798 /* @brief Has external pin 19 connected to LLWU device. */ 799 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 800 /* @brief Index of port of external pin. */ 801 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 802 /* @brief Number of external pin port on specified port. */ 803 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 804 /* @brief Has external pin 20 connected to LLWU device. */ 805 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 806 /* @brief Index of port of external pin. */ 807 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 808 /* @brief Number of external pin port on specified port. */ 809 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 810 /* @brief Has external pin 21 connected to LLWU device. */ 811 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 812 /* @brief Index of port of external pin. */ 813 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 814 /* @brief Number of external pin port on specified port. */ 815 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 816 /* @brief Has external pin 22 connected to LLWU device. */ 817 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 818 /* @brief Index of port of external pin. */ 819 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 820 /* @brief Number of external pin port on specified port. */ 821 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 822 /* @brief Has external pin 23 connected to LLWU device. */ 823 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 824 /* @brief Index of port of external pin. */ 825 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 826 /* @brief Number of external pin port on specified port. */ 827 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 828 /* @brief Has external pin 24 connected to LLWU device. */ 829 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 830 /* @brief Index of port of external pin. */ 831 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 832 /* @brief Number of external pin port on specified port. */ 833 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 834 /* @brief Has external pin 25 connected to LLWU device. */ 835 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 836 /* @brief Index of port of external pin. */ 837 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 838 /* @brief Number of external pin port on specified port. */ 839 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 840 /* @brief Has external pin 26 connected to LLWU device. */ 841 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 842 /* @brief Index of port of external pin. */ 843 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 844 /* @brief Number of external pin port on specified port. */ 845 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 846 /* @brief Has external pin 27 connected to LLWU device. */ 847 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 848 /* @brief Index of port of external pin. */ 849 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 850 /* @brief Number of external pin port on specified port. */ 851 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 852 /* @brief Has external pin 28 connected to LLWU device. */ 853 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 854 /* @brief Index of port of external pin. */ 855 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 856 /* @brief Number of external pin port on specified port. */ 857 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 858 /* @brief Has external pin 29 connected to LLWU device. */ 859 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 860 /* @brief Index of port of external pin. */ 861 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 862 /* @brief Number of external pin port on specified port. */ 863 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 864 /* @brief Has external pin 30 connected to LLWU device. */ 865 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 866 /* @brief Index of port of external pin. */ 867 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 868 /* @brief Number of external pin port on specified port. */ 869 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 870 /* @brief Has external pin 31 connected to LLWU device. */ 871 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 872 /* @brief Index of port of external pin. */ 873 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 874 /* @brief Number of external pin port on specified port. */ 875 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 876 /* @brief Has internal module 0 connected to LLWU device. */ 877 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 878 /* @brief Has internal module 1 connected to LLWU device. */ 879 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 880 /* @brief Has internal module 2 connected to LLWU device. */ 881 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 882 /* @brief Has internal module 3 connected to LLWU device. */ 883 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 884 /* @brief Has internal module 4 connected to LLWU device. */ 885 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 886 /* @brief Has internal module 5 connected to LLWU device. */ 887 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 888 /* @brief Has internal module 6 connected to LLWU device. */ 889 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 890 /* @brief Has internal module 7 connected to LLWU device. */ 891 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 892 /* @brief Has Version ID Register (LLWU_VERID). */ 893 #define FSL_FEATURE_LLWU_HAS_VERID (0) 894 /* @brief Has Parameter Register (LLWU_PARAM). */ 895 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 896 /* @brief Width of registers of the LLWU. */ 897 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 898 /* @brief Has DMA Enable register (LLWU_DE). */ 899 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 900 #elif defined(CPU_MKV10Z128VLF7) || defined(CPU_MKV10Z64VLF7) 901 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 902 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 903 /* @brief Has pins 8-15 connected to LLWU device. */ 904 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 905 /* @brief Maximum number of internal modules connected to LLWU device. */ 906 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 907 /* @brief Number of digital filters. */ 908 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 909 /* @brief Has MF register. */ 910 #define FSL_FEATURE_LLWU_HAS_MF (1) 911 /* @brief Has PF register. */ 912 #define FSL_FEATURE_LLWU_HAS_PF (1) 913 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 914 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 915 /* @brief Has no internal module wakeup flag register. */ 916 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 917 /* @brief Has external pin 0 connected to LLWU device. */ 918 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 919 /* @brief Index of port of external pin. */ 920 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 921 /* @brief Number of external pin port on specified port. */ 922 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 923 /* @brief Has external pin 1 connected to LLWU device. */ 924 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 925 /* @brief Index of port of external pin. */ 926 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 927 /* @brief Number of external pin port on specified port. */ 928 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 929 /* @brief Has external pin 2 connected to LLWU device. */ 930 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 931 /* @brief Index of port of external pin. */ 932 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 933 /* @brief Number of external pin port on specified port. */ 934 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 935 /* @brief Has external pin 3 connected to LLWU device. */ 936 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 937 /* @brief Index of port of external pin. */ 938 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 939 /* @brief Number of external pin port on specified port. */ 940 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 941 /* @brief Has external pin 4 connected to LLWU device. */ 942 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 943 /* @brief Index of port of external pin. */ 944 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 945 /* @brief Number of external pin port on specified port. */ 946 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 947 /* @brief Has external pin 5 connected to LLWU device. */ 948 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 949 /* @brief Index of port of external pin. */ 950 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 951 /* @brief Number of external pin port on specified port. */ 952 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 953 /* @brief Has external pin 6 connected to LLWU device. */ 954 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 955 /* @brief Index of port of external pin. */ 956 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 957 /* @brief Number of external pin port on specified port. */ 958 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 959 /* @brief Has external pin 7 connected to LLWU device. */ 960 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 961 /* @brief Index of port of external pin. */ 962 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 963 /* @brief Number of external pin port on specified port. */ 964 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 965 /* @brief Has external pin 8 connected to LLWU device. */ 966 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 967 /* @brief Index of port of external pin. */ 968 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 969 /* @brief Number of external pin port on specified port. */ 970 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 971 /* @brief Has external pin 9 connected to LLWU device. */ 972 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 973 /* @brief Index of port of external pin. */ 974 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 975 /* @brief Number of external pin port on specified port. */ 976 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 977 /* @brief Has external pin 10 connected to LLWU device. */ 978 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 979 /* @brief Index of port of external pin. */ 980 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 981 /* @brief Number of external pin port on specified port. */ 982 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 983 /* @brief Has external pin 11 connected to LLWU device. */ 984 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 985 /* @brief Index of port of external pin. */ 986 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 987 /* @brief Number of external pin port on specified port. */ 988 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 989 /* @brief Has external pin 12 connected to LLWU device. */ 990 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 991 /* @brief Index of port of external pin. */ 992 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 993 /* @brief Number of external pin port on specified port. */ 994 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 995 /* @brief Has external pin 13 connected to LLWU device. */ 996 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 997 /* @brief Index of port of external pin. */ 998 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 999 /* @brief Number of external pin port on specified port. */ 1000 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1001 /* @brief Has external pin 14 connected to LLWU device. */ 1002 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1003 /* @brief Index of port of external pin. */ 1004 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1005 /* @brief Number of external pin port on specified port. */ 1006 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1007 /* @brief Has external pin 15 connected to LLWU device. */ 1008 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1009 /* @brief Index of port of external pin. */ 1010 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1011 /* @brief Number of external pin port on specified port. */ 1012 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1013 /* @brief Has external pin 16 connected to LLWU device. */ 1014 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1015 /* @brief Index of port of external pin. */ 1016 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1017 /* @brief Number of external pin port on specified port. */ 1018 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1019 /* @brief Has external pin 17 connected to LLWU device. */ 1020 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1021 /* @brief Index of port of external pin. */ 1022 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1023 /* @brief Number of external pin port on specified port. */ 1024 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1025 /* @brief Has external pin 18 connected to LLWU device. */ 1026 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1027 /* @brief Index of port of external pin. */ 1028 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1029 /* @brief Number of external pin port on specified port. */ 1030 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1031 /* @brief Has external pin 19 connected to LLWU device. */ 1032 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1033 /* @brief Index of port of external pin. */ 1034 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1035 /* @brief Number of external pin port on specified port. */ 1036 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1037 /* @brief Has external pin 20 connected to LLWU device. */ 1038 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1039 /* @brief Index of port of external pin. */ 1040 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1041 /* @brief Number of external pin port on specified port. */ 1042 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1043 /* @brief Has external pin 21 connected to LLWU device. */ 1044 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1045 /* @brief Index of port of external pin. */ 1046 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1047 /* @brief Number of external pin port on specified port. */ 1048 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1049 /* @brief Has external pin 22 connected to LLWU device. */ 1050 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1051 /* @brief Index of port of external pin. */ 1052 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1053 /* @brief Number of external pin port on specified port. */ 1054 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1055 /* @brief Has external pin 23 connected to LLWU device. */ 1056 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1057 /* @brief Index of port of external pin. */ 1058 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1059 /* @brief Number of external pin port on specified port. */ 1060 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1061 /* @brief Has external pin 24 connected to LLWU device. */ 1062 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1063 /* @brief Index of port of external pin. */ 1064 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1065 /* @brief Number of external pin port on specified port. */ 1066 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1067 /* @brief Has external pin 25 connected to LLWU device. */ 1068 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1069 /* @brief Index of port of external pin. */ 1070 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1071 /* @brief Number of external pin port on specified port. */ 1072 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1073 /* @brief Has external pin 26 connected to LLWU device. */ 1074 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1075 /* @brief Index of port of external pin. */ 1076 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1077 /* @brief Number of external pin port on specified port. */ 1078 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1079 /* @brief Has external pin 27 connected to LLWU device. */ 1080 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1081 /* @brief Index of port of external pin. */ 1082 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1083 /* @brief Number of external pin port on specified port. */ 1084 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1085 /* @brief Has external pin 28 connected to LLWU device. */ 1086 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1087 /* @brief Index of port of external pin. */ 1088 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1089 /* @brief Number of external pin port on specified port. */ 1090 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1091 /* @brief Has external pin 29 connected to LLWU device. */ 1092 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1093 /* @brief Index of port of external pin. */ 1094 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1095 /* @brief Number of external pin port on specified port. */ 1096 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1097 /* @brief Has external pin 30 connected to LLWU device. */ 1098 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1099 /* @brief Index of port of external pin. */ 1100 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1101 /* @brief Number of external pin port on specified port. */ 1102 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1103 /* @brief Has external pin 31 connected to LLWU device. */ 1104 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1105 /* @brief Index of port of external pin. */ 1106 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1107 /* @brief Number of external pin port on specified port. */ 1108 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1109 /* @brief Has internal module 0 connected to LLWU device. */ 1110 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1111 /* @brief Has internal module 1 connected to LLWU device. */ 1112 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1113 /* @brief Has internal module 2 connected to LLWU device. */ 1114 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1115 /* @brief Has internal module 3 connected to LLWU device. */ 1116 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1117 /* @brief Has internal module 4 connected to LLWU device. */ 1118 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1119 /* @brief Has internal module 5 connected to LLWU device. */ 1120 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1121 /* @brief Has internal module 6 connected to LLWU device. */ 1122 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1123 /* @brief Has internal module 7 connected to LLWU device. */ 1124 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1125 /* @brief Has Version ID Register (LLWU_VERID). */ 1126 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1127 /* @brief Has Parameter Register (LLWU_PARAM). */ 1128 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1129 /* @brief Width of registers of the LLWU. */ 1130 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1131 /* @brief Has DMA Enable register (LLWU_DE). */ 1132 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1133 #elif defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VLH7) 1134 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1135 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 1136 /* @brief Has pins 8-15 connected to LLWU device. */ 1137 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1138 /* @brief Maximum number of internal modules connected to LLWU device. */ 1139 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 1140 /* @brief Number of digital filters. */ 1141 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 1142 /* @brief Has MF register. */ 1143 #define FSL_FEATURE_LLWU_HAS_MF (1) 1144 /* @brief Has PF register. */ 1145 #define FSL_FEATURE_LLWU_HAS_PF (1) 1146 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1147 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 1148 /* @brief Has no internal module wakeup flag register. */ 1149 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1150 /* @brief Has external pin 0 connected to LLWU device. */ 1151 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 1152 /* @brief Index of port of external pin. */ 1153 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 1154 /* @brief Number of external pin port on specified port. */ 1155 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 1156 /* @brief Has external pin 1 connected to LLWU device. */ 1157 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 1158 /* @brief Index of port of external pin. */ 1159 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 1160 /* @brief Number of external pin port on specified port. */ 1161 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 1162 /* @brief Has external pin 2 connected to LLWU device. */ 1163 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 1164 /* @brief Index of port of external pin. */ 1165 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 1166 /* @brief Number of external pin port on specified port. */ 1167 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 1168 /* @brief Has external pin 3 connected to LLWU device. */ 1169 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 1170 /* @brief Index of port of external pin. */ 1171 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 1172 /* @brief Number of external pin port on specified port. */ 1173 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 1174 /* @brief Has external pin 4 connected to LLWU device. */ 1175 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 1176 /* @brief Index of port of external pin. */ 1177 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 1178 /* @brief Number of external pin port on specified port. */ 1179 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 1180 /* @brief Has external pin 5 connected to LLWU device. */ 1181 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1182 /* @brief Index of port of external pin. */ 1183 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1184 /* @brief Number of external pin port on specified port. */ 1185 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1186 /* @brief Has external pin 6 connected to LLWU device. */ 1187 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1188 /* @brief Index of port of external pin. */ 1189 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1190 /* @brief Number of external pin port on specified port. */ 1191 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1192 /* @brief Has external pin 7 connected to LLWU device. */ 1193 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1194 /* @brief Index of port of external pin. */ 1195 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1196 /* @brief Number of external pin port on specified port. */ 1197 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1198 /* @brief Has external pin 8 connected to LLWU device. */ 1199 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1200 /* @brief Index of port of external pin. */ 1201 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1202 /* @brief Number of external pin port on specified port. */ 1203 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1204 /* @brief Has external pin 9 connected to LLWU device. */ 1205 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1206 /* @brief Index of port of external pin. */ 1207 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1208 /* @brief Number of external pin port on specified port. */ 1209 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1210 /* @brief Has external pin 10 connected to LLWU device. */ 1211 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1212 /* @brief Index of port of external pin. */ 1213 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1214 /* @brief Number of external pin port on specified port. */ 1215 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1216 /* @brief Has external pin 11 connected to LLWU device. */ 1217 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1218 /* @brief Index of port of external pin. */ 1219 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1220 /* @brief Number of external pin port on specified port. */ 1221 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1222 /* @brief Has external pin 12 connected to LLWU device. */ 1223 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1224 /* @brief Index of port of external pin. */ 1225 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1226 /* @brief Number of external pin port on specified port. */ 1227 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1228 /* @brief Has external pin 13 connected to LLWU device. */ 1229 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1230 /* @brief Index of port of external pin. */ 1231 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1232 /* @brief Number of external pin port on specified port. */ 1233 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1234 /* @brief Has external pin 14 connected to LLWU device. */ 1235 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1236 /* @brief Index of port of external pin. */ 1237 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1238 /* @brief Number of external pin port on specified port. */ 1239 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1240 /* @brief Has external pin 15 connected to LLWU device. */ 1241 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1242 /* @brief Index of port of external pin. */ 1243 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1244 /* @brief Number of external pin port on specified port. */ 1245 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1246 /* @brief Has external pin 16 connected to LLWU device. */ 1247 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1248 /* @brief Index of port of external pin. */ 1249 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1250 /* @brief Number of external pin port on specified port. */ 1251 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1252 /* @brief Has external pin 17 connected to LLWU device. */ 1253 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1254 /* @brief Index of port of external pin. */ 1255 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1256 /* @brief Number of external pin port on specified port. */ 1257 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1258 /* @brief Has external pin 18 connected to LLWU device. */ 1259 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1260 /* @brief Index of port of external pin. */ 1261 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1262 /* @brief Number of external pin port on specified port. */ 1263 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1264 /* @brief Has external pin 19 connected to LLWU device. */ 1265 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1266 /* @brief Index of port of external pin. */ 1267 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1268 /* @brief Number of external pin port on specified port. */ 1269 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1270 /* @brief Has external pin 20 connected to LLWU device. */ 1271 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1272 /* @brief Index of port of external pin. */ 1273 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1274 /* @brief Number of external pin port on specified port. */ 1275 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1276 /* @brief Has external pin 21 connected to LLWU device. */ 1277 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1278 /* @brief Index of port of external pin. */ 1279 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1280 /* @brief Number of external pin port on specified port. */ 1281 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1282 /* @brief Has external pin 22 connected to LLWU device. */ 1283 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1284 /* @brief Index of port of external pin. */ 1285 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1286 /* @brief Number of external pin port on specified port. */ 1287 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1288 /* @brief Has external pin 23 connected to LLWU device. */ 1289 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1290 /* @brief Index of port of external pin. */ 1291 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1292 /* @brief Number of external pin port on specified port. */ 1293 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1294 /* @brief Has external pin 24 connected to LLWU device. */ 1295 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1296 /* @brief Index of port of external pin. */ 1297 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1298 /* @brief Number of external pin port on specified port. */ 1299 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1300 /* @brief Has external pin 25 connected to LLWU device. */ 1301 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1302 /* @brief Index of port of external pin. */ 1303 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1304 /* @brief Number of external pin port on specified port. */ 1305 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1306 /* @brief Has external pin 26 connected to LLWU device. */ 1307 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1308 /* @brief Index of port of external pin. */ 1309 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1310 /* @brief Number of external pin port on specified port. */ 1311 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1312 /* @brief Has external pin 27 connected to LLWU device. */ 1313 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1314 /* @brief Index of port of external pin. */ 1315 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1316 /* @brief Number of external pin port on specified port. */ 1317 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1318 /* @brief Has external pin 28 connected to LLWU device. */ 1319 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1320 /* @brief Index of port of external pin. */ 1321 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1322 /* @brief Number of external pin port on specified port. */ 1323 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1324 /* @brief Has external pin 29 connected to LLWU device. */ 1325 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1326 /* @brief Index of port of external pin. */ 1327 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1328 /* @brief Number of external pin port on specified port. */ 1329 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1330 /* @brief Has external pin 30 connected to LLWU device. */ 1331 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1332 /* @brief Index of port of external pin. */ 1333 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1334 /* @brief Number of external pin port on specified port. */ 1335 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1336 /* @brief Has external pin 31 connected to LLWU device. */ 1337 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1338 /* @brief Index of port of external pin. */ 1339 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1340 /* @brief Number of external pin port on specified port. */ 1341 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1342 /* @brief Has internal module 0 connected to LLWU device. */ 1343 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1344 /* @brief Has internal module 1 connected to LLWU device. */ 1345 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1346 /* @brief Has internal module 2 connected to LLWU device. */ 1347 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1348 /* @brief Has internal module 3 connected to LLWU device. */ 1349 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1350 /* @brief Has internal module 4 connected to LLWU device. */ 1351 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1352 /* @brief Has internal module 5 connected to LLWU device. */ 1353 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1354 /* @brief Has internal module 6 connected to LLWU device. */ 1355 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1356 /* @brief Has internal module 7 connected to LLWU device. */ 1357 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1358 /* @brief Has Version ID Register (LLWU_VERID). */ 1359 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1360 /* @brief Has Parameter Register (LLWU_PARAM). */ 1361 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1362 /* @brief Width of registers of the LLWU. */ 1363 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1364 /* @brief Has DMA Enable register (LLWU_DE). */ 1365 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1366 #endif /* defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) */ 1367 1368 /* LPTMR module features */ 1369 1370 /* @brief Has shared interrupt handler with another LPTMR module. */ 1371 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1372 /* @brief Whether LPTMR counter is 32 bits width. */ 1373 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1374 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1375 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1376 1377 /* MCG module features */ 1378 1379 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1380 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) 1381 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1382 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) 1383 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1384 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) 1385 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1386 #define FSL_FEATURE_MCG_PLL_REF_MIN (0) 1387 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1388 #define FSL_FEATURE_MCG_PLL_REF_MAX (0) 1389 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1390 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1391 /* @brief FRDIV supports 1280. */ 1392 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1393 /* @brief FRDIV supports 1536. */ 1394 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1395 /* @brief MCGFFCLK divider. */ 1396 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1397 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1398 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) 1399 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1400 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1401 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1402 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1403 /* @brief Has 48MHz internal oscillator. */ 1404 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1405 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1406 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1407 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1408 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1409 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1410 #define FSL_FEATURE_MCG_HAS_LOLRE (0) 1411 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1412 #define FSL_FEATURE_MCG_USE_OSCSEL (0) 1413 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1414 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1415 /* @brief TBD */ 1416 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1417 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ 1418 #define FSL_FEATURE_MCG_HAS_PLL (0) 1419 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1420 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 1421 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1422 #define FSL_FEATURE_MCG_HAS_FLL (1) 1423 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1424 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1425 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1426 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1427 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1428 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) 1429 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1430 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1431 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1432 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1433 /* @brief Has external clock monitor (register bit C6[CME]). */ 1434 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1435 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1436 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1437 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1438 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1439 /* @brief Has PEI mode or PBI mode. */ 1440 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1441 /* @brief Reset clock mode is BLPI. */ 1442 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1443 1444 /* MMDVSQ module features */ 1445 1446 /* No feature definitions */ 1447 1448 /* interrupt module features */ 1449 1450 /* @brief Lowest interrupt request number. */ 1451 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1452 /* @brief Highest interrupt request number. */ 1453 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 1454 1455 /* OSC module features */ 1456 1457 /* @brief Has OSC1 external oscillator. */ 1458 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1459 /* @brief Has OSC0 external oscillator. */ 1460 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 1461 /* @brief Has OSC external oscillator (without index). */ 1462 #define FSL_FEATURE_OSC_HAS_OSC (0) 1463 /* @brief Number of OSC external oscillators. */ 1464 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1465 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1466 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 1467 1468 /* PDB module features */ 1469 1470 /* @brief Has DAC support. */ 1471 #define FSL_FEATURE_PDB_HAS_DAC (1) 1472 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1473 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (1) 1474 /* @brief PDB channel number). */ 1475 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1476 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1477 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1478 /* @brief DAC interval trigger number). */ 1479 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 1480 /* @brief Pulse out number). */ 1481 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1482 1483 /* PMC module features */ 1484 1485 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1486 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1487 /* @brief Has Bandgap Buffer Enable. */ 1488 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1489 /* @brief Has Bandgap Buffer Drive Select. */ 1490 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1491 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1492 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1493 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1494 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1495 /* @brief Has LPO. */ 1496 #define FSL_FEATURE_PMC_HAS_LPO (0) 1497 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1498 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1499 /* @brief Has acknowledge isolation support. */ 1500 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1501 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1502 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1503 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1504 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1505 /* @brief Has PMC_HVDSC1. */ 1506 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1507 /* @brief Has PMC_PARAM. */ 1508 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1509 /* @brief Has PMC_VERID. */ 1510 #define FSL_FEATURE_PMC_HAS_VERID (0) 1511 1512 /* PORT module features */ 1513 1514 /* @brief Has control lock (register bit PCR[LK]). */ 1515 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 1516 /* @brief Has open drain control (register bit PCR[ODE]). */ 1517 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 1518 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1519 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 1520 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1521 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1522 /* @brief Has pull resistor selection available. */ 1523 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1524 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1525 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1526 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1527 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1528 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1529 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1530 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1531 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1532 /* @brief Has separate drive strength register (HDRVE). */ 1533 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1534 /* @brief Has glitch filter (register IOFLT). */ 1535 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1536 /* @brief Defines width of PCR[MUX] field. */ 1537 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1538 /* @brief Has dedicated interrupt vector. */ 1539 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1540 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1541 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1542 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1543 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1544 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1545 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1546 1547 /* RCM module features */ 1548 1549 /* @brief Has Loss-of-Lock Reset support. */ 1550 #define FSL_FEATURE_RCM_HAS_LOL (0) 1551 /* @brief Has Loss-of-Clock Reset support. */ 1552 #define FSL_FEATURE_RCM_HAS_LOC (1) 1553 /* @brief Has JTAG generated Reset support. */ 1554 #define FSL_FEATURE_RCM_HAS_JTAG (0) 1555 /* @brief Has EzPort generated Reset support. */ 1556 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1557 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1558 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1559 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1560 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1561 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1562 #define FSL_FEATURE_RCM_HAS_SSRS (0) 1563 /* @brief Has Version ID Register (RCM_VERID). */ 1564 #define FSL_FEATURE_RCM_HAS_VERID (0) 1565 /* @brief Has Parameter Register (RCM_PARAM). */ 1566 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1567 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1568 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1569 /* @brief Width of registers of the RCM. */ 1570 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1571 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1572 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1573 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1574 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1575 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1576 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1577 1578 /* SIM module features */ 1579 1580 /* @brief Has USB FS divider. */ 1581 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1582 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1583 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1584 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1585 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1586 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1587 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1588 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1589 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1590 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1591 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1592 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1593 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1594 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1595 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1596 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1597 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1598 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1599 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1600 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1601 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1602 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1603 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1604 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1605 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1606 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1607 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) 1608 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1609 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1610 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1611 #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) 1612 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1613 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1) 1614 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1615 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1) 1616 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1617 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1618 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1619 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1620 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1621 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1622 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1623 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1624 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1625 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1626 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1627 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1628 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1629 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1630 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1631 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1632 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1633 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1634 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1635 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1636 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1637 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1638 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1639 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1640 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1641 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1642 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1643 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1644 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1645 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1646 /* @brief Has FTM module(s) configuration. */ 1647 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1648 /* @brief Number of FTM modules. */ 1649 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1650 /* @brief Number of FTM triggers with selectable source. */ 1651 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1652 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1653 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1654 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1655 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1656 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1657 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1658 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1659 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1660 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1661 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1662 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1663 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1664 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1665 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1666 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1667 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1668 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1669 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1670 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1671 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1672 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1673 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1674 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1675 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1676 /* @brief Has TPM module(s) configuration. */ 1677 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1678 /* @brief The highest TPM module index. */ 1679 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1680 /* @brief Has TPM module with index 0. */ 1681 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1682 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1683 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1684 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1685 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1686 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1687 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1688 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1689 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1690 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1691 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1692 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1693 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1694 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1695 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1696 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1697 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1698 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1699 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1700 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1701 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1702 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1703 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1704 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1705 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1706 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1707 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1708 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1709 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1710 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1711 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1712 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1713 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1714 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1715 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1716 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1717 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1718 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1719 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1720 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1721 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1722 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1723 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1724 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1725 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1726 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1727 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1728 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1729 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1730 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1731 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1732 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1733 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1734 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1735 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (2) 1736 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1737 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (2) 1738 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1739 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1740 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1741 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1742 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1743 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1744 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1745 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1746 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1747 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1748 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1749 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1750 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1751 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1752 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1753 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1754 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1755 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1756 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1757 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1758 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1759 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1760 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1761 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 1762 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1763 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (1) 1764 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1765 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1766 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1767 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1768 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1769 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1770 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1771 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1772 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1773 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1774 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1775 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1776 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1777 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1778 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1779 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1780 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1781 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1782 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1783 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1784 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1785 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) 1786 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1787 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1788 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1789 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1790 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1791 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1792 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1793 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1794 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1795 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1796 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1797 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1798 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1799 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1800 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1801 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1802 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1803 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) 1804 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1805 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1806 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1807 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1808 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1809 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1810 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1811 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1812 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1813 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1814 /* @brief Has miscellanious control register (register MCR). */ 1815 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1816 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1817 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1818 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1819 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1820 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1821 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1822 /* @brief Has UIDH registers. */ 1823 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1824 /* @brief Has UIDM registers. */ 1825 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1826 1827 /* SMC module features */ 1828 1829 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1830 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1831 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1832 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1833 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1834 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1835 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1836 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1837 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1838 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1839 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1840 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1841 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1842 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1843 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1844 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1845 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1846 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1847 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1848 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1849 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1850 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1851 /* @brief Has stop submode. */ 1852 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1853 /* @brief Has stop submode 0(VLLS0). */ 1854 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1855 /* @brief Has stop submode 1(VLLS1). */ 1856 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1857 /* @brief Has stop submode 2(VLLS2). */ 1858 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1859 /* @brief Has SMC_PARAM. */ 1860 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1861 /* @brief Has SMC_VERID. */ 1862 #define FSL_FEATURE_SMC_HAS_VERID (0) 1863 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1864 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1865 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1866 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1867 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1868 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1869 /* @brief Width of SMC registers. */ 1870 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1871 1872 /* DSPI module features */ 1873 1874 #if defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) 1875 /* @brief Receive/transmit FIFO size in number of items. */ 1876 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1877 /* @brief Maximum transfer data width in bits. */ 1878 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1879 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1880 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (5) 1881 /* @brief Number of chip select pins. */ 1882 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) 1883 /* @brief Number of CTAR registers. */ 1884 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1885 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1886 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 1887 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1888 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (1) 1889 /* @brief Has 16-bit data transfer support. */ 1890 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1891 /* @brief Has separate DMA RX and TX requests. */ 1892 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1893 #elif defined(CPU_MKV10Z128VLF7) || defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7) 1894 /* @brief Receive/transmit FIFO size in number of items. */ 1895 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1896 /* @brief Maximum transfer data width in bits. */ 1897 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1898 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1899 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (5) 1900 /* @brief Number of chip select pins. */ 1901 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) 1902 /* @brief Number of CTAR registers. */ 1903 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1904 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1905 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 1906 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1907 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (1) 1908 /* @brief Has 16-bit data transfer support. */ 1909 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1910 /* @brief Has separate DMA RX and TX requests. */ 1911 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1912 #endif /* defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) */ 1913 1914 /* SysTick module features */ 1915 1916 /* @brief Systick has external reference clock. */ 1917 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1918 /* @brief Systick external reference clock is core clock divided by this value. */ 1919 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1920 1921 /* UART module features */ 1922 1923 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1924 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1925 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1926 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1927 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1928 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1929 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1930 #define FSL_FEATURE_UART_HAS_FIFO (1) 1931 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1932 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1933 /* @brief Infrared (modulation) is supported. */ 1934 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1935 /* @brief 2 bits long stop bit is available. */ 1936 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1937 /* @brief If 10-bit mode is supported. */ 1938 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1939 /* @brief Baud rate fine adjustment is available. */ 1940 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1941 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1942 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1943 /* @brief Baud rate oversampling is available. */ 1944 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1945 /* @brief Baud rate oversampling is available. */ 1946 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1947 /* @brief Peripheral type. */ 1948 #define FSL_FEATURE_UART_IS_SCI (0) 1949 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1950 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1951 (((x) == UART0) ? (8) : \ 1952 (((x) == UART1) ? (1) : (-1))) 1953 /* @brief Supports two match addresses to filter incoming frames. */ 1954 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1955 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1956 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1957 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1958 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1959 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1960 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1961 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1962 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) 1963 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1964 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1965 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1966 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1967 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1968 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1969 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1970 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1971 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1972 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1973 /* @brief Has separate DMA RX and TX requests. */ 1974 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1975 1976 /* WDOG module features */ 1977 1978 /* @brief Watchdog is available. */ 1979 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1980 /* @brief Has Wait mode support. */ 1981 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1982 1983 #endif /* _MKV10Z1287_FEATURES_H_ */ 1984 1985
