1 /* 2 ** ################################################################### 3 ** Version: rev. 1.3, 2015-05-25 4 ** Build: b210422 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2014-07-22) 20 ** Initial version. 21 ** - rev. 1.1 (2015-01-21) 22 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 23 ** - rev. 1.2 (2015-05-19) 24 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 25 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 26 ** Added features for PORT. 27 ** - rev. 1.3 (2015-05-25) 28 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 29 ** 30 ** ################################################################### 31 */ 32 33 #ifndef _MKM34ZA5_FEATURES_H_ 34 #define _MKM34ZA5_FEATURES_H_ 35 36 /* SOC module features */ 37 38 /* @brief ADC16 availability on the SoC. */ 39 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 40 /* @brief AFE availability on the SoC. */ 41 #define FSL_FEATURE_SOC_AFE_COUNT (1) 42 /* @brief AIPS availability on the SoC. */ 43 #define FSL_FEATURE_SOC_AIPS_COUNT (1) 44 /* @brief CMP availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CMP_COUNT (2) 46 /* @brief CRC availability on the SoC. */ 47 #define FSL_FEATURE_SOC_CRC_COUNT (1) 48 /* @brief DMA availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DMA_COUNT (1) 50 /* @brief DMAMUX availability on the SoC. */ 51 #define FSL_FEATURE_SOC_DMAMUX_COUNT (4) 52 /* @brief EWM availability on the SoC. */ 53 #define FSL_FEATURE_SOC_EWM_COUNT (1) 54 /* @brief FTFA availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 56 /* @brief GPIO availability on the SoC. */ 57 #define FSL_FEATURE_SOC_GPIO_COUNT (9) 58 /* @brief I2C availability on the SoC. */ 59 #define FSL_FEATURE_SOC_I2C_COUNT (2) 60 /* @brief SLCD availability on the SoC. */ 61 #define FSL_FEATURE_SOC_SLCD_COUNT (1) 62 /* @brief LLWU availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 64 /* @brief LPTMR availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 66 /* @brief MCG availability on the SoC. */ 67 #define FSL_FEATURE_SOC_MCG_COUNT (1) 68 /* @brief MCM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MCM_COUNT (1) 70 /* @brief SYSMPU availability on the SoC. */ 71 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 72 /* @brief MTB availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MTB_COUNT (1) 74 /* @brief MTBDWT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 76 /* @brief OSC availability on the SoC. */ 77 #define FSL_FEATURE_SOC_OSC_COUNT (1) 78 /* @brief PIT availability on the SoC. */ 79 #define FSL_FEATURE_SOC_PIT_COUNT (2) 80 /* @brief PMC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_PMC_COUNT (1) 82 /* @brief PORT availability on the SoC. */ 83 #define FSL_FEATURE_SOC_PORT_COUNT (9) 84 /* @brief RCM availability on the SoC. */ 85 #define FSL_FEATURE_SOC_RCM_COUNT (1) 86 /* @brief RNG availability on the SoC. */ 87 #define FSL_FEATURE_SOC_RNG_COUNT (1) 88 /* @brief ROM availability on the SoC. */ 89 #define FSL_FEATURE_SOC_ROM_COUNT (1) 90 /* @brief RTC availability on the SoC. */ 91 #define FSL_FEATURE_SOC_RTC_COUNT (1) 92 /* @brief SIM availability on the SoC. */ 93 #define FSL_FEATURE_SOC_SIM_COUNT (1) 94 /* @brief SMC availability on the SoC. */ 95 #define FSL_FEATURE_SOC_SMC_COUNT (1) 96 /* @brief SPI availability on the SoC. */ 97 #define FSL_FEATURE_SOC_SPI_COUNT (2) 98 /* @brief TMR availability on the SoC. */ 99 #define FSL_FEATURE_SOC_TMR_COUNT (4) 100 /* @brief UART availability on the SoC. */ 101 #define FSL_FEATURE_SOC_UART_COUNT (4) 102 /* @brief VREF availability on the SoC. */ 103 #define FSL_FEATURE_SOC_VREF_COUNT (1) 104 /* @brief WDOG availability on the SoC. */ 105 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 106 /* @brief XBAR availability on the SoC. */ 107 #define FSL_FEATURE_SOC_XBAR_COUNT (1) 108 109 /* ADC16 module features */ 110 111 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 112 #define FSL_FEATURE_ADC16_HAS_PGA (0) 113 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 114 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 115 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 116 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 117 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 118 #define FSL_FEATURE_ADC16_HAS_DMA (1) 119 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 120 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (0) 121 /* @brief Has FIFO (bit SC4[AFDEP]). */ 122 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 123 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 124 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 125 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 126 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (0) 127 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 128 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 129 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 130 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 131 /* @brief Has HW averaging (bit SC3[AVGE]). */ 132 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 133 /* @brief Has offset correction (register OFS). */ 134 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 135 /* @brief Maximum ADC resolution. */ 136 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 137 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 138 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (4) 139 140 /* AFE module features */ 141 142 /* @brief AFE channel counter. */ 143 #define FSL_FEATURE_AFE_CHANNEL_NUMBER (4) 144 /* @brief AFE channel counter with PGA feature. */ 145 #define FSL_FEATURE_AFE_CHANNEL_NUMBER_WITH_PGA (2) 146 /* @brief AFE has four channels. */ 147 #define FSL_FEATURE_AFE_HAS_FOUR_CHANNELS (1) 148 149 /* CMP module features */ 150 151 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 152 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 153 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 154 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 155 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 156 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 157 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 158 #define FSL_FEATURE_CMP_HAS_DMA (1) 159 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 160 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 161 /* @brief Has DAC Test function in CMP (register DACTEST). */ 162 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 163 164 /* CRC module features */ 165 166 /* @brief Has data register with name CRC */ 167 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 168 169 /* DMA module features */ 170 171 /* @brief Number of DMA channels. */ 172 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) 173 /* @brief Total number of DMA channels on all modules. */ 174 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (16) 175 176 /* DMAMUX module features */ 177 178 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 179 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (1) 180 /* @brief Total number of DMA channels on all modules. */ 181 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4) 182 /* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */ 183 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 184 /* @brief Register CHCFGn width. */ 185 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 186 187 /* EWM module features */ 188 189 /* @brief Has clock select (register CLKCTRL). */ 190 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 191 /* @brief Has clock prescaler (register CLKPRESCALER). */ 192 #define FSL_FEATURE_EWM_HAS_PRESCALER (0) 193 194 /* FLASH module features */ 195 196 /* @brief Is of type FTFA. */ 197 #define FSL_FEATURE_FLASH_IS_FTFA (1) 198 /* @brief Is of type FTFE. */ 199 #define FSL_FEATURE_FLASH_IS_FTFE (0) 200 /* @brief Is of type FTFL. */ 201 #define FSL_FEATURE_FLASH_IS_FTFL (0) 202 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 203 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 204 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 205 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 206 /* @brief Has EEPROM region protection (register FEPROT). */ 207 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 208 /* @brief Has data flash region protection (register FDPROT). */ 209 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 210 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 211 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 212 /* @brief Has flash cache control in FMC module. */ 213 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 214 /* @brief Has flash cache control in MCM module. */ 215 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 216 /* @brief Has flash cache control in MSCM module. */ 217 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 218 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 219 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 220 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 221 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 222 /* @brief P-Flash start address. */ 223 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 224 /* @brief P-Flash block count. */ 225 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 226 /* @brief P-Flash block size. */ 227 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 228 /* @brief P-Flash sector size. */ 229 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 230 /* @brief P-Flash write unit size. */ 231 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 232 /* @brief P-Flash data path width. */ 233 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 234 /* @brief P-Flash block swap feature. */ 235 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 236 /* @brief P-Flash protection region count. */ 237 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 238 /* @brief Has FlexNVM memory. */ 239 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 240 /* @brief Has FlexNVM alias. */ 241 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 242 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 243 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 244 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 245 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 246 /* @brief FlexNVM block count. */ 247 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 248 /* @brief FlexNVM block size. */ 249 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 250 /* @brief FlexNVM sector size. */ 251 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 252 /* @brief FlexNVM write unit size. */ 253 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 254 /* @brief FlexNVM data path width. */ 255 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 256 /* @brief Has FlexRAM memory. */ 257 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 258 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 259 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 260 /* @brief FlexRAM size. */ 261 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 262 /* @brief Has 0x00 Read 1s Block command. */ 263 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 264 /* @brief Has 0x01 Read 1s Section command. */ 265 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 266 /* @brief Has 0x02 Program Check command. */ 267 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 268 /* @brief Has 0x03 Read Resource command. */ 269 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 270 /* @brief Has 0x06 Program Longword command. */ 271 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 272 /* @brief Has 0x07 Program Phrase command. */ 273 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 274 /* @brief Has 0x08 Erase Flash Block command. */ 275 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 276 /* @brief Has 0x09 Erase Flash Sector command. */ 277 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 278 /* @brief Has 0x0B Program Section command. */ 279 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 280 /* @brief Has 0x40 Read 1s All Blocks command. */ 281 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 282 /* @brief Has 0x41 Read Once command. */ 283 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 284 /* @brief Has 0x43 Program Once command. */ 285 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 286 /* @brief Has 0x44 Erase All Blocks command. */ 287 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 288 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 289 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 290 /* @brief Has 0x46 Swap Control command. */ 291 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 292 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 293 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 294 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 295 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 296 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 297 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 298 /* @brief Has 0x80 Program Partition command. */ 299 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 300 /* @brief Has 0x81 Set FlexRAM Function command. */ 301 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 302 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 303 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 304 /* @brief P-Flash Erase sector command address alignment. */ 305 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 306 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 307 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 308 /* @brief P-Flash Read resource command address alignment. */ 309 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 310 /* @brief P-Flash Program check command address alignment. */ 311 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 312 /* @brief P-Flash Program check command address alignment. */ 313 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 314 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 315 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 316 /* @brief FlexNVM Erase sector command address alignment. */ 317 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 318 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 319 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 320 /* @brief FlexNVM Read resource command address alignment. */ 321 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 322 /* @brief FlexNVM Program check command address alignment. */ 323 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 324 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 325 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 326 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 327 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 328 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 329 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 330 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 331 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 332 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 333 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 334 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 335 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 336 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 337 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 338 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 339 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 340 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 341 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 342 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 343 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 344 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 345 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 346 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 347 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 348 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 349 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 350 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 351 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 352 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 353 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 354 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 355 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 356 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 357 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 358 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 359 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 360 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 361 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 362 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 363 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 364 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 366 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 368 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 370 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 372 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 374 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 376 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 378 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 380 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 382 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 384 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 386 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 388 389 /* GPIO module features */ 390 391 /* @brief Has GPIO attribute checker register (GACR). */ 392 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (1) 393 /* @brief GPIO registers width */ 394 #define FSL_FEATURE_GPIO_REGISTERS_WIDTH (8) 395 /* @brief Has no independent GPIO output control registers(register PSOR, PCOR and PTOR). */ 396 #define FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL (1) 397 398 /* I2C module features */ 399 400 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 401 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 402 /* @brief Maximum supported baud rate in kilobit per second. */ 403 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 404 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 405 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 406 /* @brief Has DMA support (register bit C1[DMAEN]). */ 407 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 408 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 409 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 410 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 411 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 412 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 413 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 414 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 415 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 416 /* @brief Has control of the drive capability of the I2C pins. */ 417 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 418 /* @brief Has double buffering support (register S2). */ 419 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 420 /* @brief Has double buffer enable. */ 421 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 422 /* @brief I2C0 and I2C1 has shared interrupt vector. */ 423 #define FSL_FEATURE_I2C_HAS_SHARED_IRQ0_IRQ1 (1) 424 425 /* SLCD module features */ 426 427 /* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ 428 #define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) 429 /* @brief Has fast frame rate (register bit GCR[FFR]). */ 430 #define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) 431 /* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ 432 #define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) 433 /* @brief Has high reference select (register bit GCR[HREFSEL]). */ 434 #define FSL_FEATURE_SLCD_HAS_HIGH_REFERENCE_SELECT (0) 435 /* @brief Has pad safe (register bit GCR[PADSAFE]). */ 436 #define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) 437 /* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ 438 #define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) 439 /* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ 440 #define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) 441 /* @brief Total pin number on LCD. */ 442 #define FSL_FEATURE_SLCD_HAS_PIN_NUM (64) 443 /* @brief Total phase number on SLCD. */ 444 #define FSL_FEATURE_SLCD_HAS_PHASE_NUM (8) 445 446 /* LLWU module features */ 447 448 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 449 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 450 /* @brief Has pins 8-15 connected to LLWU device. */ 451 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 452 /* @brief Maximum number of internal modules connected to LLWU device. */ 453 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (5) 454 /* @brief Number of digital filters. */ 455 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 456 /* @brief Has MF register. */ 457 #define FSL_FEATURE_LLWU_HAS_MF (0) 458 /* @brief Has PF register. */ 459 #define FSL_FEATURE_LLWU_HAS_PF (0) 460 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 461 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 462 /* @brief Has no internal module wakeup flag register. */ 463 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 464 /* @brief Has external pin 0 connected to LLWU device. */ 465 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 466 /* @brief Index of port of external pin. */ 467 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOG_IDX) 468 /* @brief Number of external pin port on specified port. */ 469 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (6) 470 /* @brief Has external pin 1 connected to LLWU device. */ 471 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 472 /* @brief Index of port of external pin. */ 473 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOG_IDX) 474 /* @brief Number of external pin port on specified port. */ 475 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 476 /* @brief Has external pin 2 connected to LLWU device. */ 477 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 478 /* @brief Index of port of external pin. */ 479 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOG_IDX) 480 /* @brief Number of external pin port on specified port. */ 481 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (1) 482 /* @brief Has external pin 3 connected to LLWU device. */ 483 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 484 /* @brief Index of port of external pin. */ 485 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOF_IDX) 486 /* @brief Number of external pin port on specified port. */ 487 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (6) 488 /* @brief Has external pin 4 connected to LLWU device. */ 489 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 490 /* @brief Index of port of external pin. */ 491 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOF_IDX) 492 /* @brief Number of external pin port on specified port. */ 493 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 494 /* @brief Has external pin 5 connected to LLWU device. */ 495 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 496 /* @brief Index of port of external pin. */ 497 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOE_IDX) 498 /* @brief Number of external pin port on specified port. */ 499 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (6) 500 /* @brief Has external pin 6 connected to LLWU device. */ 501 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 502 /* @brief Index of port of external pin. */ 503 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOE_IDX) 504 /* @brief Number of external pin port on specified port. */ 505 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (5) 506 /* @brief Has external pin 7 connected to LLWU device. */ 507 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 508 /* @brief Index of port of external pin. */ 509 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOD_IDX) 510 /* @brief Number of external pin port on specified port. */ 511 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (7) 512 /* @brief Has external pin 8 connected to LLWU device. */ 513 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 514 /* @brief Index of port of external pin. */ 515 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOD_IDX) 516 /* @brief Number of external pin port on specified port. */ 517 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (6) 518 /* @brief Has external pin 9 connected to LLWU device. */ 519 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 520 /* @brief Index of port of external pin. */ 521 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOD_IDX) 522 /* @brief Number of external pin port on specified port. */ 523 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (4) 524 /* @brief Has external pin 10 connected to LLWU device. */ 525 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 526 /* @brief Index of port of external pin. */ 527 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOD_IDX) 528 /* @brief Number of external pin port on specified port. */ 529 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) 530 /* @brief Has external pin 11 connected to LLWU device. */ 531 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 532 /* @brief Index of port of external pin. */ 533 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOD_IDX) 534 /* @brief Number of external pin port on specified port. */ 535 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 536 /* @brief Has external pin 12 connected to LLWU device. */ 537 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 538 /* @brief Index of port of external pin. */ 539 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) 540 /* @brief Number of external pin port on specified port. */ 541 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (5) 542 /* @brief Has external pin 13 connected to LLWU device. */ 543 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 544 /* @brief Index of port of external pin. */ 545 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) 546 /* @brief Number of external pin port on specified port. */ 547 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (3) 548 /* @brief Has external pin 14 connected to LLWU device. */ 549 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 550 /* @brief Index of port of external pin. */ 551 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOA_IDX) 552 /* @brief Number of external pin port on specified port. */ 553 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) 554 /* @brief Has external pin 15 connected to LLWU device. */ 555 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 556 /* @brief Index of port of external pin. */ 557 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOA_IDX) 558 /* @brief Number of external pin port on specified port. */ 559 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (4) 560 /* @brief Has external pin 16 connected to LLWU device. */ 561 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 562 /* @brief Index of port of external pin. */ 563 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 564 /* @brief Number of external pin port on specified port. */ 565 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 566 /* @brief Has external pin 17 connected to LLWU device. */ 567 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 568 /* @brief Index of port of external pin. */ 569 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 570 /* @brief Number of external pin port on specified port. */ 571 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 572 /* @brief Has external pin 18 connected to LLWU device. */ 573 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 574 /* @brief Index of port of external pin. */ 575 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 576 /* @brief Number of external pin port on specified port. */ 577 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 578 /* @brief Has external pin 19 connected to LLWU device. */ 579 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 580 /* @brief Index of port of external pin. */ 581 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 582 /* @brief Number of external pin port on specified port. */ 583 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 584 /* @brief Has external pin 20 connected to LLWU device. */ 585 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 586 /* @brief Index of port of external pin. */ 587 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 588 /* @brief Number of external pin port on specified port. */ 589 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 590 /* @brief Has external pin 21 connected to LLWU device. */ 591 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 592 /* @brief Index of port of external pin. */ 593 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 594 /* @brief Number of external pin port on specified port. */ 595 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 596 /* @brief Has external pin 22 connected to LLWU device. */ 597 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 598 /* @brief Index of port of external pin. */ 599 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 600 /* @brief Number of external pin port on specified port. */ 601 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 602 /* @brief Has external pin 23 connected to LLWU device. */ 603 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 604 /* @brief Index of port of external pin. */ 605 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 606 /* @brief Number of external pin port on specified port. */ 607 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 608 /* @brief Has external pin 24 connected to LLWU device. */ 609 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 610 /* @brief Index of port of external pin. */ 611 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 612 /* @brief Number of external pin port on specified port. */ 613 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 614 /* @brief Has external pin 25 connected to LLWU device. */ 615 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 616 /* @brief Index of port of external pin. */ 617 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 618 /* @brief Number of external pin port on specified port. */ 619 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 620 /* @brief Has external pin 26 connected to LLWU device. */ 621 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 622 /* @brief Index of port of external pin. */ 623 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 624 /* @brief Number of external pin port on specified port. */ 625 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 626 /* @brief Has external pin 27 connected to LLWU device. */ 627 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 628 /* @brief Index of port of external pin. */ 629 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 630 /* @brief Number of external pin port on specified port. */ 631 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 632 /* @brief Has external pin 28 connected to LLWU device. */ 633 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 634 /* @brief Index of port of external pin. */ 635 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 636 /* @brief Number of external pin port on specified port. */ 637 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 638 /* @brief Has external pin 29 connected to LLWU device. */ 639 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 640 /* @brief Index of port of external pin. */ 641 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 642 /* @brief Number of external pin port on specified port. */ 643 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 644 /* @brief Has external pin 30 connected to LLWU device. */ 645 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 646 /* @brief Index of port of external pin. */ 647 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 648 /* @brief Number of external pin port on specified port. */ 649 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 650 /* @brief Has external pin 31 connected to LLWU device. */ 651 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 652 /* @brief Index of port of external pin. */ 653 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 654 /* @brief Number of external pin port on specified port. */ 655 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 656 /* @brief Has internal module 0 connected to LLWU device. */ 657 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 658 /* @brief Has internal module 1 connected to LLWU device. */ 659 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 660 /* @brief Has internal module 2 connected to LLWU device. */ 661 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 662 /* @brief Has internal module 3 connected to LLWU device. */ 663 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 664 /* @brief Has internal module 4 connected to LLWU device. */ 665 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 666 /* @brief Has internal module 5 connected to LLWU device. */ 667 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 668 /* @brief Has internal module 6 connected to LLWU device. */ 669 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 670 /* @brief Has internal module 7 connected to LLWU device. */ 671 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 672 /* @brief Has Version ID Register (LLWU_VERID). */ 673 #define FSL_FEATURE_LLWU_HAS_VERID (0) 674 /* @brief Has Parameter Register (LLWU_PARAM). */ 675 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 676 /* @brief Width of registers of the LLWU. */ 677 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 678 /* @brief Has DMA Enable register (LLWU_DE). */ 679 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 680 681 /* LPTMR module features */ 682 683 /* @brief Has shared interrupt handler with another LPTMR module. */ 684 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 685 /* @brief Whether LPTMR counter is 32 bits width. */ 686 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 687 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 688 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 689 690 /* MCG module features */ 691 692 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 693 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) 694 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 695 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) 696 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 697 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) 698 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 699 #define FSL_FEATURE_MCG_PLL_REF_MIN (0) 700 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 701 #define FSL_FEATURE_MCG_PLL_REF_MAX (0) 702 /* @brief The PLL clock is divided by 2 before VCO divider. */ 703 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 704 /* @brief FRDIV supports 1280. */ 705 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 706 /* @brief FRDIV supports 1536. */ 707 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 708 /* @brief MCGFFCLK divider. */ 709 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 710 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 711 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 712 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 713 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 714 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 715 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 716 /* @brief Has 48MHz internal oscillator. */ 717 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 718 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 719 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 720 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 721 #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) 722 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 723 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 724 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 725 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 726 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 727 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 728 /* @brief TBD */ 729 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 730 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 731 #define FSL_FEATURE_MCG_HAS_PLL (1) 732 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 733 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) 734 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 735 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) 736 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 737 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 738 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 739 #define FSL_FEATURE_MCG_HAS_FLL (1) 740 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 741 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 742 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 743 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 744 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 745 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 746 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 747 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 748 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 749 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 750 /* @brief Has external clock monitor (register bit C6[CME]). */ 751 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 752 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 753 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 754 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 755 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 756 /* @brief Has PEI mode or PBI mode. */ 757 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (1) 758 /* @brief Reset clock mode is BLPI. */ 759 #define FSL_FEATURE_MCG_RESET_IS_BLPI (1) 760 761 /* OSC module features */ 762 763 /* @brief Has OSC1 external oscillator. */ 764 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 765 /* @brief Has OSC0 external oscillator. */ 766 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 767 /* @brief Has OSC external oscillator (without index). */ 768 #define FSL_FEATURE_OSC_HAS_OSC (1) 769 /* @brief Number of OSC external oscillators. */ 770 #define FSL_FEATURE_OSC_OSC_COUNT (1) 771 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 772 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 773 774 /* PIT module features */ 775 776 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 777 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 778 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 779 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 780 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 781 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 782 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 783 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 784 /* @brief Has timer enable control. */ 785 #define FSL_FEATURE_PIT_HAS_MDIS (1) 786 787 /* PMC module features */ 788 789 /* @brief Has Bandgap Enable In VLPx Operation support. */ 790 #define FSL_FEATURE_PMC_HAS_BGEN (1) 791 /* @brief Has Bandgap Buffer Enable. */ 792 #define FSL_FEATURE_PMC_HAS_BGBE (1) 793 /* @brief Has Bandgap Buffer Drive Select. */ 794 #define FSL_FEATURE_PMC_HAS_BGBDS (1) 795 /* @brief Has Low-Voltage Detect Voltage Select support. */ 796 #define FSL_FEATURE_PMC_HAS_LVDV (1) 797 /* @brief Has Low-Voltage Warning Voltage Select support. */ 798 #define FSL_FEATURE_PMC_HAS_LVWV (1) 799 /* @brief Has LPO. */ 800 #define FSL_FEATURE_PMC_HAS_LPO (0) 801 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 802 #define FSL_FEATURE_PMC_HAS_VLPO (0) 803 /* @brief Has acknowledge isolation support. */ 804 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 805 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 806 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 807 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 808 #define FSL_FEATURE_PMC_HAS_REGONS (1) 809 /* @brief Has PMC_HVDSC1. */ 810 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 811 /* @brief Has PMC_PARAM. */ 812 #define FSL_FEATURE_PMC_HAS_PARAM (0) 813 /* @brief Has PMC_VERID. */ 814 #define FSL_FEATURE_PMC_HAS_VERID (0) 815 816 /* PORT module features */ 817 818 /* @brief Has control lock (register bit PCR[LK]). */ 819 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 820 /* @brief Has open drain control (register bit PCR[ODE]). */ 821 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 822 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 823 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 824 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 825 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 826 /* @brief Has pull resistor selection available. */ 827 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 828 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 829 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 830 /* @brief Has slew rate control (register bit PCR[SRE]). */ 831 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 832 /* @brief Has passive filter (register bit field PCR[PFE]). */ 833 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (0) 834 /* @brief Has drive strength control (register bit PCR[DSE]). */ 835 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0) 836 /* @brief Has separate drive strength register (HDRVE). */ 837 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 838 /* @brief Has glitch filter (register IOFLT). */ 839 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 840 /* @brief Defines width of PCR[MUX] field. */ 841 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 842 /* @brief Has dedicated interrupt vector. */ 843 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 844 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 845 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 846 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 847 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 848 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 849 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 850 851 /* RCM module features */ 852 853 /* @brief Has Loss-of-Lock Reset support. */ 854 #define FSL_FEATURE_RCM_HAS_LOL (1) 855 /* @brief Has Loss-of-Clock Reset support. */ 856 #define FSL_FEATURE_RCM_HAS_LOC (1) 857 /* @brief Has JTAG generated Reset support. */ 858 #define FSL_FEATURE_RCM_HAS_JTAG (0) 859 /* @brief Has EzPort generated Reset support. */ 860 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 861 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 862 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 863 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 864 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 865 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 866 #define FSL_FEATURE_RCM_HAS_SSRS (0) 867 /* @brief Has Version ID Register (RCM_VERID). */ 868 #define FSL_FEATURE_RCM_HAS_VERID (0) 869 /* @brief Has Parameter Register (RCM_PARAM). */ 870 #define FSL_FEATURE_RCM_HAS_PARAM (0) 871 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 872 #define FSL_FEATURE_RCM_HAS_SRIE (0) 873 /* @brief Width of registers of the RCM. */ 874 #define FSL_FEATURE_RCM_REG_WIDTH (8) 875 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 876 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 877 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 878 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 879 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 880 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 881 882 /* RTC module features */ 883 884 /* @brief Has Tamper Direction Register support. */ 885 #define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) 886 /* @brief Has Tamper Queue Status and Control Register support. */ 887 #define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) 888 /* @brief Whether RTC is IRTC. */ 889 #define FSL_FEATURE_RTC_IS_IRTC (1) 890 891 /* SIM module features */ 892 893 /* @brief Has USB FS divider. */ 894 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 895 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 896 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 897 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 898 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 899 /* @brief Has SRAM size specification (register bit field SOPT1[SRAMSIZE]). */ 900 #define FSL_FEATURE_SIM_OPT_HAS_SRAMSIZE (1) 901 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 902 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 903 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 904 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 905 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 906 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 907 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 908 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 909 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 910 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 911 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 912 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 913 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 914 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 915 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 916 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 917 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 918 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 919 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 920 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 921 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 922 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 923 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 924 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 925 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 926 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 927 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 928 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 929 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 930 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 931 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 932 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 933 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 934 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 935 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 936 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 937 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 938 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 939 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 940 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 941 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 942 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 943 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 944 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 945 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 946 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 947 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 948 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 949 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 950 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 951 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 952 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 953 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 954 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 955 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 956 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 957 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 958 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 959 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 960 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 961 /* @brief Has FTM module(s) configuration. */ 962 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 963 /* @brief Number of FTM modules. */ 964 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 965 /* @brief Number of FTM triggers with selectable source. */ 966 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 967 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 968 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 969 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 970 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 971 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 972 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 973 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 974 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 975 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 976 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 977 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 978 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 979 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 980 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 981 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 982 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 983 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 984 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 985 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 986 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 987 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 988 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 989 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 990 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 991 /* @brief Has TPM module(s) configuration. */ 992 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 993 /* @brief The highest TPM module index. */ 994 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 995 /* @brief Has TPM module with index 0. */ 996 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 997 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 998 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 999 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1000 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1001 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1002 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1003 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1004 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1005 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1006 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1007 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1008 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1009 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1010 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1011 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1012 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1013 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1014 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1015 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1016 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1017 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1018 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1019 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1020 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1021 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1022 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1023 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1024 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1025 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1026 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1027 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1028 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1029 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1030 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1031 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1032 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1033 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1034 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1035 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1036 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1037 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1038 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1039 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1040 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1041 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1042 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1043 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1044 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1045 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1046 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1047 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1048 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) 1049 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1050 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) 1051 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1052 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1053 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1054 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1055 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1056 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1057 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1058 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1059 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1060 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1061 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1062 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1063 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1064 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1065 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1066 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1067 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1068 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1069 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1070 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1071 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1072 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1073 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1074 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) 1075 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1076 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) 1077 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1078 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1079 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1080 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1081 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1082 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1083 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1084 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1085 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1086 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1087 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1088 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1089 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1090 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1091 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1092 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1093 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1094 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1095 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1096 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1097 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1098 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1099 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1100 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1101 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1102 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1103 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1104 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1105 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1106 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1107 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1108 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1109 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1110 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1111 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1112 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1113 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1114 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1115 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1116 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1117 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1118 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) 1119 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1120 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1121 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1122 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1123 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1124 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1125 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1126 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1127 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1128 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1129 /* @brief Has miscellanious control register (register MCR). */ 1130 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1131 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1132 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1133 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1134 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1135 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1136 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1137 /* @brief Has UIDH registers. */ 1138 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1139 /* @brief Has UIDM registers. */ 1140 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1141 1142 /* SMC module features */ 1143 1144 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1145 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1146 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1147 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1148 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1149 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1150 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1151 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1152 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1153 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1154 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1155 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1156 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1157 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1158 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1159 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1160 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1161 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1162 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1163 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1164 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1165 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1166 /* @brief Has stop submode. */ 1167 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1168 /* @brief Has stop submode 0(VLLS0). */ 1169 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1170 /* @brief Has stop submode 1(VLLS1). */ 1171 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1172 /* @brief Has stop submode 2(VLLS2). */ 1173 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1174 /* @brief Has SMC_PARAM. */ 1175 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1176 /* @brief Has SMC_VERID. */ 1177 #define FSL_FEATURE_SMC_HAS_VERID (0) 1178 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1179 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1180 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1181 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1182 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1183 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1184 /* @brief Width of SMC registers. */ 1185 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1186 1187 /* SPI module features */ 1188 1189 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1190 #define FSL_FEATURE_SPI_HAS_FIFO (1) 1191 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 1192 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) 1193 /* @brief Has separate DMA RX and TX requests. */ 1194 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1195 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 1196 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) (0) 1197 /* @brief Maximum transfer data width in bits. */ 1198 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) 1199 /* @brief The data register name has postfix (L as low and H as high). */ 1200 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) 1201 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1202 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1203 /* @brief Has 16-bit data transfer support. */ 1204 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) 1205 1206 /* SYSMPU module features */ 1207 1208 /* @brief Specifies number of descriptors available. */ 1209 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (8) 1210 /* @brief Has process identifier support. */ 1211 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1212 /* @brief Total number of MPU slave. */ 1213 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (2) 1214 /* @brief Total number of MPU master. */ 1215 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (3) 1216 1217 /* UART module features */ 1218 1219 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1220 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1221 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1222 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1223 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1224 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1225 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1226 #define FSL_FEATURE_UART_HAS_FIFO (1) 1227 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1228 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1229 /* @brief Infrared (modulation) is supported. */ 1230 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1231 /* @brief 2 bits long stop bit is available. */ 1232 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1233 /* @brief If 10-bit mode is supported. */ 1234 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1235 /* @brief Baud rate fine adjustment is available. */ 1236 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1237 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1238 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1239 /* @brief Baud rate oversampling is available. */ 1240 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1241 /* @brief Baud rate oversampling is available. */ 1242 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1243 /* @brief Peripheral type. */ 1244 #define FSL_FEATURE_UART_IS_SCI (0) 1245 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1246 #define FSL_FEATURE_UART_FIFO_SIZEn(x) (8) 1247 /* @brief Supports two match addresses to filter incoming frames. */ 1248 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1249 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1250 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1251 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1252 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1253 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1254 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1255 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1256 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1257 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1258 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1259 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1260 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1261 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1262 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1263 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1264 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0) 1265 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1266 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0) 1267 /* @brief Has separate DMA RX and TX requests. */ 1268 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1269 /* @brief UART0 and UART1 have shared interrupt vector. */ 1270 #define FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1 (1) 1271 /* @brief UART2 and UART3 have shared interrupt vector. */ 1272 #define FSL_FEATURE_UART_HAS_SHARED_IRQ2_IRQ3 (1) 1273 1274 /* VREF module features */ 1275 1276 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1277 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1278 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1279 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1280 /* @brief If high/low buffer mode supported */ 1281 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1282 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1283 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (1) 1284 1285 /* WDOG module features */ 1286 1287 /* @brief Watchdog is available. */ 1288 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1289 /* @brief Has Wait mode support. */ 1290 #define FSL_FEATURE_WDOG_HAS_WAITEN (0) 1291 1292 /* XBAR module features */ 1293 1294 /* @brief Number of interrupt requests. */ 1295 #define FSL_FEATURE_XBAR_INTERRUPT_COUNT (1) 1296 1297 #endif /* _MKM34ZA5_FEATURES_H_ */ 1298 1299
