1 /* 2 ** ################################################################### 3 ** Version: rev. 4.0, 2016-09-20 4 ** Build: b231109 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2015-11-18) 18 ** Initial version. 19 ** - rev. 2.0 (2015-12-03) 20 ** Alpha version based on rev0 RDP. 21 ** - rev. 3.0 (2016-04-13) 22 ** Final version based on rev1 RDP. 23 ** - rev. 4.0 (2016-09-20) 24 ** Updated based on rev2 RDP. 25 ** 26 ** ################################################################### 27 */ 28 29 #ifndef _MKE18F16_FEATURES_H_ 30 #define _MKE18F16_FEATURES_H_ 31 32 /* SOC module features */ 33 34 /* @brief ACMP availability on the SoC. */ 35 #define FSL_FEATURE_SOC_ACMP_COUNT (3) 36 /* @brief ADC12 availability on the SoC. */ 37 #define FSL_FEATURE_SOC_ADC12_COUNT (3) 38 /* @brief AIPS availability on the SoC. */ 39 #define FSL_FEATURE_SOC_AIPS_COUNT (1) 40 /* @brief FLEXCAN availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) 42 /* @brief CRC availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CRC_COUNT (1) 44 /* @brief DAC32 availability on the SoC. */ 45 #define FSL_FEATURE_SOC_DAC32_COUNT (1) 46 /* @brief EDMA availability on the SoC. */ 47 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 48 /* @brief DMAMUX availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 50 /* @brief EWM availability on the SoC. */ 51 #define FSL_FEATURE_SOC_EWM_COUNT (1) 52 /* @brief FLEXIO availability on the SoC. */ 53 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 54 /* @brief FTFE availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 56 /* @brief FTM availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FTM_COUNT (4) 58 /* @brief GPIO availability on the SoC. */ 59 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 60 /* @brief LMEM availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LMEM_COUNT (1) 62 /* @brief LPI2C availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 64 /* @brief LPIT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LPIT_COUNT (1) 66 /* @brief LPSPI availability on the SoC. */ 67 #define FSL_FEATURE_SOC_LPSPI_COUNT (2) 68 /* @brief LPTMR availability on the SoC. */ 69 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 70 /* @brief LPUART availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LPUART_COUNT (3) 72 /* @brief MCM availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MCM_COUNT (1) 74 /* @brief SYSMPU availability on the SoC. */ 75 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 76 /* @brief MSCM availability on the SoC. */ 77 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 78 /* @brief OSC32 availability on the SoC. */ 79 #define FSL_FEATURE_SOC_OSC32_COUNT (1) 80 /* @brief PDB availability on the SoC. */ 81 #define FSL_FEATURE_SOC_PDB_COUNT (3) 82 /* @brief PCC availability on the SoC. */ 83 #define FSL_FEATURE_SOC_PCC_COUNT (1) 84 /* @brief PMC availability on the SoC. */ 85 #define FSL_FEATURE_SOC_PMC_COUNT (1) 86 /* @brief PORT availability on the SoC. */ 87 #define FSL_FEATURE_SOC_PORT_COUNT (5) 88 /* @brief PWT availability on the SoC. */ 89 #define FSL_FEATURE_SOC_PWT_COUNT (1) 90 /* @brief RCM availability on the SoC. */ 91 #define FSL_FEATURE_SOC_RCM_COUNT (1) 92 /* @brief RTC availability on the SoC. */ 93 #define FSL_FEATURE_SOC_RTC_COUNT (1) 94 /* @brief SCG availability on the SoC. */ 95 #define FSL_FEATURE_SOC_SCG_COUNT (1) 96 /* @brief SIM availability on the SoC. */ 97 #define FSL_FEATURE_SOC_SIM_COUNT (1) 98 /* @brief SMC availability on the SoC. */ 99 #define FSL_FEATURE_SOC_SMC_COUNT (1) 100 /* @brief TRGMUX availability on the SoC. */ 101 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) 102 /* @brief WDOG availability on the SoC. */ 103 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 104 105 /* ADC12 module features */ 106 107 /* @brief Has DMA support (bit SC2[DMAEN]. */ 108 #define FSL_FEATURE_ADC12_HAS_DMA_SUPPORT (1) 109 /* @brief Conversion control count (related to number of registers SC1n and Rn). */ 110 #define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (8) 111 112 /* FLEXCAN module features */ 113 114 /* @brief Message buffer size */ 115 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 116 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 117 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) 118 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 119 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) 120 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 121 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 122 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 123 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 124 /* @brief Instance has extended bit timing register (register CBT). */ 125 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 126 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 127 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 128 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 129 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 130 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 131 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 132 /* @brief Has bitfield name BUF31TO0M. */ 133 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (1) 134 /* @brief Number of interrupt vectors. */ 135 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 136 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 137 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 138 139 /* ACMP module features */ 140 141 /* @brief Has CMP_C3. */ 142 #define FSL_FEATURE_ACMP_HAS_C3_REG (0) 143 /* @brief Has C0 LINKEN Bit */ 144 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (0) 145 /* @brief Has C0 OFFSET Bit */ 146 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (1) 147 /* @brief Has C0 HYSTCTR Bit */ 148 #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) 149 /* @brief Has C1 INPSEL Bit */ 150 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (1) 151 /* @brief Has C1 INNSEL Bit */ 152 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (1) 153 /* @brief Has C1 DACOE Bit */ 154 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) 155 /* @brief Has C1 DMODE Bit */ 156 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (0) 157 /* @brief Has C2 RRE Bit */ 158 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (1) 159 160 /* CRC module features */ 161 162 /* @brief Has data register with name CRC */ 163 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 164 165 /* DAC32 module features */ 166 167 /* No feature definitions */ 168 169 /* EDMA module features */ 170 171 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 172 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 173 /* @brief Total number of DMA channels on all modules. */ 174 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) 175 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 176 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 177 /* @brief Has DMA_Error interrupt vector. */ 178 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 179 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 180 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) 181 /* @brief Channel IRQ entry shared offset. */ 182 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 183 /* @brief If 8 bytes transfer supported. */ 184 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 185 /* @brief If 16 bytes transfer supported. */ 186 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 187 188 /* DMAMUX module features */ 189 190 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 191 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 192 /* @brief Total number of DMA channels on all modules. */ 193 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16) 194 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 195 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 196 /* @brief Register CHCFGn width. */ 197 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 198 199 /* EWM module features */ 200 201 /* @brief Has clock select (register CLKCTRL). */ 202 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 203 /* @brief Has clock prescaler (register CLKPRESCALER). */ 204 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 205 206 /* FLEXIO module features */ 207 208 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 209 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 210 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 211 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 212 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 213 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0) 214 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 215 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0) 216 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 217 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0) 218 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 219 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) 220 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 221 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) 222 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 223 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0) 224 /* @brief Reset value of the FLEXIO_VERID register */ 225 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010000) 226 /* @brief Reset value of the FLEXIO_PARAM register */ 227 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4080404) 228 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 229 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) 230 /* @brief Flexio DMA request base channel */ 231 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 232 233 /* FLASH module features */ 234 235 #if defined(CPU_MKE18F256VLH16) || defined(CPU_MKE18F256VLL16) 236 /* @brief Is of type FTFA. */ 237 #define FSL_FEATURE_FLASH_IS_FTFA (0) 238 /* @brief Is of type FTFE. */ 239 #define FSL_FEATURE_FLASH_IS_FTFE (1) 240 /* @brief Is of type FTFL. */ 241 #define FSL_FEATURE_FLASH_IS_FTFL (0) 242 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 243 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 244 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 245 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 246 /* @brief Has EEPROM region protection (register FEPROT). */ 247 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 248 /* @brief Has data flash region protection (register FDPROT). */ 249 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 250 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 251 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 252 /* @brief Has flash cache control in FMC module. */ 253 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 254 /* @brief Has flash cache control in MCM module. */ 255 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 256 /* @brief Has flash cache control in MSCM module. */ 257 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1) 258 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 259 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 260 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 261 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 262 /* @brief P-Flash start address. */ 263 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 264 /* @brief P-Flash block count. */ 265 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 266 /* @brief P-Flash block size. */ 267 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 268 /* @brief P-Flash sector size. */ 269 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 270 /* @brief P-Flash write unit size. */ 271 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 272 /* @brief P-Flash data path width. */ 273 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 274 /* @brief P-Flash block swap feature. */ 275 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 276 /* @brief P-Flash protection region count. */ 277 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 278 /* @brief Has FlexNVM memory. */ 279 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 280 /* @brief Has FlexNVM alias. */ 281 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 282 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 283 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 284 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 285 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 286 /* @brief FlexNVM block count. */ 287 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 288 /* @brief FlexNVM block size. */ 289 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (65536) 290 /* @brief FlexNVM sector size. */ 291 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (2048) 292 /* @brief FlexNVM write unit size. */ 293 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 294 /* @brief FlexNVM data path width. */ 295 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (8) 296 /* @brief Has FlexRAM memory. */ 297 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 298 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 299 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 300 /* @brief FlexRAM size. */ 301 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 302 /* @brief Has 0x00 Read 1s Block command. */ 303 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 304 /* @brief Has 0x01 Read 1s Section command. */ 305 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 306 /* @brief Has 0x02 Program Check command. */ 307 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 308 /* @brief Has 0x03 Read Resource command. */ 309 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 310 /* @brief Has 0x06 Program Longword command. */ 311 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 312 /* @brief Has 0x07 Program Phrase command. */ 313 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 314 /* @brief Has 0x08 Erase Flash Block command. */ 315 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 316 /* @brief Has 0x09 Erase Flash Sector command. */ 317 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 318 /* @brief Has 0x0B Program Section command. */ 319 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 320 /* @brief Has 0x40 Read 1s All Blocks command. */ 321 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 322 /* @brief Has 0x41 Read Once command. */ 323 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 324 /* @brief Has 0x43 Program Once command. */ 325 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 326 /* @brief Has 0x44 Erase All Blocks command. */ 327 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 328 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 329 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 330 /* @brief Has 0x46 Swap Control command. */ 331 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 332 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 333 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 334 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 335 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 336 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 337 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 338 /* @brief Has 0x80 Program Partition command. */ 339 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 340 /* @brief Has 0x81 Set FlexRAM Function command. */ 341 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 342 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 343 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 344 /* @brief P-Flash Erase sector command address alignment. */ 345 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 346 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 347 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 348 /* @brief P-Flash Read resource command address alignment. */ 349 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 350 /* @brief P-Flash Program check command address alignment. */ 351 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 352 /* @brief P-Flash Program check command address alignment. */ 353 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 354 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 355 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (8) 356 /* @brief FlexNVM Erase sector command address alignment. */ 357 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (8) 358 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 359 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (8) 360 /* @brief FlexNVM Read resource command address alignment. */ 361 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 362 /* @brief FlexNVM Program check command address alignment. */ 363 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 364 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00010000U) 366 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x0000E000U) 368 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0000C000U) 370 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00008000U) 372 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00000000U) 374 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 376 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 378 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 380 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000U) 382 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000U) 384 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000U) 386 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000U) 388 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000U) 390 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 392 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 394 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00010000U) 396 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 398 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 400 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 402 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 404 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 406 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 408 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 410 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 412 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 414 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 416 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 417 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 418 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 419 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 420 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 421 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 422 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 423 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 424 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 425 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 426 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 427 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 428 #elif defined(CPU_MKE18F512VLH16) || defined(CPU_MKE18F512VLL16) 429 /* @brief Is of type FTFA. */ 430 #define FSL_FEATURE_FLASH_IS_FTFA (0) 431 /* @brief Is of type FTFE. */ 432 #define FSL_FEATURE_FLASH_IS_FTFE (1) 433 /* @brief Is of type FTFL. */ 434 #define FSL_FEATURE_FLASH_IS_FTFL (0) 435 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 436 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 437 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 438 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 439 /* @brief Has EEPROM region protection (register FEPROT). */ 440 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 441 /* @brief Has data flash region protection (register FDPROT). */ 442 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 443 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 444 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 445 /* @brief Has flash cache control in FMC module. */ 446 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 447 /* @brief Has flash cache control in MCM module. */ 448 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 449 /* @brief Has flash cache control in MSCM module. */ 450 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1) 451 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 452 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 453 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 454 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 455 /* @brief P-Flash start address. */ 456 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 457 /* @brief P-Flash block count. */ 458 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 459 /* @brief P-Flash block size. */ 460 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 461 /* @brief P-Flash sector size. */ 462 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 463 /* @brief P-Flash write unit size. */ 464 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 465 /* @brief P-Flash data path width. */ 466 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 467 /* @brief P-Flash block swap feature. */ 468 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 469 /* @brief P-Flash protection region count. */ 470 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 471 /* @brief Has FlexNVM memory. */ 472 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 473 /* @brief Has FlexNVM alias. */ 474 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 475 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 476 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 477 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 478 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 479 /* @brief FlexNVM block count. */ 480 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 481 /* @brief FlexNVM block size. */ 482 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (65536) 483 /* @brief FlexNVM sector size. */ 484 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (2048) 485 /* @brief FlexNVM write unit size. */ 486 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 487 /* @brief FlexNVM data path width. */ 488 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (8) 489 /* @brief Has FlexRAM memory. */ 490 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 491 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 492 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 493 /* @brief FlexRAM size. */ 494 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 495 /* @brief Has 0x00 Read 1s Block command. */ 496 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 497 /* @brief Has 0x01 Read 1s Section command. */ 498 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 499 /* @brief Has 0x02 Program Check command. */ 500 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 501 /* @brief Has 0x03 Read Resource command. */ 502 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 503 /* @brief Has 0x06 Program Longword command. */ 504 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 505 /* @brief Has 0x07 Program Phrase command. */ 506 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 507 /* @brief Has 0x08 Erase Flash Block command. */ 508 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 509 /* @brief Has 0x09 Erase Flash Sector command. */ 510 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 511 /* @brief Has 0x0B Program Section command. */ 512 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 513 /* @brief Has 0x40 Read 1s All Blocks command. */ 514 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 515 /* @brief Has 0x41 Read Once command. */ 516 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 517 /* @brief Has 0x43 Program Once command. */ 518 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 519 /* @brief Has 0x44 Erase All Blocks command. */ 520 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 521 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 522 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 523 /* @brief Has 0x46 Swap Control command. */ 524 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 525 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 526 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 527 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 528 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 529 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 530 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 531 /* @brief Has 0x80 Program Partition command. */ 532 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 533 /* @brief Has 0x81 Set FlexRAM Function command. */ 534 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 535 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 536 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 537 /* @brief P-Flash Erase sector command address alignment. */ 538 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 539 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 540 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 541 /* @brief P-Flash Read resource command address alignment. */ 542 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 543 /* @brief P-Flash Program check command address alignment. */ 544 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 545 /* @brief P-Flash Program check command address alignment. */ 546 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 547 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 548 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (8) 549 /* @brief FlexNVM Erase sector command address alignment. */ 550 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (8) 551 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 552 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (8) 553 /* @brief FlexNVM Read resource command address alignment. */ 554 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 555 /* @brief FlexNVM Program check command address alignment. */ 556 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 557 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 558 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00010000U) 559 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 560 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x0000E000U) 561 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 562 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0000C000U) 563 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 564 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00008000U) 565 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 566 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00000000U) 567 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 568 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 569 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 570 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 571 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 572 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 573 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 574 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000U) 575 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 576 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000U) 577 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 578 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000U) 579 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 580 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000U) 581 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 582 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000U) 583 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 584 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 585 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 586 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 587 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 588 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00010000U) 589 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 590 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 591 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 592 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 593 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 594 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 595 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 596 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 597 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 598 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 599 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 600 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 601 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 602 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 603 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 604 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 605 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 606 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 607 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 608 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 609 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 610 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 611 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 612 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 613 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 614 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 615 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 616 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 617 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 618 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 619 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 620 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 621 #endif /* defined(CPU_MKE18F256VLH16) || defined(CPU_MKE18F256VLL16) */ 622 623 /* FTM module features */ 624 625 /* @brief Number of channels. */ 626 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) (8) 627 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 628 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 629 /* @brief Has extended deadtime value. */ 630 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (1) 631 /* @brief Enable pwm output for the module. */ 632 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1) 633 /* @brief Has half-cycle reload for the module. */ 634 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1) 635 /* @brief Has reload interrupt. */ 636 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1) 637 /* @brief Has reload initialization trigger. */ 638 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1) 639 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 640 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 641 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 642 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (1) 643 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 644 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (1) 645 /* @brief If instance has only TPM function. */ 646 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 647 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 648 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (1) 649 650 /* GPIO module features */ 651 652 /* @brief Has GPIO attribute checker register (GACR). */ 653 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 654 655 /* LMEM module features */ 656 657 /* @brief Has process identifier support. */ 658 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0) 659 /* @brief Has L1 cache. */ 660 #define FSL_FEATURE_HAS_L1CACHE (1) 661 /* @brief L1 ICACHE line size in byte. */ 662 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16) 663 /* @brief L1 DCACHE line size in byte. */ 664 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16) 665 666 /* LPI2C module features */ 667 668 /* @brief Has separate DMA RX and TX requests. */ 669 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 670 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 671 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 672 673 /* LPIT module features */ 674 675 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 676 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 677 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 678 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 679 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 680 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0) 681 682 /* LPSPI module features */ 683 684 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 685 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (0) 686 /* @brief Has separate DMA RX and TX requests. */ 687 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 688 689 /* LPTMR module features */ 690 691 /* @brief Has shared interrupt handler with another LPTMR module. */ 692 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 693 /* @brief Whether LPTMR counter is 32 bits width. */ 694 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 695 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 696 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 697 698 /* LPUART module features */ 699 700 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 701 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 702 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 703 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 704 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 705 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 706 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 707 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 708 /* @brief Has 32-bit register MODIR */ 709 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 710 /* @brief Hardware flow control (RTS, CTS) is supported. */ 711 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 712 /* @brief Infrared (modulation) is supported. */ 713 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 714 /* @brief 2 bits long stop bit is available. */ 715 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 716 /* @brief If 10-bit mode is supported. */ 717 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 718 /* @brief If 7-bit mode is supported. */ 719 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 720 /* @brief Baud rate fine adjustment is available. */ 721 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 722 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 723 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 724 /* @brief Baud rate oversampling is available. */ 725 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 726 /* @brief Baud rate oversampling is available. */ 727 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 728 /* @brief Peripheral type. */ 729 #define FSL_FEATURE_LPUART_IS_SCI (1) 730 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 731 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 732 /* @brief Supports two match addresses to filter incoming frames. */ 733 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 734 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 735 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 736 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 737 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 738 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 739 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 740 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 741 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 742 /* @brief Has improved smart card (ISO7816 protocol) support. */ 743 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 744 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 745 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 746 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 747 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 748 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 749 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 750 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 751 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 752 /* @brief Has separate DMA RX and TX requests. */ 753 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 754 /* @brief Has separate RX and TX interrupts. */ 755 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (1) 756 /* @brief Has LPAURT_PARAM. */ 757 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 758 /* @brief Has LPUART_VERID. */ 759 #define FSL_FEATURE_LPUART_HAS_VERID (1) 760 /* @brief Has LPUART_GLOBAL. */ 761 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 762 /* @brief Has LPUART_PINCFG. */ 763 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 764 765 /* MSCM module features */ 766 767 /* @brief Number of configuration information for processors. */ 768 #define FSL_FEATURE_MSCM_HAS_CP_COUNT (1) 769 /* @brief Has data cache. */ 770 #define FSL_FEATURE_MSCM_HAS_DATACACHE (0) 771 772 /* interrupt module features */ 773 774 /* @brief Lowest interrupt request number. */ 775 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 776 /* @brief Highest interrupt request number. */ 777 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (91) 778 779 /* OSC32 module features */ 780 781 /* No feature definitions */ 782 783 /* PDB module features */ 784 785 /* @brief Has DAC support. */ 786 #define FSL_FEATURE_PDB_HAS_DAC (1) 787 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 788 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 789 /* @brief PDB channel number). */ 790 #define FSL_FEATURE_PDB_CHANNEL_COUNT (1) 791 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 792 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (8) 793 /* @brief DAC interval trigger number). */ 794 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 795 /* @brief Pulse out number). */ 796 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (1) 797 798 /* PMC module features */ 799 800 /* @brief Has Bandgap Enable In VLPx Operation support. */ 801 #define FSL_FEATURE_PMC_HAS_BGEN (0) 802 /* @brief Has Bandgap Buffer Enable. */ 803 #define FSL_FEATURE_PMC_HAS_BGBE (0) 804 /* @brief Has Bandgap Buffer Drive Select. */ 805 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 806 /* @brief Has Low-Voltage Detect Voltage Select support. */ 807 #define FSL_FEATURE_PMC_HAS_LVDV (0) 808 /* @brief Has Low-Voltage Warning Voltage Select support. */ 809 #define FSL_FEATURE_PMC_HAS_LVWV (0) 810 /* @brief Has LPO. */ 811 #define FSL_FEATURE_PMC_HAS_LPO (1) 812 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 813 #define FSL_FEATURE_PMC_HAS_VLPO (0) 814 /* @brief Has acknowledge isolation support. */ 815 #define FSL_FEATURE_PMC_HAS_ACKISO (0) 816 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 817 #define FSL_FEATURE_PMC_HAS_REGFPM (1) 818 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 819 #define FSL_FEATURE_PMC_HAS_REGONS (0) 820 /* @brief Has PMC_HVDSC1. */ 821 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 822 /* @brief Has PMC_PARAM. */ 823 #define FSL_FEATURE_PMC_HAS_PARAM (0) 824 /* @brief Has PMC_VERID. */ 825 #define FSL_FEATURE_PMC_HAS_VERID (0) 826 827 /* PORT module features */ 828 829 /* @brief Has control lock (register bit PCR[LK]). */ 830 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 831 /* @brief Has open drain control (register bit PCR[ODE]). */ 832 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 833 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 834 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 835 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 836 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 837 /* @brief Has pull resistor selection available. */ 838 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 839 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 840 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 841 /* @brief Has slew rate control (register bit PCR[SRE]). */ 842 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) 843 /* @brief Has passive filter (register bit field PCR[PFE]). */ 844 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 845 /* @brief Has drive strength control (register bit PCR[DSE]). */ 846 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 847 /* @brief Has separate drive strength register (HDRVE). */ 848 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 849 /* @brief Has glitch filter (register IOFLT). */ 850 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 851 /* @brief Defines width of PCR[MUX] field. */ 852 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 853 /* @brief Has dedicated interrupt vector. */ 854 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 855 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 856 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 857 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 858 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 859 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 860 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 861 862 /* RCM module features */ 863 864 /* @brief Has Loss-of-Lock Reset support. */ 865 #define FSL_FEATURE_RCM_HAS_LOL (1) 866 /* @brief Has Loss-of-Clock Reset support. */ 867 #define FSL_FEATURE_RCM_HAS_LOC (1) 868 /* @brief Has JTAG generated Reset support. */ 869 #define FSL_FEATURE_RCM_HAS_JTAG (1) 870 /* @brief Has EzPort generated Reset support. */ 871 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 872 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 873 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 874 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 875 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 876 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 877 #define FSL_FEATURE_RCM_HAS_SSRS (1) 878 /* @brief Has RCM_VERID. */ 879 #define FSL_FEATURE_RCM_HAS_VERID (1) 880 /* @brief Has RCM_PARAM. */ 881 #define FSL_FEATURE_RCM_HAS_PARAM (1) 882 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 883 #define FSL_FEATURE_RCM_HAS_SRIE (1) 884 /* @brief RCM register bit width. */ 885 #define FSL_FEATURE_RCM_REG_WIDTH (32) 886 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 887 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 888 /* @brief Has MDM-AP system reset support RCM_SRS[MDM_AP] */ 889 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 890 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 891 #define FSL_FEATURE_RCM_HAS_WAKEUP (0) 892 893 /* RTC module features */ 894 895 /* @brief Has wakeup pin. */ 896 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) 897 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 898 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) 899 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 900 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 901 /* @brief Has read/write access control (registers WAR and RAR). */ 902 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 903 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 904 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 905 /* @brief Has RTC_CLKIN available. */ 906 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 907 /* @brief Has prescaler adjust for LPO. */ 908 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) 909 /* @brief Has Clock Pin Enable field. */ 910 #define FSL_FEATURE_RTC_HAS_CPE (1) 911 /* @brief Has Timer Seconds Interrupt Configuration field. */ 912 #define FSL_FEATURE_RTC_HAS_TSIC (1) 913 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 914 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) 915 /* @brief Has Tamper Interrupt Register (register TIR). */ 916 #define FSL_FEATURE_RTC_HAS_TIR (0) 917 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 918 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 919 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 920 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 921 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 922 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 923 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 924 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 925 /* @brief Has Tamper Detect Register (register TDR). */ 926 #define FSL_FEATURE_RTC_HAS_TDR (0) 927 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 928 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 929 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 930 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 931 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 932 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 933 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 934 #define FSL_FEATURE_RTC_HAS_TTSR (0) 935 /* @brief Has Pin Configuration Register (register PCR). */ 936 #define FSL_FEATURE_RTC_HAS_PCR (0) 937 938 /* SCG module features */ 939 940 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ 941 #define FSL_FEATURE_SCG_HAS_DIVPLAT (0) 942 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ 943 #define FSL_FEATURE_SCG_HAS_DIVBUS (1) 944 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ 945 #define FSL_FEATURE_SCG_HAS_DIVEXT (0) 946 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ 947 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) 948 /* @brief Has OSC freq range SOSCCFG[RANGE]. */ 949 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (1) 950 /* @brief Has SOSCCSR[SOSCERCLKEN]. */ 951 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (1) 952 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ 953 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) 954 /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ 955 #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (1) 956 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ 957 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (0) 958 /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ 959 #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1) 960 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ 961 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (0) 962 /* @brief Has SCG_SIRCCSR[LPOPO]. */ 963 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) 964 /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ 965 #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1) 966 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ 967 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (0) 968 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ 969 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) 970 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ 971 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) 972 /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ 973 #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (1) 974 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ 975 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0) 976 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ 977 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) 978 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ 979 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) 980 /* @brief Has SCG_SPLLCFG[PLLS]. */ 981 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) 982 /* @brief Has SCG_SPLLCFG[BYPASS]. */ 983 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) 984 /* @brief Has SCG_SPLLCFG[PFDSEL]. */ 985 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) 986 /* @brief Has SCG_SPLLCSR[SPLLCM]. */ 987 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (1) 988 /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ 989 #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) 990 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ 991 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) 992 /* @brief Has low power FLL, SCG_LPFLLCSR. */ 993 #define FSL_FEATURE_SCG_HAS_LPFLL (0) 994 /* @brief Has low power FLL stop enable. */ 995 #define FSL_FEATURE_SCG_HAS_LPFLLSTEN (0) 996 /* @brief Has system PLL, SCG_SPLLCSR. */ 997 #define FSL_FEATURE_SCG_HAS_SPLL (1) 998 /* @brief Has system PLL PFD, SCG_SPLLPFD. */ 999 #define FSL_FEATURE_SCG_HAS_SPLLPFD (0) 1000 /* @brief Has auxiliary PLL, SCG_APLLCSR. */ 1001 #define FSL_FEATURE_SCG_HAS_APLL (0) 1002 /* @brief Has RTC OSC control, SCG_ROSCCSR. */ 1003 #define FSL_FEATURE_SCG_HAS_ROSC (0) 1004 /* @brief Has RTC OSC clock source. */ 1005 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (0) 1006 /* @brief Has RTC OSC clock out select. */ 1007 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (0) 1008 /* @brief Has SIRC clock out select. */ 1009 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) 1010 /* @brief Has FIRC trim source USB0 Start of Frame. */ 1011 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0) 1012 /* @brief Has FIRC trim source USB1 Start of Frame. */ 1013 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) 1014 /* @brief Has FIRC trim source system OSC. */ 1015 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) 1016 /* @brief Has FIRC trim source RTC OSC. */ 1017 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (0) 1018 1019 /* SMC module features */ 1020 1021 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1022 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1023 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1024 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1025 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1026 #define FSL_FEATURE_SMC_HAS_PORPO (0) 1027 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1028 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1029 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1030 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1031 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1032 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1033 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1034 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1035 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1036 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1037 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1038 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1039 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1040 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1041 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1042 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (0) 1043 /* @brief Has stop submode. */ 1044 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0) 1045 /* @brief Has stop submode 0(state VLLS0 of register bit STOPCTRL[VLLSM]). */ 1046 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) 1047 /* @brief Has stop submode 2(state VLLS2 of register bit STOPCTRL[VLLSM]). */ 1048 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1049 /* @brief Has SMC_PARAM. */ 1050 #define FSL_FEATURE_SMC_HAS_PARAM (1) 1051 /* @brief Has SMC_VERID. */ 1052 #define FSL_FEATURE_SMC_HAS_VERID (1) 1053 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1054 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1055 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1056 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1057 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1058 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1059 /* @brief Width of SMC registers. */ 1060 #define FSL_FEATURE_SMC_REG_WIDTH (32) 1061 1062 /* SYSMPU module features */ 1063 1064 /* @brief Specifies number of descriptors available. */ 1065 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (8) 1066 /* @brief Has process identifier support. */ 1067 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1068 /* @brief Total number of MPU slave. */ 1069 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (4) 1070 /* @brief Total number of MPU master. */ 1071 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (3) 1072 1073 /* SysTick module features */ 1074 1075 /* @brief Systick has external reference clock. */ 1076 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1077 /* @brief Systick external reference clock is core clock divided by this value. */ 1078 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1079 1080 /* WDOG module features */ 1081 1082 /* @brief Watchdog is available. */ 1083 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1084 /* @brief WDOG_CNT can be 32-bit written. */ 1085 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 1086 1087 #endif /* _MKE18F16_FEATURES_H_ */
