1 /* 2 ** ################################################################### 3 ** Version: rev. 1.3, 2018-01-09 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-05-10) 20 ** Initial version 21 ** - rev. 1.1 (2016-10-20) 22 ** Update based on Rev1 RM. 23 ** - rev. 1.2 (2017-04-06) 24 ** Remove TSI. 25 ** Add ISD2FA, ISD3FA, ISD2FB and ISD3FB bits in QuadSPI0_MCR. 26 ** - rev. 1.3 (2018-01-09) 27 ** Add K28FA support. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _MK28FA15_FEATURES_H_ 33 #define _MK28FA15_FEATURES_H_ 34 35 /* SOC module features */ 36 37 /* @brief ADC16 availability on the SoC. */ 38 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 39 /* @brief AIPS availability on the SoC. */ 40 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 41 /* @brief AXBS availability on the SoC. */ 42 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 43 /* @brief MMCAU availability on the SoC. */ 44 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 45 /* @brief CMP availability on the SoC. */ 46 #define FSL_FEATURE_SOC_CMP_COUNT (2) 47 /* @brief CMT availability on the SoC. */ 48 #define FSL_FEATURE_SOC_CMT_COUNT (1) 49 /* @brief CRC availability on the SoC. */ 50 #define FSL_FEATURE_SOC_CRC_COUNT (1) 51 /* @brief DAC availability on the SoC. */ 52 #define FSL_FEATURE_SOC_DAC_COUNT (1) 53 /* @brief EDMA availability on the SoC. */ 54 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 55 /* @brief DMAMUX availability on the SoC. */ 56 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 57 /* @brief DSPI availability on the SoC. */ 58 #define FSL_FEATURE_SOC_DSPI_COUNT (4) 59 /* @brief EWM availability on the SoC. */ 60 #define FSL_FEATURE_SOC_EWM_COUNT (1) 61 /* @brief FB availability on the SoC. */ 62 #define FSL_FEATURE_SOC_FB_COUNT (1) 63 /* @brief FLEXIO availability on the SoC. */ 64 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 65 /* @brief FMC availability on the SoC. */ 66 #define FSL_FEATURE_SOC_FMC_COUNT (1) 67 /* @brief FTFE availability on the SoC. */ 68 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 69 /* @brief FTM availability on the SoC. */ 70 #define FSL_FEATURE_SOC_FTM_COUNT (4) 71 /* @brief GPIO availability on the SoC. */ 72 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 73 /* @brief I2C availability on the SoC. */ 74 #define FSL_FEATURE_SOC_I2C_COUNT (4) 75 /* @brief I2S availability on the SoC. */ 76 #define FSL_FEATURE_SOC_I2S_COUNT (2) 77 /* @brief LLWU availability on the SoC. */ 78 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 79 /* @brief LMEM availability on the SoC. */ 80 #define FSL_FEATURE_SOC_LMEM_COUNT (1) 81 /* @brief LPTMR availability on the SoC. */ 82 #define FSL_FEATURE_SOC_LPTMR_COUNT (2) 83 /* @brief LPUART availability on the SoC. */ 84 #define FSL_FEATURE_SOC_LPUART_COUNT (5) 85 /* @brief MCG availability on the SoC. */ 86 #define FSL_FEATURE_SOC_MCG_COUNT (1) 87 /* @brief MCM availability on the SoC. */ 88 #define FSL_FEATURE_SOC_MCM_COUNT (1) 89 /* @brief SYSMPU availability on the SoC. */ 90 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 91 /* @brief OSC availability on the SoC. */ 92 #define FSL_FEATURE_SOC_OSC_COUNT (1) 93 /* @brief PDB availability on the SoC. */ 94 #define FSL_FEATURE_SOC_PDB_COUNT (1) 95 /* @brief PIT availability on the SoC. */ 96 #define FSL_FEATURE_SOC_PIT_COUNT (1) 97 /* @brief PMC availability on the SoC. */ 98 #define FSL_FEATURE_SOC_PMC_COUNT (1) 99 /* @brief PORT availability on the SoC. */ 100 #define FSL_FEATURE_SOC_PORT_COUNT (5) 101 /* @brief QuadSPI availability on the SoC. */ 102 #define FSL_FEATURE_SOC_QuadSPI_COUNT (1) 103 /* @brief RCM availability on the SoC. */ 104 #define FSL_FEATURE_SOC_RCM_COUNT (1) 105 /* @brief RFSYS availability on the SoC. */ 106 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 107 /* @brief RFVBAT availability on the SoC. */ 108 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 109 /* @brief RTC availability on the SoC. */ 110 #define FSL_FEATURE_SOC_RTC_COUNT (1) 111 /* @brief SDHC availability on the SoC. */ 112 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 113 /* @brief SDRAM availability on the SoC. */ 114 #define FSL_FEATURE_SOC_SDRAM_COUNT (1) 115 /* @brief SIM availability on the SoC. */ 116 #define FSL_FEATURE_SOC_SIM_COUNT (1) 117 /* @brief SMC availability on the SoC. */ 118 #define FSL_FEATURE_SOC_SMC_COUNT (1) 119 /* @brief TPM availability on the SoC. */ 120 #define FSL_FEATURE_SOC_TPM_COUNT (2) 121 /* @brief TRNG availability on the SoC. */ 122 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 123 /* @brief USB availability on the SoC. */ 124 #define FSL_FEATURE_SOC_USB_COUNT (1) 125 /* @brief USBDCD availability on the SoC. */ 126 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 127 /* @brief USBHS availability on the SoC. */ 128 #define FSL_FEATURE_SOC_USBHS_COUNT (1) 129 /* @brief USBHSDCD availability on the SoC. */ 130 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 131 /* @brief USBPHY availability on the SoC. */ 132 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 133 /* @brief VREF availability on the SoC. */ 134 #define FSL_FEATURE_SOC_VREF_COUNT (1) 135 /* @brief WDOG availability on the SoC. */ 136 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 137 138 /* ADC16 module features */ 139 140 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 141 #define FSL_FEATURE_ADC16_HAS_PGA (0) 142 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 143 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 144 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 145 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 146 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 147 #define FSL_FEATURE_ADC16_HAS_DMA (1) 148 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 149 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 150 /* @brief Has FIFO (bit SC4[AFDEP]). */ 151 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 152 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 153 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 154 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 155 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 156 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 157 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 158 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 159 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 160 /* @brief Has HW averaging (bit SC3[AVGE]). */ 161 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 162 /* @brief Has offset correction (register OFS). */ 163 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 164 /* @brief Maximum ADC resolution. */ 165 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 166 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 167 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 168 169 /* CMP module features */ 170 171 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 172 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 173 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 174 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 175 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 176 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 177 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 178 #define FSL_FEATURE_CMP_HAS_DMA (1) 179 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 180 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 181 /* @brief Has DAC Test function in CMP (register DACTEST). */ 182 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 183 184 /* CRC module features */ 185 186 /* @brief Has data register with name CRC */ 187 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 188 189 /* DAC module features */ 190 191 /* @brief Define the size of hardware buffer */ 192 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 193 /* @brief Define whether the buffer supports watermark event detection or not. */ 194 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 195 /* @brief Define whether the buffer supports watermark selection detection or not. */ 196 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 197 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 198 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 199 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 200 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 201 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 202 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 203 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 204 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 205 /* @brief Define whether FIFO buffer mode is available or not. */ 206 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 207 /* @brief Define whether swing buffer mode is available or not.. */ 208 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 209 210 /* EDMA module features */ 211 212 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 213 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 214 /* @brief Total number of DMA channels on all modules. */ 215 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) 216 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 217 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) 218 /* @brief Has DMA_Error interrupt vector. */ 219 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 220 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 221 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 222 /* @brief Channel IRQ entry shared offset. */ 223 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) 224 /* @brief If 8 bytes transfer supported. */ 225 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 226 /* @brief If 16 bytes transfer supported. */ 227 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 228 229 /* DMAMUX module features */ 230 231 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 232 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 233 /* @brief Total number of DMA channels on all modules. */ 234 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32) 235 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 236 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 237 /* @brief Register CHCFGn width. */ 238 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 239 240 /* EWM module features */ 241 242 /* @brief Has clock select (register CLKCTRL). */ 243 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 244 /* @brief Has clock prescaler (register CLKPRESCALER). */ 245 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 246 247 /* FLEXBUS module features */ 248 249 /* No feature definitions */ 250 251 /* FLEXIO module features */ 252 253 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 254 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 255 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 256 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 257 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 258 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 259 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 260 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 261 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 262 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 263 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 264 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 265 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 266 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 267 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 268 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 269 /* @brief Reset value of the FLEXIO_VERID register */ 270 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 271 /* @brief Reset value of the FLEXIO_PARAM register */ 272 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10200808) 273 /* @brief Flexio DMA request base channel */ 274 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (16) 275 276 /* FLASH module features */ 277 278 /* @brief Is of type FTFA. */ 279 #define FSL_FEATURE_FLASH_IS_FTFA (0) 280 /* @brief Is of type FTFE. */ 281 #define FSL_FEATURE_FLASH_IS_FTFE (1) 282 /* @brief Is of type FTFL. */ 283 #define FSL_FEATURE_FLASH_IS_FTFL (0) 284 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 285 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 286 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 287 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 288 /* @brief Has EEPROM region protection (register FEPROT). */ 289 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 290 /* @brief Has data flash region protection (register FDPROT). */ 291 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 292 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 293 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 294 /* @brief Has flash cache control in FMC module. */ 295 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 296 /* @brief Has flash cache control in MCM module. */ 297 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 298 /* @brief Has flash cache control in MSCM module. */ 299 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 300 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 301 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 302 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 303 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 304 /* @brief P-Flash start address. */ 305 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 306 /* @brief P-Flash block count. */ 307 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (4) 308 /* @brief P-Flash block size. */ 309 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 310 /* @brief P-Flash sector size. */ 311 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 312 /* @brief P-Flash write unit size. */ 313 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 314 /* @brief P-Flash data path width. */ 315 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 316 /* @brief P-Flash block swap feature. */ 317 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) 318 /* @brief P-Flash protection region count. */ 319 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16) 320 /* @brief Has FlexNVM memory. */ 321 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 322 /* @brief Has FlexNVM alias. */ 323 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 324 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 325 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 326 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 327 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 328 /* @brief FlexNVM block count. */ 329 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 330 /* @brief FlexNVM block size. */ 331 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 332 /* @brief FlexNVM sector size. */ 333 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 334 /* @brief FlexNVM write unit size. */ 335 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 336 /* @brief FlexNVM data path width. */ 337 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 338 /* @brief Has FlexRAM memory. */ 339 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 340 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 341 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 342 /* @brief FlexRAM size. */ 343 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 344 /* @brief Has 0x00 Read 1s Block command. */ 345 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 346 /* @brief Has 0x01 Read 1s Section command. */ 347 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 348 /* @brief Has 0x02 Program Check command. */ 349 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 350 /* @brief Has 0x03 Read Resource command. */ 351 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 352 /* @brief Has 0x06 Program Longword command. */ 353 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 354 /* @brief Has 0x07 Program Phrase command. */ 355 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 356 /* @brief Has 0x08 Erase Flash Block command. */ 357 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 358 /* @brief Has 0x09 Erase Flash Sector command. */ 359 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 360 /* @brief Has 0x0B Program Section command. */ 361 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 362 /* @brief Has 0x40 Read 1s All Blocks command. */ 363 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 364 /* @brief Has 0x41 Read Once command. */ 365 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 366 /* @brief Has 0x43 Program Once command. */ 367 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 368 /* @brief Has 0x44 Erase All Blocks command. */ 369 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 370 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 371 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 372 /* @brief Has 0x46 Swap Control command. */ 373 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) 374 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 375 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 376 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 377 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 378 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 379 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 380 /* @brief Has 0x80 Program Partition command. */ 381 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 382 /* @brief Has 0x81 Set FlexRAM Function command. */ 383 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 384 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 385 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 386 /* @brief P-Flash Erase sector command address alignment. */ 387 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 388 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 389 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 390 /* @brief P-Flash Read resource command address alignment. */ 391 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 392 /* @brief P-Flash Program check command address alignment. */ 393 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 394 /* @brief P-Flash Program check command address alignment. */ 395 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) 396 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 398 /* @brief FlexNVM Erase sector command address alignment. */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 400 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 402 /* @brief FlexNVM Read resource command address alignment. */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 404 /* @brief FlexNVM Program check command address alignment. */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 406 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 407 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 408 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 409 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 410 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 411 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 412 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 413 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 414 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 415 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 416 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 417 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 418 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 419 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 420 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 421 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 422 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 423 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 424 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 425 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 426 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 427 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 428 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 429 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 430 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 431 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 432 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 433 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 434 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 435 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 436 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 437 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 438 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 439 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 440 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 441 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 442 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 443 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 444 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 445 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 446 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 447 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 448 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 449 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 450 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 451 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 452 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 453 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 454 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 455 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 456 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 457 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 458 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 459 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 460 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 461 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 462 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 463 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 464 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 465 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 466 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 467 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 468 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 469 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 470 471 /* FTM module features */ 472 473 /* @brief Number of channels. */ 474 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 475 (((x) == FTM0) ? (8) : \ 476 (((x) == FTM1) ? (2) : \ 477 (((x) == FTM2) ? (2) : \ 478 (((x) == FTM3) ? (8) : (-1))))) 479 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 480 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 481 /* @brief Has extended deadtime value. */ 482 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 483 /* @brief Enable pwm output for the module. */ 484 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 485 /* @brief Has half-cycle reload for the module. */ 486 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 487 /* @brief Has reload interrupt. */ 488 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 489 /* @brief Has reload initialization trigger. */ 490 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 491 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 492 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 493 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 494 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 495 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 496 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 497 /* @brief Has no QDCTRL. */ 498 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 499 /* @brief If instance has only TPM function. */ 500 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 501 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 502 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0) 503 504 /* GPIO module features */ 505 506 /* @brief Has GPIO attribute checker register (GACR). */ 507 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 508 509 /* I2C module features */ 510 511 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 512 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 513 /* @brief Maximum supported baud rate in kilobit per second. */ 514 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 515 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 516 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 517 /* @brief Has DMA support (register bit C1[DMAEN]). */ 518 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 519 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 520 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 521 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 522 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 523 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 524 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 525 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 526 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 527 /* @brief Has control of the drive capability of the I2C pins. */ 528 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 529 /* @brief Has double buffering support (register S2). */ 530 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) 531 /* @brief Has double buffer enable. */ 532 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 533 534 /* SAI module features */ 535 536 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 537 #define FSL_FEATURE_SAI_HAS_FIFO (1) 538 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 539 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) 540 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 541 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) 542 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 543 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 544 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 545 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 546 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 547 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 548 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 549 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 550 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 551 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 552 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 553 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 554 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 555 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 556 /* @brief Ihe interrupt source number */ 557 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 558 /* @brief Has register of MCR. */ 559 #define FSL_FEATURE_SAI_HAS_MCR (1) 560 /* @brief Has register of MDR */ 561 #define FSL_FEATURE_SAI_HAS_MDR (1) 562 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 563 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 564 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 565 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 566 567 /* LLWU module features */ 568 569 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 570 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26) 571 /* @brief Has pins 8-15 connected to LLWU device. */ 572 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 573 /* @brief Maximum number of internal modules connected to LLWU device. */ 574 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 575 /* @brief Number of digital filters. */ 576 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 577 /* @brief Has MF register. */ 578 #define FSL_FEATURE_LLWU_HAS_MF (1) 579 /* @brief Has PF register. */ 580 #define FSL_FEATURE_LLWU_HAS_PF (1) 581 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 582 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 583 /* @brief Has no internal module wakeup flag register. */ 584 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 585 /* @brief Has external pin 0 connected to LLWU device. */ 586 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 587 /* @brief Index of port of external pin. */ 588 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 589 /* @brief Number of external pin port on specified port. */ 590 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 591 /* @brief Has external pin 1 connected to LLWU device. */ 592 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 593 /* @brief Index of port of external pin. */ 594 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 595 /* @brief Number of external pin port on specified port. */ 596 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 597 /* @brief Has external pin 2 connected to LLWU device. */ 598 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 599 /* @brief Index of port of external pin. */ 600 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 601 /* @brief Number of external pin port on specified port. */ 602 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 603 /* @brief Has external pin 3 connected to LLWU device. */ 604 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 605 /* @brief Index of port of external pin. */ 606 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 607 /* @brief Number of external pin port on specified port. */ 608 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 609 /* @brief Has external pin 4 connected to LLWU device. */ 610 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 611 /* @brief Index of port of external pin. */ 612 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 613 /* @brief Number of external pin port on specified port. */ 614 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 615 /* @brief Has external pin 5 connected to LLWU device. */ 616 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 617 /* @brief Index of port of external pin. */ 618 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 619 /* @brief Number of external pin port on specified port. */ 620 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 621 /* @brief Has external pin 6 connected to LLWU device. */ 622 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 623 /* @brief Index of port of external pin. */ 624 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 625 /* @brief Number of external pin port on specified port. */ 626 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 627 /* @brief Has external pin 7 connected to LLWU device. */ 628 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 629 /* @brief Index of port of external pin. */ 630 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 631 /* @brief Number of external pin port on specified port. */ 632 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 633 /* @brief Has external pin 8 connected to LLWU device. */ 634 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 635 /* @brief Index of port of external pin. */ 636 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 637 /* @brief Number of external pin port on specified port. */ 638 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 639 /* @brief Has external pin 9 connected to LLWU device. */ 640 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 641 /* @brief Index of port of external pin. */ 642 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 643 /* @brief Number of external pin port on specified port. */ 644 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 645 /* @brief Has external pin 10 connected to LLWU device. */ 646 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 647 /* @brief Index of port of external pin. */ 648 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 649 /* @brief Number of external pin port on specified port. */ 650 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 651 /* @brief Has external pin 11 connected to LLWU device. */ 652 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 653 /* @brief Index of port of external pin. */ 654 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 655 /* @brief Number of external pin port on specified port. */ 656 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 657 /* @brief Has external pin 12 connected to LLWU device. */ 658 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 659 /* @brief Index of port of external pin. */ 660 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 661 /* @brief Number of external pin port on specified port. */ 662 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 663 /* @brief Has external pin 13 connected to LLWU device. */ 664 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 665 /* @brief Index of port of external pin. */ 666 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 667 /* @brief Number of external pin port on specified port. */ 668 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 669 /* @brief Has external pin 14 connected to LLWU device. */ 670 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 671 /* @brief Index of port of external pin. */ 672 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 673 /* @brief Number of external pin port on specified port. */ 674 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 675 /* @brief Has external pin 15 connected to LLWU device. */ 676 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 677 /* @brief Index of port of external pin. */ 678 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 679 /* @brief Number of external pin port on specified port. */ 680 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 681 /* @brief Has external pin 16 connected to LLWU device. */ 682 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 683 /* @brief Index of port of external pin. */ 684 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 685 /* @brief Number of external pin port on specified port. */ 686 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 687 /* @brief Has external pin 17 connected to LLWU device. */ 688 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 689 /* @brief Index of port of external pin. */ 690 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 691 /* @brief Number of external pin port on specified port. */ 692 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 693 /* @brief Has external pin 18 connected to LLWU device. */ 694 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 695 /* @brief Index of port of external pin. */ 696 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 697 /* @brief Number of external pin port on specified port. */ 698 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 699 /* @brief Has external pin 19 connected to LLWU device. */ 700 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 701 /* @brief Index of port of external pin. */ 702 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 703 /* @brief Number of external pin port on specified port. */ 704 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 705 /* @brief Has external pin 20 connected to LLWU device. */ 706 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 707 /* @brief Index of port of external pin. */ 708 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 709 /* @brief Number of external pin port on specified port. */ 710 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 711 /* @brief Has external pin 21 connected to LLWU device. */ 712 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 713 /* @brief Index of port of external pin. */ 714 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOA_IDX) 715 /* @brief Number of external pin port on specified port. */ 716 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (21) 717 /* @brief Has external pin 22 connected to LLWU device. */ 718 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 719 /* @brief Index of port of external pin. */ 720 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) 721 /* @brief Number of external pin port on specified port. */ 722 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) 723 /* @brief Has external pin 23 connected to LLWU device. */ 724 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 725 /* @brief Index of port of external pin. */ 726 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) 727 /* @brief Number of external pin port on specified port. */ 728 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) 729 /* @brief Has external pin 24 connected to LLWU device. */ 730 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) 731 /* @brief Index of port of external pin. */ 732 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) 733 /* @brief Number of external pin port on specified port. */ 734 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) 735 /* @brief Has external pin 25 connected to LLWU device. */ 736 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) 737 /* @brief Index of port of external pin. */ 738 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) 739 /* @brief Number of external pin port on specified port. */ 740 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) 741 /* @brief Has external pin 26 connected to LLWU device. */ 742 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 743 /* @brief Index of port of external pin. */ 744 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 745 /* @brief Number of external pin port on specified port. */ 746 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 747 /* @brief Has external pin 27 connected to LLWU device. */ 748 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 749 /* @brief Index of port of external pin. */ 750 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 751 /* @brief Number of external pin port on specified port. */ 752 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 753 /* @brief Has external pin 28 connected to LLWU device. */ 754 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 755 /* @brief Index of port of external pin. */ 756 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 757 /* @brief Number of external pin port on specified port. */ 758 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 759 /* @brief Has external pin 29 connected to LLWU device. */ 760 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 761 /* @brief Index of port of external pin. */ 762 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 763 /* @brief Number of external pin port on specified port. */ 764 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 765 /* @brief Has external pin 30 connected to LLWU device. */ 766 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 767 /* @brief Index of port of external pin. */ 768 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 769 /* @brief Number of external pin port on specified port. */ 770 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 771 /* @brief Has external pin 31 connected to LLWU device. */ 772 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 773 /* @brief Index of port of external pin. */ 774 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 775 /* @brief Number of external pin port on specified port. */ 776 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 777 /* @brief Has internal module 0 connected to LLWU device. */ 778 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 779 /* @brief Has internal module 1 connected to LLWU device. */ 780 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 781 /* @brief Has internal module 2 connected to LLWU device. */ 782 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 783 /* @brief Has internal module 3 connected to LLWU device. */ 784 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 785 /* @brief Has internal module 4 connected to LLWU device. */ 786 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 787 /* @brief Has internal module 5 connected to LLWU device. */ 788 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 789 /* @brief Has internal module 6 connected to LLWU device. */ 790 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 791 /* @brief Has internal module 7 connected to LLWU device. */ 792 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 793 /* @brief Has Version ID Register (LLWU_VERID). */ 794 #define FSL_FEATURE_LLWU_HAS_VERID (0) 795 /* @brief Has Parameter Register (LLWU_PARAM). */ 796 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 797 /* @brief Width of registers of the LLWU. */ 798 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 799 /* @brief Has DMA Enable register (LLWU_DE). */ 800 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 801 802 /* LMEM module features */ 803 804 /* @brief Has process identifier support. */ 805 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1) 806 /* @brief Has L1 cache. */ 807 #define FSL_FEATURE_HAS_L1CACHE (1) 808 /* @brief L1 ICACHE line size in byte. */ 809 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16) 810 /* @brief L1 DCACHE line size in byte. */ 811 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16) 812 813 /* LPTMR module features */ 814 815 /* @brief Has shared interrupt handler with another LPTMR module. */ 816 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (1) 817 /* @brief Whether LPTMR counter is 32 bits width. */ 818 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) 819 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 820 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 821 822 /* LPUART module features */ 823 824 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 825 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 826 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 827 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 828 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 829 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 830 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 831 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 832 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 833 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 834 /* @brief Has 32-bit register MODIR */ 835 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 836 /* @brief Hardware flow control (RTS, CTS) is supported. */ 837 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 838 /* @brief Infrared (modulation) is supported. */ 839 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 840 /* @brief 2 bits long stop bit is available. */ 841 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 842 /* @brief If 10-bit mode is supported. */ 843 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 844 /* @brief If 7-bit mode is supported. */ 845 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 846 /* @brief Baud rate fine adjustment is available. */ 847 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 848 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 849 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 850 /* @brief Baud rate oversampling is available. */ 851 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 852 /* @brief Baud rate oversampling is available. */ 853 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 854 /* @brief Peripheral type. */ 855 #define FSL_FEATURE_LPUART_IS_SCI (1) 856 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 857 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) 858 /* @brief Supports two match addresses to filter incoming frames. */ 859 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 860 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 861 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 862 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 863 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 864 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 865 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 866 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 867 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 868 /* @brief Has improved smart card (ISO7816 protocol) support. */ 869 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 870 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 871 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 872 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 873 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 874 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 875 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 876 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 877 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 878 /* @brief Has separate DMA RX and TX requests. */ 879 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 880 /* @brief Has separate RX and TX interrupts. */ 881 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 882 /* @brief Has LPAURT_PARAM. */ 883 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 884 /* @brief Has LPUART_VERID. */ 885 #define FSL_FEATURE_LPUART_HAS_VERID (0) 886 /* @brief Has LPUART_GLOBAL. */ 887 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 888 /* @brief Has LPUART_PINCFG. */ 889 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 890 891 /* MCG module features */ 892 893 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 894 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 895 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 896 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7) 897 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 898 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) 899 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 900 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000) 901 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 902 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000) 903 /* @brief The PLL clock is divided by 2 before VCO divider. */ 904 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1) 905 /* @brief FRDIV supports 1280. */ 906 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 907 /* @brief FRDIV supports 1536. */ 908 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 909 /* @brief MCGFFCLK divider. */ 910 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 911 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 912 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 913 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 914 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 915 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 916 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 917 /* @brief Has 48MHz internal oscillator. */ 918 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 919 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 920 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 921 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 922 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 923 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 924 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 925 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 926 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 927 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 928 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 929 /* @brief TBD */ 930 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 931 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 932 #define FSL_FEATURE_MCG_HAS_PLL (1) 933 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 934 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 935 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 936 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 937 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 938 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 939 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 940 #define FSL_FEATURE_MCG_HAS_FLL (1) 941 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 942 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) 943 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 944 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 945 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 946 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 947 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 948 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) 949 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 950 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 951 /* @brief Has external clock monitor (register bit C6[CME]). */ 952 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 953 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 954 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 955 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 956 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 957 /* @brief Has PEI mode or PBI mode. */ 958 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 959 /* @brief Reset clock mode is BLPI. */ 960 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 961 962 /* interrupt module features */ 963 964 /* @brief Lowest interrupt request number. */ 965 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 966 /* @brief Highest interrupt request number. */ 967 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (100) 968 969 /* OSC module features */ 970 971 /* @brief Has OSC1 external oscillator. */ 972 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 973 /* @brief Has OSC0 external oscillator. */ 974 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 975 /* @brief Has OSC external oscillator (without index). */ 976 #define FSL_FEATURE_OSC_HAS_OSC (1) 977 /* @brief Number of OSC external oscillators. */ 978 #define FSL_FEATURE_OSC_OSC_COUNT (1) 979 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 980 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 981 982 /* PDB module features */ 983 984 /* @brief Has DAC support. */ 985 #define FSL_FEATURE_PDB_HAS_DAC (1) 986 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 987 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 988 /* @brief PDB channel number). */ 989 #define FSL_FEATURE_PDB_CHANNEL_COUNT (1) 990 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 991 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 992 /* @brief DAC interval trigger number). */ 993 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 994 /* @brief Pulse out number). */ 995 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 996 997 /* PIT module features */ 998 999 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1000 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1001 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1002 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1003 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1004 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1005 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1006 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1007 /* @brief Has timer enable control. */ 1008 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1009 1010 /* PMC module features */ 1011 1012 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1013 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1014 /* @brief Has Bandgap Buffer Enable. */ 1015 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1016 /* @brief Has Bandgap Buffer Drive Select. */ 1017 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1018 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1019 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1020 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1021 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1022 /* @brief Has LPO. */ 1023 #define FSL_FEATURE_PMC_HAS_LPO (0) 1024 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1025 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1026 /* @brief Has acknowledge isolation support. */ 1027 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1028 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1029 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1030 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1031 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1032 /* @brief Has PMC_HVDSC1. */ 1033 #define FSL_FEATURE_PMC_HAS_HVDSC1 (1) 1034 /* @brief Has PMC_PARAM. */ 1035 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1036 /* @brief Has PMC_VERID. */ 1037 #define FSL_FEATURE_PMC_HAS_VERID (0) 1038 1039 /* PORT module features */ 1040 1041 /* @brief Has control lock (register bit PCR[LK]). */ 1042 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1043 /* @brief Has open drain control (register bit PCR[ODE]). */ 1044 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1045 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1046 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1047 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1048 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1049 /* @brief Has pull resistor selection available. */ 1050 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1051 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1052 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1053 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1054 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1055 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1056 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1057 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1058 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1059 /* @brief Has separate drive strength register (HDRVE). */ 1060 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1061 /* @brief Has glitch filter (register IOFLT). */ 1062 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1063 /* @brief Defines width of PCR[MUX] field. */ 1064 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1065 /* @brief Has dedicated interrupt vector. */ 1066 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1067 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1068 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1069 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1070 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1071 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1072 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1073 1074 /* QSPI module features */ 1075 1076 /* @brief QSPI lookup table depth. */ 1077 #define FSL_FEATURE_QSPI_LUT_DEPTH (64) 1078 /* @brief QSPI Tx FIFO depth. */ 1079 #define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) 1080 /* @brief QSPI Rx FIFO depth. */ 1081 #define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) 1082 /* @brief QSPI AHB buffer count. */ 1083 #define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) 1084 /* @brief QSPI AHB buffer size in byte. */ 1085 #define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (512U) 1086 /* @brief QSPI AMBA base address. */ 1087 #define FSL_FEATURE_QSPI_AMBA_BASE (0x68000000U) 1088 /* @brief QSPI AHB buffer ARDB base address. */ 1089 #define FSL_FEATURE_QSPI_ARDB_BASE (0x67000000U) 1090 /* @brief QSPI has command usage error flag. */ 1091 #define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1) 1092 /* @brief QSPI support parallel mode. */ 1093 #define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1) 1094 /* @brief QSPI support dual die. */ 1095 #define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1) 1096 1097 /* RCM module features */ 1098 1099 /* @brief Has Loss-of-Lock Reset support. */ 1100 #define FSL_FEATURE_RCM_HAS_LOL (1) 1101 /* @brief Has Loss-of-Clock Reset support. */ 1102 #define FSL_FEATURE_RCM_HAS_LOC (1) 1103 /* @brief Has JTAG generated Reset support. */ 1104 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1105 /* @brief Has EzPort generated Reset support. */ 1106 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1107 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1108 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1109 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1110 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 1111 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1112 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1113 /* @brief Has Version ID Register (RCM_VERID). */ 1114 #define FSL_FEATURE_RCM_HAS_VERID (0) 1115 /* @brief Has Parameter Register (RCM_PARAM). */ 1116 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1117 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1118 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1119 /* @brief Width of registers of the RCM. */ 1120 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1121 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1122 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1123 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1124 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1125 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1126 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1127 1128 /* RTC module features */ 1129 1130 /* @brief Has wakeup pin. */ 1131 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1132 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1133 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1134 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1135 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1136 /* @brief Has read/write access control (registers WAR and RAR). */ 1137 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1138 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1139 #define FSL_FEATURE_RTC_HAS_SECURITY (1) 1140 /* @brief Has RTC_CLKIN available. */ 1141 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1142 /* @brief Has prescaler adjust for LPO. */ 1143 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1144 /* @brief Has Clock Pin Enable field. */ 1145 #define FSL_FEATURE_RTC_HAS_CPE (0) 1146 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1147 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1148 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1149 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1150 /* @brief Has Tamper Interrupt Register (register TIR). */ 1151 #define FSL_FEATURE_RTC_HAS_TIR (0) 1152 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1153 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1154 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1155 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1156 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1157 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1158 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1159 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1160 /* @brief Has Tamper Detect Register (register TDR). */ 1161 #define FSL_FEATURE_RTC_HAS_TDR (0) 1162 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1163 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1164 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1165 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1166 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1167 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1168 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1169 #define FSL_FEATURE_RTC_HAS_TTSR (0) 1170 /* @brief Has Pin Configuration Register (register PCR). */ 1171 #define FSL_FEATURE_RTC_HAS_PCR (0) 1172 1173 /* SDHC module features */ 1174 1175 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ 1176 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0) 1177 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ 1178 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) 1179 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ 1180 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) 1181 1182 /* SIM module features */ 1183 1184 /* @brief Has USB FS divider. */ 1185 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1186 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1187 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1188 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1189 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1190 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1191 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1192 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1193 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1194 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1195 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1196 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1197 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1198 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1199 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1200 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1201 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1) 1202 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1203 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1204 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1205 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1206 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1207 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1208 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1209 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1210 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1211 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1212 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1213 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (5) 1214 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1215 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) 1216 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1217 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1218 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1219 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1220 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1221 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1222 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1223 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1224 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1225 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1226 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1227 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1228 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1229 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) 1230 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1231 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1232 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1233 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) 1234 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1235 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) 1236 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1237 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1238 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1239 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1240 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1241 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1242 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1243 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1244 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1245 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1246 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1247 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1248 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1249 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1250 /* @brief Has FTM module(s) configuration. */ 1251 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1252 /* @brief Number of FTM modules. */ 1253 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1254 /* @brief Number of FTM triggers with selectable source. */ 1255 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1256 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1257 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1258 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1259 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1260 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1261 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1262 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1263 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1264 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1265 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1266 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1267 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1268 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1269 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1270 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1271 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1272 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1273 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1274 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1275 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1276 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1277 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1278 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1279 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1280 /* @brief Has TPM module(s) configuration. */ 1281 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1282 /* @brief The highest TPM module index. */ 1283 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1284 /* @brief Has TPM module with index 0. */ 1285 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1286 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1287 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1288 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1289 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1290 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1291 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1292 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1293 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1294 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1295 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) 1296 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1297 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1298 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1299 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1300 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1301 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1302 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1303 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1304 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1305 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1306 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1307 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1308 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1309 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) 1310 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1311 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1312 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1313 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1314 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1315 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1316 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1317 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1318 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1319 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1320 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1321 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1322 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1323 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) 1324 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1325 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1326 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1327 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1328 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1329 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) 1330 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1331 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1332 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1333 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1334 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1335 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1336 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1337 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1338 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1339 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1340 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1341 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1342 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1343 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1344 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1345 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1346 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1347 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1348 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1349 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1350 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1351 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1352 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1353 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1354 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1355 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1356 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1357 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1358 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1359 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1360 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1361 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1362 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1363 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1364 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1365 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1366 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1367 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1368 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1369 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) 1370 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1371 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1372 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1373 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1374 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1375 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) 1376 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1377 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1378 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1379 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) 1380 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1381 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1382 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1383 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1384 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1385 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1386 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1387 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1388 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1389 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1390 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1391 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1392 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1393 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1394 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1395 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1396 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1397 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1398 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1399 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1400 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1401 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) 1402 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1403 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) 1404 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1405 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) 1406 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1407 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1408 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1409 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1410 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1411 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1412 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1413 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1414 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1415 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) 1416 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1417 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) 1418 /* @brief Has miscellanious control register (register MCR). */ 1419 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1420 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1421 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1422 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1423 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1424 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1425 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1426 /* @brief Has UIDH registers. */ 1427 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1428 /* @brief Has UIDM registers. */ 1429 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1430 1431 /* SMC module features */ 1432 1433 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1434 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1435 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1436 #define FSL_FEATURE_SMC_HAS_LPOPO (1) 1437 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1438 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1439 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1440 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1441 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1442 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1443 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1444 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1445 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1446 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1447 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1448 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1449 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1450 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1451 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1452 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1453 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1454 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1455 /* @brief Has stop submode. */ 1456 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1457 /* @brief Has stop submode 0(VLLS0). */ 1458 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) 1459 /* @brief Has stop submode 1(VLLS1). */ 1460 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (0) 1461 /* @brief Has stop submode 2(VLLS2). */ 1462 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1463 /* @brief Has SMC_PARAM. */ 1464 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1465 /* @brief Has SMC_VERID. */ 1466 #define FSL_FEATURE_SMC_HAS_VERID (0) 1467 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1468 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1469 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1470 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1471 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1472 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1473 /* @brief Width of SMC registers. */ 1474 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1475 1476 /* DSPI module features */ 1477 1478 /* @brief Receive/transmit FIFO size in number of items. */ 1479 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1480 /* @brief Maximum transfer data width in bits. */ 1481 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1482 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1483 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1484 /* @brief Number of chip select pins. */ 1485 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1486 /* @brief Number of CTAR registers. */ 1487 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1488 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1489 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1490 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1491 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1492 /* @brief Has 16-bit data transfer support. */ 1493 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1494 /* @brief Has separate DMA RX and TX requests. */ 1495 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1496 1497 /* SYSMPU module features */ 1498 1499 /* @brief Specifies number of descriptors available. */ 1500 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 1501 /* @brief Has process identifier support. */ 1502 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1503 /* @brief Total number of MPU slave. */ 1504 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (7) 1505 /* @brief Total number of MPU master. */ 1506 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (6) 1507 1508 /* SysTick module features */ 1509 1510 /* @brief Systick has external reference clock. */ 1511 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1512 /* @brief Systick external reference clock is core clock divided by this value. */ 1513 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1514 1515 /* TPM module features */ 1516 1517 /* @brief Bus clock is the source clock for the module. */ 1518 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1519 /* @brief Number of channels. */ 1520 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (2) 1521 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1522 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1523 /* @brief Has TPM_PARAM. */ 1524 #define FSL_FEATURE_TPM_HAS_PARAM (0) 1525 /* @brief Has TPM_VERID. */ 1526 #define FSL_FEATURE_TPM_HAS_VERID (0) 1527 /* @brief Has TPM_GLOBAL. */ 1528 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 1529 /* @brief Has TPM_TRIG. */ 1530 #define FSL_FEATURE_TPM_HAS_TRIG (0) 1531 /* @brief Whether TRIG register has effect. */ 1532 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) 1533 /* @brief Has counter pause on trigger. */ 1534 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1535 /* @brief Has external trigger selection. */ 1536 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1537 /* @brief Has TPM_COMBINE register. */ 1538 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 1539 /* @brief Whether COMBINE register has effect. */ 1540 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 1541 /* @brief Has TPM_POL. */ 1542 #define FSL_FEATURE_TPM_HAS_POL (1) 1543 /* @brief Whether POL register has effect. */ 1544 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 1545 /* @brief Has TPM_FILTER register. */ 1546 #define FSL_FEATURE_TPM_HAS_FILTER (1) 1547 /* @brief Whether FILTER register has effect. */ 1548 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 1549 /* @brief Has TPM_QDCTRL register. */ 1550 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 1551 /* @brief Whether QDCTRL register has effect. */ 1552 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 1553 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 1554 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 1555 /* @brief Whether 32 bits counter has effect. */ 1556 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 1557 1558 /* USB module features */ 1559 1560 /* @brief KHCI module instance count */ 1561 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1562 /* @brief HOST mode enabled */ 1563 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 1564 /* @brief OTG mode enabled */ 1565 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 1566 /* @brief Size of the USB dedicated RAM */ 1567 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 1568 /* @brief Has KEEP_ALIVE_CTRL register */ 1569 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1570 /* @brief Has the Dynamic SOF threshold compare support */ 1571 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) 1572 /* @brief Has the VBUS detect support */ 1573 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) 1574 /* @brief Has the IRC48M module clock support */ 1575 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) 1576 /* @brief Number of endpoints supported */ 1577 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1578 /* @brief Has STALL_IL/OL_DIS registers */ 1579 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 1580 /* @brief Has STALL_IH/OH_DIS registers */ 1581 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 1582 1583 /* USBHS module features */ 1584 1585 /* @brief EHCI module instance count */ 1586 #define FSL_FEATURE_USBHS_EHCI_COUNT (1) 1587 /* @brief Number of endpoints supported */ 1588 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 1589 1590 /* VREF module features */ 1591 1592 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1593 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1594 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1595 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1596 /* @brief If high/low buffer mode supported */ 1597 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1598 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1599 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1600 /* @brief Has VREF_TRM4. */ 1601 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1602 1603 /* WDOG module features */ 1604 1605 /* @brief Watchdog is available. */ 1606 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1607 /* @brief Has Wait mode support. */ 1608 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1609 1610 #endif /* _MK28FA15_FEATURES_H_ */ 1611 1612
