1 /*
2 ** ###################################################################
3 ** Processors: MK02FN128VFM10
4 ** MK02FN128VLF10
5 ** MK02FN128VLH10
6 ** MK02FN64VFM10
7 ** MK02FN64VLF10
8 ** MK02FN64VLH10
9 **
10 ** Compilers: Freescale C/C++ for Embedded ARM
11 ** GNU C Compiler
12 ** IAR ANSI C/C++ Compiler for ARM
13 ** Keil ARM C/C++ Compiler
14 ** MCUXpresso Compiler
15 **
16 ** Reference manual: K02P64M100SFARM, Rev. 0, February 14, 2014
17 ** Version: rev. 0.5, 2015-02-19
18 ** Build: b181105
19 **
20 ** Abstract:
21 ** Provides a system configuration function and a global variable that
22 ** contains the system frequency. It configures the device and initializes
23 ** the oscillator (PLL) that is part of the microcontroller device.
24 **
25 ** Copyright 2016 Freescale Semiconductor, Inc.
26 ** Copyright 2016-2018 NXP
27 ** All rights reserved.
28 **
29 ** SPDX-License-Identifier: BSD-3-Clause
30 **
31 ** http: www.nxp.com
32 ** mail: support@nxp.com
33 **
34 ** Revisions:
35 ** - rev. 0.1 (2014-02-24)
36 ** Initial version
37 ** - rev. 0.2 (2014-07-15)
38 ** Module access macro module_BASES replaced by module_BASE_PTRS.
39 ** Update of system and startup files.
40 ** - rev. 0.3 (2014-08-28)
41 ** Update of system files - default clock configuration changed.
42 ** Update of startup files - possibility to override DefaultISR added.
43 ** - rev. 0.4 (2014-10-14)
44 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
45 ** - rev. 0.5 (2015-02-19)
46 ** Renamed interrupt vector LLW to LLWU.
47 **
48 ** ###################################################################
49 */
50
51 /*!
52 * @file MK02F12810
53 * @version 0.5
54 * @date 2015-02-19
55 * @brief Device specific configuration file for MK02F12810 (implementation file)
56 *
57 * Provides a system configuration function and a global variable that contains
58 * the system frequency. It configures the device and initializes the oscillator
59 * (PLL) that is part of the microcontroller device.
60 */
61
62 #include <stdint.h>
63 #include "fsl_device_registers.h"
64
65
66
67 /* ----------------------------------------------------------------------------
68 -- Core clock
69 ---------------------------------------------------------------------------- */
70
71 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
72
73 /* ----------------------------------------------------------------------------
74 -- SystemInit()
75 ---------------------------------------------------------------------------- */
76
SystemInit(void)77 void SystemInit (void) {
78 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
79 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
80 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
81
82 #if (DISABLE_WDOG)
83 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
84 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
85 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
86 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
87 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
88 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
89 WDOG_STCTRLH_WAITEN_MASK |
90 WDOG_STCTRLH_STOPEN_MASK |
91 WDOG_STCTRLH_ALLOWUPDATE_MASK |
92 WDOG_STCTRLH_CLKSRC_MASK |
93 0x0100U;
94 #endif /* (DISABLE_WDOG) */
95
96 SystemInitHook();
97 }
98
99 /* ----------------------------------------------------------------------------
100 -- SystemCoreClockUpdate()
101 ---------------------------------------------------------------------------- */
102
SystemCoreClockUpdate(void)103 void SystemCoreClockUpdate (void) {
104
105 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
106 uint16_t Divider;
107 uint8_t tmpC7 = 0;
108
109 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
110 /* FLL is selected */
111 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
112 /* External reference clock is selected */
113 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
114 case 0x00U:
115 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
116 break;
117 case 0x02U:
118 default:
119 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
120 break;
121 }
122 tmpC7 = MCG->C7;
123 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
124 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
125 case 0x38U:
126 Divider = 1536U;
127 break;
128 case 0x30U:
129 Divider = 1280U;
130 break;
131 default:
132 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
133 break;
134 }
135 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
136 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
137 }
138 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
139 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
140 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
141 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
142 /* Select correct multiplier to calculate the MCG output clock */
143 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
144 case 0x00U:
145 MCGOUTClock *= 640U;
146 break;
147 case 0x20U:
148 MCGOUTClock *= 1280U;
149 break;
150 case 0x40U:
151 MCGOUTClock *= 1920U;
152 break;
153 case 0x60U:
154 MCGOUTClock *= 2560U;
155 break;
156 case 0x80U:
157 MCGOUTClock *= 732U;
158 break;
159 case 0xA0U:
160 MCGOUTClock *= 1464U;
161 break;
162 case 0xC0U:
163 MCGOUTClock *= 2197U;
164 break;
165 case 0xE0U:
166 MCGOUTClock *= 2929U;
167 break;
168 default:
169 MCGOUTClock *= 640U;
170 break;
171 }
172 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
173 /* Internal reference clock is selected */
174 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
175 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
176 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
177 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
178 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
179 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
180 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
181 /* External reference clock is selected */
182 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
183 case 0x00U:
184 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
185 break;
186 case 0x02U:
187 default:
188 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
189 break;
190 }
191 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
192 /* Reserved value */
193 return;
194 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
195 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
196 }
197
198 /* ----------------------------------------------------------------------------
199 -- SystemInitHook()
200 ---------------------------------------------------------------------------- */
201
SystemInitHook(void)202 __attribute__ ((weak)) void SystemInitHook (void) {
203 /* Void implementation of the weak function. */
204 }
205
