1 /*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef FSL_RESET_H_
8 #define FSL_RESET_H_
9
10 #include <assert.h>
11 #include <stdbool.h>
12 #include <stdint.h>
13 #include <string.h>
14 #include "fsl_device_registers.h"
15
16 /*!
17 * @addtogroup reset
18 * @{
19 */
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24
25 /*! @name Driver version */
26 /*@{*/
27 /*! @brief reset driver version 2.0.1. */
28 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
29 /*@}*/
30
31 #if defined(MIMXRT798S_hifi1_SERIES) || defined(MIMXRT798S_cm33_core1_SERIES) || \
32 defined(MIMXRT758S_cm33_core1_SERIES) || defined(MIMXRT735S_cm33_core1_SERIES)
33 #define FSL_RESET_DRIVER_SENSE
34 #elif defined(MIMXRT798S_hifi4_SERIES) || defined(MIMXRT798S_cm33_core0_SERIES) || \
35 defined(MIMXRT758S_cm33_core0_SERIES) || defined(MIMXRT735S_cm33_core0_SERIES)
36 #define FSL_RESET_DRIVER_COMPUTE
37 #elif defined(MIMXRT798S_ezhv_SERIES)
38 #define FSL_RESET_DRIVER_MEDIA
39 #else
40 #error "Unsupported core!"
41 #endif
42
43 /*!
44 * @brief Reset control registers index
45 */
46 /* RSTCTL0, RSTCTL_COM_VDD2 */
47 #define RST_CTL0_PSCCTL0 0
48 #define RST_CTL0_PSCCTL1 1
49 #define RST_CTL0_PSCCTL2 2
50 #define RST_CTL0_PSCCTL3 3
51 #define RST_CTL0_PSCCTL4 4
52 #define RST_CTL0_PSCCTL5 5
53 /* RSTCTL1, RSTCTL_VDD1_SENSE */
54 #define RST_CTL1_PSCCTL0 6
55 /* RSTCTL2, RSTCTL_COMN_VDDN */
56 #define RST_CTL2_PSCCTL0 7
57 /* RSTCTL3, RSTCTL_VDD1_COM */
58 #define RST_CTL3_PSCCTL0 8
59 #define RST_CTL3_PSCCTL1 9
60 /* RSTCTL4, RSTCTL_MED_VDD2 */
61 #define RST_CTL4_PSCCTL0 10
62 #define RST_CTL4_PSCCTL1 11
63
64 /*!
65 * @brief Enumeration for system reset status bits
66 *
67 * Defines the enumeration for system reset status bits in SYSRSTSTAT register
68 */
69 typedef enum _rstctl_reset_source
70 {
71 kRSTCTL_SourceVddPor = RSTCTL3_SYSRSTSTAT_VDD_POR_MASK, /*!< VDD Power-On Reset(POR) */
72 kRSTCTL_SourcePad = RSTCTL3_SYSRSTSTAT_RESETN_RESET_MASK, /*!< PPAD Reset */
73 kRSTCTL_SourceIspAp = RSTCTL3_SYSRSTSTAT_ISP_AP_RESET_MASK, /*!< ISP_AP reset Reset */
74 kRSTCTL_SourceItrcSw = RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK, /*!< ITRC_SW (Intrusion and Tamper Response
75 Controller SW) Reset */
76 kRSTCTL_SourceCpu0 = RSTCTL3_SYSRSTSTAT_CPU0_RESET_MASK, /*!< VDD2_COMP Core Reset */
77 kRSTCTL_SourceCpu1 = RSTCTL3_SYSRSTSTAT_CPU1_RESET_MASK, /*!< VDD1_SENSE Core Reset */
78 kRSTCTL_SourceWwdt0 = RSTCTL3_SYSRSTSTAT_WWDT0_RESET_MASK, /*!< WatchDog Timer 0 Reset */
79 kRSTCTL_SourceWwdt1 = RSTCTL3_SYSRSTSTAT_WWDT1_RESET_MASK, /*!< WatchDog Timer 1 Reset*/
80 kRSTCTL_SourceWwdt2 = RSTCTL3_SYSRSTSTAT_WWDT2_RESET_MASK, /*!< WatchDog Timer 2 Reset */
81 kRSTCTL_SourceWwdt3 = RSTCTL3_SYSRSTSTAT_WWDT3_RESET_MASK, /*!< WatchDog Timer 3 Reset*/
82 kRSTCTL_SourceCdog0 = RSTCTL3_SYSRSTSTAT_CDOG0_RESET_MASK, /*!< Code WatchDog Timer 0 Reset */
83 kRSTCTL_SourceCdog1 = RSTCTL3_SYSRSTSTAT_CDOG1_RESET_MASK, /*!< Code WatchDog Timer 1 Reset */
84 kRSTCTL_SourceCdog2 = RSTCTL3_SYSRSTSTAT_CDOG2_RESET_MASK, /*!< Code WatchDog Timer 2 Reset */
85 kRSTCTL_SourceCdog3 = RSTCTL3_SYSRSTSTAT_CDOG3_RESET_MASK, /*!< Code WatchDog Timer 3 Reset */
86 kRSTCTL_SourceCdog4 = RSTCTL3_SYSRSTSTAT_CDOG4_RESET_MASK, /*!< Code WatchDog Timer 4 Reset */
87 kRSTCTL_SourceAll = (int)0xffffffffU,
88 } rstctl_reset_source_t;
89
90 /*!
91 * @brief Enumeration for peripheral reset control bits
92 *
93 * Defines the enumeration for peripheral reset control bits in RSTCLTx registers
94 */
95 typedef enum _RSTCTL_RSTn
96 {
97 kIOPCTL0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 6U, /*!< IOPCTL0 reset control */
98
99 kELS_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 0U, /*!< ELS S50 reset control */
100
101 kDMA0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 5U, /*!< eDMA0 reset control */
102 kDMA1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 6U, /*!< eDMA1 reset control */
103 kPKC_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 8U, /*!< PKC reset control */
104 kXSPI0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 10U, /*!< XSPI0 reset control */
105 kXSPI1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 11U, /*!< XSPI1 reset control */
106 kGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 18U, /*!< GPIO0 reset control */
107 kGPIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 19U, /*!< GPIO1 reset control */
108 kGPIO2_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 20U, /*!< GPIO2 reset control */
109 kGPIO3_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 21U, /*!< GPIO3 reset control */
110 kGPIO4_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 22U, /*!< GPIO4 reset control */
111 kGPIO5_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 23U, /*!< GPIO5 reset control */
112 kGPIO6_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 24U, /*!< GPIO6 reset control */
113 kGPIO7_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 25U, /*!< GPIO7 reset control */
114 kSCT0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 26U, /*!< SCT0 reset control */
115 kFC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 30U, /*!< LP_FLEXCOMM0 reset control */
116 kFC1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 31U, /*!< LP_FLEXCOMM1 reset control */
117
118 kFC2_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 0U, /*!< LP_FLEXCOMM2 reset control */
119 kFC3_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 1U, /*!< LP_FLEXCOMM3 reset control */
120 kFC4_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 2U, /*!< LP_FLEXCOMM4 reset control */
121 kFC5_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 3U, /*!< LP_FLEXCOMM5 reset control */
122 kFC6_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 4U, /*!< LP_FLEXCOMM6 reset control */
123 kFC7_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 5U, /*!< LP_FLEXCOMM7 reset control */
124 kFC8_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 6U, /*!< LP_FLEXCOMM8 reset control */
125 kFC9_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 7U, /*!< LP_FLEXCOMM9 reset control */
126 kFC10_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 8U, /*!< LP_FLEXCOMM10 reset control */
127 kFC11_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 9U, /*!< LP_FLEXCOMM11 reset control */
128 kFC12_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 10U, /*!< LP_FLEXCOMM12 reset control */
129 kFC13_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 11U, /*!< LP_FLEXCOMM13 reset control */
130 kSAI0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 13U, /*!< SAI0 reset control */
131 kSAI1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 14U, /*!< SAI1 reset control */
132 kSAI2_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 15U, /*!< SAI2 reset control */
133 kI3C0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 16U, /*!< I3C0 reset control */
134 kI3C1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 17U, /*!< I3C1 reset control */
135 kCRC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 18U, /*!< CRC0 reset control */
136 kCTIMER0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 21U, /*!< CTIMER0 reset control */
137 kCTIMER1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 22U, /*!< CTIMER1 reset control */
138 kCTIMER2_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 23U, /*!< CTIMER2 reset control */
139 kCTIMER3_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 24U, /*!< CTIMER3 reset control */
140 kCTIMER4_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 25U, /*!< CTIMER4 reset control */
141 kMRT0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 26U, /*!< MRT0 reset control */
142 kUTICK0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 27U, /*!< UTICK0 reset control */
143 kSEMA424_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 30U, /*!< SEMA42_4 reset control */
144 kMU4_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL3 << 8) | 31U, /*!< MU4 reset control */
145
146 kSYSPM2_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 0U, /*!< SYSPM_XSPI0 reset control */
147 kSYSPM3_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 1U, /*!< SYSPM_XSPI1 reset control */
148 kSAFO_SGI_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 2U, /*!< SAFO_SGI reset control */
149 #if defined(FSL_RESET_DRIVER_COMPUTE)
150 kPINT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 5U, /*!< PINT0 reset control */
151 #endif
152 kINPUTMUX0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 7U, /*!< INPUTMUX0 reset control */
153 kFREQME0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 8U, /*!< FREQME0 reset control */
154 kSYSPM0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 10U, /*!< SYSPM_PC reset control */
155 kSYSPM1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 11U, /*!< SYSPM_PS reset control */
156 kNPU0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL4 << 8) | 12U, /*!< NPU0 reset control */
157
158 kHIFI4_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL5 << 8) | 0U, /*!< HiFi4 reset control */
159 kHIFI4_DEBUG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL5 << 8) | 2U, /*!< HiFi4 Debug reset control */
160
161 kHIFI1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 1U, /*!< HiFi1 reset control */
162 kHIFI1_DEBUG_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 2U, /*!< HiFi1 Debug reset control */
163 kDMA2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 4U, /*!< eDMA2 reset control */
164 kDMA3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 5U, /*!< eDMA3 reset control */
165 kFC17_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 6U, /*!< LP_FLEXCOMM17 reset control */
166 kFC18_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 7U, /*!< LP_FLEXCOMM18 reset control */
167 kFC19_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 8U, /*!< LP_FLEXCOMM19 reset control */
168 kFC20_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 9U, /*!< LP_FLEXCOMM20 reset control */
169 kSAI3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 10U, /*!< SAI3 reset control */
170 kI3C2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 11U, /*!< I3C2 reset control */
171 kI3C3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 12U, /*!< I3C3 reset control */
172 kGPIO8_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 13U, /*!< GPIO8 reset control */
173 kGPIO9_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 14U, /*!< GPIO9 reset control */
174 kGPIO10_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 15U, /*!< GPIO10 reset control */
175 #if defined(FSL_RESET_DRIVER_SENSE)
176 kPINT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 16U, /*!< PINT1 reset control */
177 #endif
178 kCTIMER5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 17U, /*!< CTIMER5 reset control */
179 kCTIMER6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 18U, /*!< CTIMER6 reset control */
180 kCTIMER7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 19U, /*!< CTIMER7 reset control */
181 kMRT1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 20U, /*!< MRT1 reset control */
182 kUTICK1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 21U, /*!< UTICK1 reset control */
183 kMU3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 24U, /*!< MU3 reset control */
184 kSEMA423_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 25U, /*!< SEMA42_3 reset control */
185 kPVT1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 28U, /*!< PVT1 reset control */
186
187 kIOPCTL2_RST_SHIFT_RSTn = (RST_CTL2_PSCCTL0 << 8) | 1U, /*!< IOPCTL2 reset control */
188
189 kIOPCTL1_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL0 << 8) | 0U, /*!< IOPCTL1 reset control */
190 kCPU1_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL0 << 8) | 31U, /*!< CPU1 reset control */
191 kMU0_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 1U, /*!< MU0 reset control */
192 kMU1_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 2U, /*!< MU1 reset control */
193 kMU2_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 3U, /*!< MU2 reset control */
194 kSEMA420_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 5U, /*!< SEMA42_0 reset control */
195 kADC0_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 6U, /*!< ADC0 reset control */
196 kSDADC0_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 7U, /*!< SDADC0 reset control */
197 kACMP0_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 8U, /*!< ACMP0 reset control */
198 kPDM_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 9U, /*!< MICFIL/PDM reset control */
199 kINPUTMUX1_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 14U, /*!< INPUTMUX1 reset control */
200 kLPI2C15_RST_SHIFT_RSTn = (RST_CTL3_PSCCTL1 << 8) | 18U, /*!< LPI2C15 reset control */
201
202 kVGPU_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 2U, /*!< VGPU reset control */
203 kLCDIF_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 3U, /*!< LCDIF reset control */
204 kMIPI_DSI_CTRL_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 4U, /*!< MIPIDSI reset control */
205 kEZHV_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 5U, /*!< EZHV reset control */
206 kJPEGDEC_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 6U, /*!< JPEGDEC reset control */
207 kPNGDEC_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 7U, /*!< PNGDEC reset control */
208 kXSPI2_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 8U, /*!< XSPI2 and MMU2 reset control */
209 kLPSPI14_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 13U, /*!< LPSPI14 reset control */
210 kLPSPI16_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 14U, /*!< LPSPI16 reset control */
211 kFLEXIO0_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL0 << 8) | 15U, /*!< FLEXIO0 reset control */
212
213 kUSB0_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL1 << 8) | 0U, /*!< USB0 reset control */
214 kUSBPHY0_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL1 << 8) | 1U, /*!< USBPHY0 reset control */
215 kUSB1_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL1 << 8) | 2U, /*!< USB1 reset control */
216 kUSDHC0_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL1 << 8) | 4U, /*!< USDHC0 reset control */
217 kUSDHC1_RST_SHIFT_RSTn = (RST_CTL4_PSCCTL1 << 8) | 5U, /*!< USDHC1 reset control */
218 } RSTCTL_RSTn_t;
219
220 /** Array initializers with peripheral reset bits **/
221 #define ADC_RSTS \
222 { \
223 kADC0_RST_SHIFT_RSTn \
224 } /* Reset bits for ADC peripheral */
225 #define SDADC_RSTS \
226 { \
227 kSDADC0_RST_SHIFT_RSTn \
228 } /* Reset bits for SDADC peripheral */
229 #define CRC_RSTS \
230 { \
231 kCRC0_RST_SHIFT_RSTn \
232 } /* Reset bits for CRC peripheral */
233 #define CTIMER_RSTS \
234 { \
235 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
236 kCTIMER4_RST_SHIFT_RSTn, kCTIMER5_RST_SHIFT_RSTn, kCTIMER6_RST_SHIFT_RSTn, kCTIMER7_RST_SHIFT_RSTn \
237 } /* Reset bits for TIMER peripheral */
238 #define MIPI_DSI_RSTS \
239 { \
240 kMIPI_DSI_CTRL_RST_SHIFT_RSTn \
241 } /* Reset bits for MIPI_DSI peripheral */
242 #define LCDIF_RSTS \
243 { \
244 kLCDIF_RST_SHIFT_RSTn \
245 } /* Reset bits for LCDIF peripheral */
246 #define LP_FLEXCOMM_RSTS \
247 { \
248 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
249 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, \
250 kFC10_RST_SHIFT_RSTn, kFC11_RST_SHIFT_RSTn, kFC12_RST_SHIFT_RSTn, kFC13_RST_SHIFT_RSTn, (RSTCTL_RSTn_t)0U, \
251 (RSTCTL_RSTn_t)0U, (RSTCTL_RSTn_t)0U, kFC17_RST_SHIFT_RSTn, kFC18_RST_SHIFT_RSTn, kFC19_RST_SHIFT_RSTn, \
252 kFC20_RST_SHIFT_RSTn \
253 } /* Reset bits for FLEXCOMM peripheral */
254 #define FLEXIO_RSTS \
255 { \
256 kFLEXIO0_RST_SHIFT_RSTn \
257 } /* Resets bits for FLEXIO peripheral */
258 #define XSPI_RSTS \
259 { \
260 kXSPI0_RST_SHIFT_RSTn, kXSPI1_RST_SHIFT_RSTn, kXSPI2_RST_SHIFT_RSTn \
261 } /* Resets bits for FLEXSPI peripheral */
262 #define GPIO_RSTS \
263 { \
264 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
265 kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn, kGPIO6_RST_SHIFT_RSTn, kGPIO7_RST_SHIFT_RSTn, \
266 kGPIO8_RST_SHIFT_RSTn, kGPIO9_RST_SHIFT_RSTn, kGPIO10_RST_SHIFT_RSTn, kGPIO0_RST_SHIFT_RSTn, \
267 kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, kGPIO4_RST_SHIFT_RSTn, \
268 kGPIO5_RST_SHIFT_RSTn, kGPIO6_RST_SHIFT_RSTn, kGPIO7_RST_SHIFT_RSTn, kGPIO8_RST_SHIFT_RSTn, \
269 kGPIO9_RST_SHIFT_RSTn, kGPIO10_RST_SHIFT_RSTn \
270 } /* Reset bits for GPIO peripheral */
271 #define I3C_RSTS \
272 { \
273 kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn, kI3C2_RST_SHIFT_RSTn, kI3C3_RST_SHIFT_RSTn \
274 } /* Reset bits for I3C peripheral */
275
276 #if defined(FSL_RESET_DRIVER_SENSE)
277 #define INPUTMUX_RSTS \
278 { \
279 kINPUTMUX1_RST_SHIFT_RSTn \
280 } /* Reset bits for INPUTMUX peripheral */
281 #define DMA_RSTS_N \
282 { \
283 kDMA2_RST_SHIFT_RSTn, kDMA3_RST_SHIFT_RSTn \
284 } /* Reset bits for DMA peripheral */
285 #endif
286 #if defined(FSL_RESET_DRIVER_COMPUTE)
287 #define INPUTMUX_RSTS \
288 { \
289 kINPUTMUX0_RST_SHIFT_RSTn \
290 } /* Reset bits for INPUTMUX peripheral */
291 #define DMA_RSTS_N \
292 { \
293 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
294 } /* Reset bits for DMA peripheral */
295 #endif
296 #define MRT_RSTS \
297 { \
298 kMRT0_RST_SHIFT_RSTn, kMRT1_RST_SHIFT_RSTn \
299 } /* Reset bits for MRT peripheral */
300 #if (defined(MIMXRT798S_cm33_core0_SERIES) || defined(MIMXRT758S_cm33_core0_SERIES) || \
301 defined(MIMXRT735S_cm33_core0_SERIES))
302 #define MU_RSTS \
303 { \
304 kMU0_RST_SHIFT_RSTn, kMU1_RST_SHIFT_RSTn, kMU4_RST_SHIFT_RSTn \
305 } /* Reset bits for MU peripheral */
306 #elif (defined(MIMXRT798S_cm33_core1_SERIES) || defined(MIMXRT758S_cm33_core1_SERIES) || \
307 defined(MIMXRT735S_cm33_core1_SERIES))
308 #define MU_RSTS \
309 { \
310 kMU1_RST_SHIFT_RSTn, kMU2_RST_SHIFT_RSTn, kMU3_RST_SHIFT_RSTn \
311 } /* Reset bits for MU peripheral */
312 #elif defined(MIMXRT798S_hifi4_SERIES)
313 #define MU_RSTS \
314 { \
315 kMU2_RST_SHIFT_RSTn, kMU4_RST_SHIFT_RSTn \
316 } /* Reset bits for MU peripheral */
317 #elif defined(MIMXRT798S_hifi1_SERIES)
318 #define MU_RSTS \
319 { \
320 kMU0_RST_SHIFT_RSTn, kMU3_RST_SHIFT_RSTn \
321 } /* Reset bits for MU peripheral */
322 #elif defined(MIMXRT798S_ezhv_SERIES)
323 #else
324 #error "Unsupported core!"
325 #endif
326
327 #define PINT_RSTS \
328 { \
329 kPINT_RST_SHIFT_RSTn \
330 } /* Reset bits for PINT peripheral */
331
332 #define PNGDEC_RSTS \
333 { \
334 kPNGDEC_RST_SHIFT_RSTn \
335 } /* Reset bits for PNGDEC peripheral */
336
337 #define JPEGDEC_RSTS \
338 { \
339 kJPEGDEC_RST_SHIFT_RSTn \
340 } /* Reset bits for JPEGDEC peripheral */
341
342 #define SCT_RSTS \
343 { \
344 kSCT0_RST_SHIFT_RSTn \
345 } /* Reset bits for SCT peripheral */
346 #define SEMA42_RSTS \
347 { \
348 kSEMA420_RST_SHIFT_RSTn, (RSTCTL_RSTn_t)0U, (RSTCTL_RSTn_t)0U, kSEMA423_RST_SHIFT_RSTn, \
349 kSEMA424_RST_SHIFT_RSTn \
350 } /* Reset bits for SEMA42 peripheral */
351 #define SAI_RSTS \
352 { \
353 kSAI0_RST_SHIFT_RSTn, kSAI1_RST_SHIFT_RSTn, kSAI2_RST_SHIFT_RSTn, kSAI3_RST_SHIFT_RSTn \
354 } /* Reset bits for SAI peripheral */
355 #define USDHC_RSTS \
356 { \
357 kUSDHC0_RST_SHIFT_RSTn, kUSDHC1_RST_SHIFT_RSTn \
358 } /* Reset bits for USDHC peripheral */
359 #define UTICK_RSTS \
360 { \
361 kUTICK0_RST_SHIFT_RSTn, kUTICK1_RST_SHIFT_RSTn \
362 } /* Reset bits for UTICK peripheral */
363
364 /*!
365 * @brief IP reset handle
366 */
367 typedef RSTCTL_RSTn_t reset_ip_name_t;
368
369 /*******************************************************************************
370 * API
371 ******************************************************************************/
372 #if defined(__cplusplus)
373 extern "C" {
374 #endif
375
376 /*!
377 * @brief Assert reset to peripheral.
378 *
379 * Asserts reset signal to specified peripheral module.
380 *
381 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
382 * and reset bit position in the reset register.
383 */
384 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
385
386 /*!
387 * @brief Clear reset to peripheral.
388 *
389 * Clears reset signal to specified peripheral module, allows it to operate.
390 *
391 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
392 * and reset bit position in the reset register.
393 */
394 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
395
396 /*!
397 * @brief Reset peripheral module.
398 *
399 * Reset peripheral module.
400 *
401 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
402 * and reset bit position in the reset register.
403 */
404 void RESET_PeripheralReset(reset_ip_name_t peripheral);
405
406 /*!
407 * @brief Release peripheral module.
408 *
409 * Release peripheral module.
410 *
411 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
412 * and reset bit position in the reset register.
413 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)414 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
415 {
416 RESET_ClearPeripheralReset(peripheral);
417 }
418
419 /*!
420 * @brief Gets the reset source status which caused a previous reset.
421 *
422 * This function gets the status of the latest reset event. Use source masks
423 * defined in the rstctl_reset_source_t to get the desired source status.
424 *
425 * @return All reset source status bit map.
426 */
RESET_GetPreviousResetSources(void)427 static inline uint32_t RESET_GetPreviousResetSources(void)
428 {
429 return RSTCTL3->SYSRSTSTAT;
430 }
431
432 /*!
433 * @brief Clears the reset source status.
434 *
435 * This function clears the system reset flags indicated by source masks.
436 *
437 * @param sourceMasks reset source status bit map
438 */
RESET_ClearResetSources(uint32_t sourceMasks)439 static inline void RESET_ClearResetSources(uint32_t sourceMasks)
440 {
441 RSTCTL3->SYSRSTSTAT = sourceMasks;
442 }
443
444 /*!
445 * @brief Gets the reset status of domains.
446 *
447 * This function gets the reset status of domains.
448 *
449 * @return All reset source status bit map.
450 */
RESET_GetDomainResetStatus(void)451 static inline uint32_t RESET_GetDomainResetStatus(void)
452 {
453 return RSTCTL3->DOMRSTSTAT;
454 }
455
456 #if defined(__cplusplus)
457 }
458 #endif
459
460 /*! @} */
461
462 #endif /* FSL_RESET_H_ */
463
