1 /*
2  * Copyright 2023-2024 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 #ifndef FSL_POWER_H_
8 #define FSL_POWER_H_
9 
10 #include "fsl_common.h"
11 
12 /*!
13  * @addtogroup power
14  * @{
15  */
16 
17 /*!*****************************************************************************
18  * Definitions
19  ******************************************************************************/
20 
21 /*! @name Driver version */
22 /*@{*/
23 /*! @brief power driver version 2.3.0. */
24 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
25 /*@}*/
26 
27 /* Define the default PMIC modes for power modes. */
28 #ifndef POWER_DEFAULT_PMICMODE_DS
29 #define POWER_DEFAULT_PMICMODE_DS 1U
30 #endif
31 #ifndef POWER_DEFAULT_PMICMODE_DSR
32 #define POWER_DEFAULT_PMICMODE_DSR 1U
33 #endif
34 #ifndef POWER_DEFAULT_PMICMODE_DPD
35 #define POWER_DEFAULT_PMICMODE_DPD 2U
36 #endif
37 #ifndef POWER_DEFAULT_PMICMODE_FDPD
38 #define POWER_DEFAULT_PMICMODE_FDPD 3U
39 #endif
40 
41 #define MAKE_PD_BITS(reg, slot)   (((reg) << 8) | (slot))
42 #define GET_PD_REG_FROM_BITS(bit) (((uint32_t)(bit) >> 8U) & 0xFFU)
43 
44 #define SLEEPCON_RCFG 0x0U
45 #define PMC_PDRCFG0   0x1U
46 #define PMC_PDRCFG1   0x2U
47 #define PMC_PDRCFG2   0x3U
48 #define PMC_PDRCFG3   0x4U
49 #define PMC_PDRCFG4   0x5U
50 #define PMC_PDRCFG5   0x6U
51 
52 /*! @brief Power down control bits defined in SLEEPCON and PMC. */
53 typedef enum pd_bits
54 {
55 #if defined(PMC0)
56     kPDRUNCFG_SHUT_COMPT_MAINCLK = MAKE_PD_BITS(SLEEPCON_RCFG, 0U), /*!< VDD2_COMP Domain Main Clock Shut Off. */
57 #endif
58     kPDRUNCFG_SHUT_SENSEP_MAINCLK =
59         MAKE_PD_BITS(SLEEPCON_RCFG, 1U), /*!< The Private Part in VDD1_SENSE Main Clock Shut Off. */
60     kPDRUNCFG_SHUT_SENSES_MAINCLK =
61         MAKE_PD_BITS(SLEEPCON_RCFG, 2U), /*!< The Shared Part in VDD1_SENSE Main Clock Shut Off. */
62     kPDRUNCFG_SHUT_RAM0_CLK      = MAKE_PD_BITS(SLEEPCON_RCFG, 3U), /*!< Main Clock of RAM Arbiter 0 Shut Off. */
63     kPDRUNCFG_SHUT_RAM1_CLK      = MAKE_PD_BITS(SLEEPCON_RCFG, 4U), /*!< Main Clock of RAM Arbiter 1 shut off. */
64     kPDRUNCFG_SHUT_COMNN_MAINCLK = MAKE_PD_BITS(SLEEPCON_RCFG, 5U), /*!< VDDN_COM Domain Main Clock Shut Off. */
65     kPDRUNCFG_SHUT_MEDIA_MAINCLK =
66         MAKE_PD_BITS(SLEEPCON_RCFG, 6U), /*!< VDD2_MEDIA and VDDN_MEDIA Domains Main Clock of Shut Off. */
67     kPDRUNCFG_PD_SYSXTAL = MAKE_PD_BITS(SLEEPCON_RCFG, 7U),    /*!< Xtal Oscillator Power Down. */
68 #if defined(PMC0)
69     kPDRUNCFG_PD_FRO0 = MAKE_PD_BITS(SLEEPCON_RCFG, 8U),       /*!< FRO0 Power Down. */
70     kPDRUNCFG_PD_FRO1 = MAKE_PD_BITS(SLEEPCON_RCFG, 9U),       /*!< FRO1 Power Down. */
71 #endif
72     kPDRUNCFG_PD_FRO2      = MAKE_PD_BITS(SLEEPCON_RCFG, 10U), /*!< FRO2 Power Down. */
73     kPDRUNCFG_PD_LPOSC     = MAKE_PD_BITS(SLEEPCON_RCFG, 11U), /*!< LPOSC Power Down. */
74     kPDRUNCFG_PD_PLLANA    = MAKE_PD_BITS(SLEEPCON_RCFG, 12U), /*!< Main PLL Analog Function Power Down. */
75     kPDRUNCFG_PD_PLLLDO    = MAKE_PD_BITS(SLEEPCON_RCFG, 13U), /*!< Main PLL Internal Regulator Power Down. */
76     kPDRUNCFG_PD_AUDPLLANA = MAKE_PD_BITS(SLEEPCON_RCFG, 14U), /*!< Audio PLL Analog Function Power Down. */
77     kPDRUNCFG_PD_AUDPLLLDO = MAKE_PD_BITS(SLEEPCON_RCFG, 15U), /*!< Audio PLL Internal Regulator Power Down. */
78     kPDRUNCFG_PD_ADC0      = MAKE_PD_BITS(SLEEPCON_RCFG, 16U), /*!< ADC0 Power Down, 1 - Applies gating. */
79 #if defined(PMC0)
80     kPDRUNCFG_GATE_FRO0 = MAKE_PD_BITS(SLEEPCON_RCFG, 29U),    /*!< FRO0 Gating, 1 - Applies gating. */
81 #endif
82     kPDRUNCFG_GATE_FRO2 = MAKE_PD_BITS(SLEEPCON_RCFG, 31U),    /*!< FRO2 Gating, 1 - Applies gating. */
83     kPDRUNCFG_DSR_VDD2N_MEDIA =
84         MAKE_PD_BITS(PMC_PDRCFG0, 6U), /*!< Power Switch and DSR Enable for the VDD2_MEDIA and VDDN_MEDIA domains. */
85     kPDRUNCFG_DSR_VDDN_COM = MAKE_PD_BITS(PMC_PDRCFG0, 8U), /*!< Power Switch and DSR Enable for the VDDN_COM domain. */
86     kPDRUNCFG_PD_VDD2_DSP  = MAKE_PD_BITS(PMC_PDRCFG0, 9U), /*!< Power switch for the HiFi4 DSP. */
87     kPDRUNCFG_PD_VDD2_MIPI = MAKE_PD_BITS(PMC_PDRCFG0, 10U),        /*!< Power Switch for the MIPI PHY. */
88     kPDRUNCFG_LP_DCDC      = MAKE_PD_BITS(PMC_PDRCFG0, 12U),        /*!< DCDC Low-Power Mode. */
89     kPDRUNCFG_PD_RBB_VDD1  = MAKE_PD_BITS(PMC_PDRCFG0, 22U),        /*!< Power Down RBB in VDD1. */
90     kPDRUNCFG_PD_AFBB_VDD1 = MAKE_PD_BITS(PMC_PDRCFG0, 23U),        /*!< Power Down AFBB in VDD1 Domain. */
91     kPDRUNCFG_PD_RBB_VDD2  = MAKE_PD_BITS(PMC_PDRCFG0, 24U),        /*!< Power Down RBB in VDD2 Domain.*/
92     kPDRUNCFG_PD_AFBB_VDD2 = MAKE_PD_BITS(PMC_PDRCFG0, 25U),        /*!< Power Down AFBB in VDD2 Domain.*/
93     kPDRUNCFG_PD_RBB_VDDN  = MAKE_PD_BITS(PMC_PDRCFG0, 26U),        /*!< Power Down RBB in VDDN Domain.*/
94     kPDRUNCFG_PD_AFBB_VDDN = MAKE_PD_BITS(PMC_PDRCFG0, 27U),        /*!< Power Down RBB in VDDN Domain.*/
95     kPDRUNCFG_PD_SRAM_RBB_VDD1    = MAKE_PD_BITS(PMC_PDRCFG0, 28U), /*!< Power Down SRAM RBB in VDD1 Domain. */
96     kPDRUNCFG_PD_SRAM_RBB_VDD2    = MAKE_PD_BITS(PMC_PDRCFG0, 29U), /*!< Power Down SRAM RBB in VDD2 Domain. */
97     kPDRUNCFG_PD_SRAM_AFBB_VDD2   = MAKE_PD_BITS(PMC_PDRCFG0, 31U), /*!< Power Down SRAM AFBB in VDD2 Domain.*/
98     kPDRUNCFG_PD_PMC_TEMPSNS      = MAKE_PD_BITS(PMC_PDRCFG1, 0U),  /*!< Power Down PMC Temperature Sensor.*/
99     kPDRUNCFG_LP_PMCREF           = MAKE_PD_BITS(PMC_PDRCFG1, 1U),  /*!< PMC References in Low-Power Mode.*/
100     kPDRUNCFG_PD_HVD1V8           = MAKE_PD_BITS(PMC_PDRCFG1, 2U),  /*!< HVD Power Down.*/
101     kPDRUNCFG_LP_POR_VDD1         = MAKE_PD_BITS(PMC_PDRCFG1, 3U),  /*!< POR Low-Power Mode in VDD1 Domain.*/
102     kPDRUNCFG_LP_LVD_VDD1         = MAKE_PD_BITS(PMC_PDRCFG1, 4U),  /*!< LVD Low-Power Mode in VDD1 Domain.*/
103     kPDRUNCFG_PD_HVD_VDD1         = MAKE_PD_BITS(PMC_PDRCFG1, 5U),  /*!< Power Down HVD in VDD1 Domain.*/
104     kPDRUNCFG_PD_AGDET_VDD1       = MAKE_PD_BITS(PMC_PDRCFG1, 6U),  /*!< Power Down AGDET in VDD1 Domain.*/
105     kPDRUNCFG_LP_POR_VDD2         = MAKE_PD_BITS(PMC_PDRCFG1, 7U),  /*!< POR Low-Power Mode in VDD2 Domain.*/
106     kPDRUNCFG_LP_LVD_VDD2         = MAKE_PD_BITS(PMC_PDRCFG1, 8U),  /*!< LVD Low-Power Mode in VDD2 Domain.*/
107     kPDRUNCFG_PD_HVD_VDD2         = MAKE_PD_BITS(PMC_PDRCFG1, 9U),  /*!< Power Down HVD in VDD2 Domain.*/
108     kPDRUNCFG_PD_AGDET_VDD2       = MAKE_PD_BITS(PMC_PDRCFG1, 10U), /*!< Power Down AGDET in VDD2 Domain.*/
109     kPDRUNCFG_LP_POR_VDDN         = MAKE_PD_BITS(PMC_PDRCFG1, 11U), /*!< POR Low-Power Mode in VDDN Domain.*/
110     kPDRUNCFG_LP_LVD_VDDN         = MAKE_PD_BITS(PMC_PDRCFG1, 12U), /*!< LVD Low-Power Mode in VDDN Domain.*/
111     kPDRUNCFG_PD_HVD_VDDN         = MAKE_PD_BITS(PMC_PDRCFG1, 13U), /*!< Power Down HVD in VDDN Domain.*/
112     kPDRUNCFG_PD_OTP              = MAKE_PD_BITS(PMC_PDRCFG1, 15U), /*!< Power Down OTP.*/
113     kPDRUNCFG_PD_ROM              = MAKE_PD_BITS(PMC_PDRCFG1, 16U), /*!< Power Down ROM.*/
114     kPDRUNCFG_APD_SRAM1           = MAKE_PD_BITS(PMC_PDRCFG2, 1U),  /*!< RAM Partition 1 Array Power Down. */
115     kPDRUNCFG_APD_SRAM2           = MAKE_PD_BITS(PMC_PDRCFG2, 2U),  /*!< RAM Partition 2 Array Power Down. */
116     kPDRUNCFG_APD_SRAM3           = MAKE_PD_BITS(PMC_PDRCFG2, 3U),  /*!< RAM Partition 3 Array Power Down. */
117     kPDRUNCFG_APD_SRAM4           = MAKE_PD_BITS(PMC_PDRCFG2, 4U),  /*!< RAM Partition 4 Array Power Down. */
118     kPDRUNCFG_APD_SRAM5           = MAKE_PD_BITS(PMC_PDRCFG2, 5U),  /*!< RAM Partition 5 Array Power Down. */
119     kPDRUNCFG_APD_SRAM6           = MAKE_PD_BITS(PMC_PDRCFG2, 6U),  /*!< RAM Partition 6 Array Power Down. */
120     kPDRUNCFG_APD_SRAM7           = MAKE_PD_BITS(PMC_PDRCFG2, 7U),  /*!< RAM Partition 7 Array Power Down. */
121     kPDRUNCFG_APD_SRAM8           = MAKE_PD_BITS(PMC_PDRCFG2, 8U),  /*!< RAM Partition 8 Array Power Down. */
122     kPDRUNCFG_APD_SRAM9           = MAKE_PD_BITS(PMC_PDRCFG2, 9U),  /*!< RAM Partition 9 Array Power Down. */
123     kPDRUNCFG_APD_SRAM10          = MAKE_PD_BITS(PMC_PDRCFG2, 10U), /*!< RAM Partition 10 Array Power Down. */
124     kPDRUNCFG_APD_SRAM11          = MAKE_PD_BITS(PMC_PDRCFG2, 11U), /*!< RAM Partition 11 Array Power Down. */
125     kPDRUNCFG_APD_SRAM12          = MAKE_PD_BITS(PMC_PDRCFG2, 12U), /*!< RAM Partition 12 Array Power Down. */
126     kPDRUNCFG_APD_SRAM13          = MAKE_PD_BITS(PMC_PDRCFG2, 13U), /*!< RAM Partition 13 Array Power Down. */
127     kPDRUNCFG_APD_SRAM14          = MAKE_PD_BITS(PMC_PDRCFG2, 14U), /*!< RAM Partition 14 Array Power Down. */
128     kPDRUNCFG_APD_SRAM15          = MAKE_PD_BITS(PMC_PDRCFG2, 15U), /*!< RAM Partition 15 Array Power Down. */
129     kPDRUNCFG_APD_SRAM16          = MAKE_PD_BITS(PMC_PDRCFG2, 16U), /*!< RAM Partition 16 Array Power Down. */
130     kPDRUNCFG_APD_SRAM17          = MAKE_PD_BITS(PMC_PDRCFG2, 17U), /*!< RAM Partition 17 Array Power Down. */
131     kPDRUNCFG_APD_SRAM18          = MAKE_PD_BITS(PMC_PDRCFG2, 18U), /*!< RAM Partition 18 Array Power Down. */
132     kPDRUNCFG_APD_SRAM19          = MAKE_PD_BITS(PMC_PDRCFG2, 19U), /*!< RAM Partition 19 Array Power Down. */
133     kPDRUNCFG_APD_SRAM20          = MAKE_PD_BITS(PMC_PDRCFG2, 20U), /*!< RAM Partition 20 Array Power Down. */
134     kPDRUNCFG_APD_SRAM21          = MAKE_PD_BITS(PMC_PDRCFG2, 21U), /*!< RAM Partition 21 Array Power Down. */
135     kPDRUNCFG_APD_SRAM22          = MAKE_PD_BITS(PMC_PDRCFG2, 22U), /*!< RAM Partition 22 Array Power Down. */
136     kPDRUNCFG_APD_SRAM23          = MAKE_PD_BITS(PMC_PDRCFG2, 23U), /*!< RAM Partition 23 Array Power Down. */
137     kPDRUNCFG_APD_SRAM24          = MAKE_PD_BITS(PMC_PDRCFG2, 24U), /*!< RAM Partition 24 Array Power Down. */
138     kPDRUNCFG_APD_SRAM25          = MAKE_PD_BITS(PMC_PDRCFG2, 25U), /*!< RAM Partition 25 Array Power Down. */
139     kPDRUNCFG_APD_SRAM26          = MAKE_PD_BITS(PMC_PDRCFG2, 26U), /*!< RAM Partition 26 Array Power Down. */
140     kPDRUNCFG_APD_SRAM27          = MAKE_PD_BITS(PMC_PDRCFG2, 27U), /*!< RAM Partition 27 Array Power Down. */
141     kPDRUNCFG_APD_SRAM28          = MAKE_PD_BITS(PMC_PDRCFG2, 28U), /*!< RAM Partition 28 Array Power Down. */
142     kPDRUNCFG_APD_SRAM29          = MAKE_PD_BITS(PMC_PDRCFG2, 29U), /*!< RAM Partition 29 Array Power Down. */
143     kPDRUNCFG_PPD_SRAM1           = MAKE_PD_BITS(PMC_PDRCFG3, 1U),  /*!< RAM Partition 1 Periphery Power Down. */
144     kPDRUNCFG_PPD_SRAM2           = MAKE_PD_BITS(PMC_PDRCFG3, 2U),  /*!< RAM Partition 2 Periphery Power Down. */
145     kPDRUNCFG_PPD_SRAM3           = MAKE_PD_BITS(PMC_PDRCFG3, 3U),  /*!< RAM Partition 3 Periphery Power Down. */
146     kPDRUNCFG_PPD_SRAM4           = MAKE_PD_BITS(PMC_PDRCFG3, 4U),  /*!< RAM Partition 4 Periphery Power Down. */
147     kPDRUNCFG_PPD_SRAM5           = MAKE_PD_BITS(PMC_PDRCFG3, 5U),  /*!< RAM Partition 5 Periphery Power Down. */
148     kPDRUNCFG_PPD_SRAM6           = MAKE_PD_BITS(PMC_PDRCFG3, 6U),  /*!< RAM Partition 6 Periphery Power Down. */
149     kPDRUNCFG_PPD_SRAM7           = MAKE_PD_BITS(PMC_PDRCFG3, 7U),  /*!< RAM Partition 7 Periphery Power Down. */
150     kPDRUNCFG_PPD_SRAM8           = MAKE_PD_BITS(PMC_PDRCFG3, 8U),  /*!< RAM Partition 8 Periphery Power Down. */
151     kPDRUNCFG_PPD_SRAM9           = MAKE_PD_BITS(PMC_PDRCFG3, 9U),  /*!< RAM Partition 9 Periphery Power Down. */
152     kPDRUNCFG_PPD_SRAM10          = MAKE_PD_BITS(PMC_PDRCFG3, 10U), /*!< RAM Partition 10 Periphery Power Down. */
153     kPDRUNCFG_PPD_SRAM11          = MAKE_PD_BITS(PMC_PDRCFG3, 11U), /*!< RAM Partition 11 Periphery Power Down. */
154     kPDRUNCFG_PPD_SRAM12          = MAKE_PD_BITS(PMC_PDRCFG3, 12U), /*!< RAM Partition 12 Periphery Power Down. */
155     kPDRUNCFG_PPD_SRAM13          = MAKE_PD_BITS(PMC_PDRCFG3, 13U), /*!< RAM Partition 13 Periphery Power Down. */
156     kPDRUNCFG_PPD_SRAM14          = MAKE_PD_BITS(PMC_PDRCFG3, 14U), /*!< RAM Partition 14 Periphery Power Down. */
157     kPDRUNCFG_PPD_SRAM15          = MAKE_PD_BITS(PMC_PDRCFG3, 15U), /*!< RAM Partition 15 Periphery Power Down. */
158     kPDRUNCFG_PPD_SRAM16          = MAKE_PD_BITS(PMC_PDRCFG3, 16U), /*!< RAM Partition 16 Periphery Power Down. */
159     kPDRUNCFG_PPD_SRAM17          = MAKE_PD_BITS(PMC_PDRCFG3, 17U), /*!< RAM Partition 17 Periphery Power Down. */
160     kPDRUNCFG_PPD_SRAM18          = MAKE_PD_BITS(PMC_PDRCFG3, 18U), /*!< RAM Partition 18 Periphery Power Down. */
161     kPDRUNCFG_PPD_SRAM19          = MAKE_PD_BITS(PMC_PDRCFG3, 19U), /*!< RAM Partition 19 Periphery Power Down. */
162     kPDRUNCFG_PPD_SRAM20          = MAKE_PD_BITS(PMC_PDRCFG3, 20U), /*!< RAM Partition 20 Periphery Power Down. */
163     kPDRUNCFG_PPD_SRAM21          = MAKE_PD_BITS(PMC_PDRCFG3, 21U), /*!< RAM Partition 21 Periphery Power Down. */
164     kPDRUNCFG_PPD_SRAM22          = MAKE_PD_BITS(PMC_PDRCFG3, 22U), /*!< RAM Partition 22 Periphery Power Down. */
165     kPDRUNCFG_PPD_SRAM23          = MAKE_PD_BITS(PMC_PDRCFG3, 23U), /*!< RAM Partition 23 Periphery Power Down. */
166     kPDRUNCFG_PPD_SRAM24          = MAKE_PD_BITS(PMC_PDRCFG3, 24U), /*!< RAM Partition 24 Periphery Power Down. */
167     kPDRUNCFG_PPD_SRAM25          = MAKE_PD_BITS(PMC_PDRCFG3, 25U), /*!< RAM Partition 25 Periphery Power Down. */
168     kPDRUNCFG_PPD_SRAM26          = MAKE_PD_BITS(PMC_PDRCFG3, 26U), /*!< RAM Partition 26 Periphery Power Down. */
169     kPDRUNCFG_PPD_SRAM27          = MAKE_PD_BITS(PMC_PDRCFG3, 27U), /*!< RAM Partition 27 Periphery Power Down. */
170     kPDRUNCFG_PPD_SRAM28          = MAKE_PD_BITS(PMC_PDRCFG3, 28U), /*!< RAM Partition 28 Periphery Power Down. */
171     kPDRUNCFG_PPD_SRAM29          = MAKE_PD_BITS(PMC_PDRCFG3, 29U), /*!< RAM Partition 29 Periphery Power Down. */
172     kPDRUNCFG_APD_SDHC0_SRAM      = MAKE_PD_BITS(PMC_PDRCFG4, 0U),  /*!< uSDHC0 SRAM array Power Down. */
173     kPDRUNCFG_APD_SDHC1_SRAM      = MAKE_PD_BITS(PMC_PDRCFG4, 1U),  /*!< uSDHC1 SRAM array Power Down. */
174     kPDRUNCFG_APD_USB0_SRAM       = MAKE_PD_BITS(PMC_PDRCFG4, 2U),  /*!< USB0 SRAM array Power Down. */
175     kPDRUNCFG_APD_USB1_SRAM       = MAKE_PD_BITS(PMC_PDRCFG4, 3U),  /*!< USB1 SRAM array Power Down. */
176     kPDRUNCFG_APD_JPEGDEC         = MAKE_PD_BITS(PMC_PDRCFG4, 4U),  /*!< Powers down JPEGDEC RAMs array. */
177     kPDRUNCFG_APD_PNGDEC          = MAKE_PD_BITS(PMC_PDRCFG4, 5U),  /*!< Powers down PNGDEC RAMs array. */
178     kPDRUNCFG_APD_MIPIDSI         = MAKE_PD_BITS(PMC_PDRCFG4, 6U),  /*!< Powers down MIPI PHY RAMs array. */
179     kPDRUNCFG_APD_GPU             = MAKE_PD_BITS(PMC_PDRCFG4, 7U),  /*!< Powers down VGPU RAMs array. */
180     kPDRUNCFG_APD_DMA2_3          = MAKE_PD_BITS(PMC_PDRCFG4, 8U),  /*!< Powers down DMA2 and DMA3 RAMs array. */
181     kPDRUNCFG_APD_DMA0_1_PKC_ETF  = MAKE_PD_BITS(PMC_PDRCFG4, 9U),  /*!< Powers down DMA0-1, PKC, and ETF RAMs array. */
182     kPDRUNCFG_APD_CPU0_CODE_CACHE = MAKE_PD_BITS(PMC_PDRCFG4, 10U), /*!< Powers down CPU0 code cache RAMs array. */
183     kPDRUNCFG_APD_CPU0_SYSTEM_CACHE = MAKE_PD_BITS(PMC_PDRCFG4, 11U), /*!< Powers down CPU0 system cache RAMs array. */
184     kPDRUNCFG_APD_DSP_ICACHE = MAKE_PD_BITS(PMC_PDRCFG4, 12U), /*!< Powers down HiFi4 instruction cache RAMs array. */
185     kPDRUNCFG_APD_DSP_DCACHE = MAKE_PD_BITS(PMC_PDRCFG4, 13U), /*!< Powers down HiFi4 data cache RAMs array. */
186     kPDRUNCFG_APD_DSP_ITCM   = MAKE_PD_BITS(PMC_PDRCFG4, 14U), /*!< Powers down HiFi4 instruction TCM RAMs array. */
187     kPDRUNCFG_APD_DSP_DTCM   = MAKE_PD_BITS(PMC_PDRCFG4, 15U), /*!< Powers down HiFi4 data TCM RAMs array. */
188     kPDRUNCFG_APD_EZHV_TCM   = MAKE_PD_BITS(PMC_PDRCFG4, 16U), /*!< Powers down EZH-V TCM RAMs array. */
189     kPDRUNCFG_APD_NPU        = MAKE_PD_BITS(PMC_PDRCFG4, 17U), /*!< Powers down NPU RAMs array. */
190     kPDRUNCFG_APD_XSPI0      = MAKE_PD_BITS(PMC_PDRCFG4, 18U), /*!< Powers down XSPI0, MMU0, and cache RAMs array. */
191     kPDRUNCFG_APD_XSPI1      = MAKE_PD_BITS(PMC_PDRCFG4, 19U), /*!< Powers down XSPI1, MMU1, and cache RAMs array. */
192     kPDRUNCFG_APD_XSPI2      = MAKE_PD_BITS(PMC_PDRCFG4, 20U), /*!< Powers down XSPI2 and MMU2 RAMs array. */
193     kPDRUNCFG_APD_LCDIF      = MAKE_PD_BITS(PMC_PDRCFG4, 21U), /*!< Powers down LCDIF controller RAMs array. */
194     kPDRUNCFG_APD_OCOTP      = MAKE_PD_BITS(PMC_PDRCFG4, 22U), /*!< Powers down OCOTP shadow RAMs array. */
195     kPDRUNCFG_PPD_SDHC0_SRAM = MAKE_PD_BITS(PMC_PDRCFG5, 0U),  /*!< Powers down uSDHC0 RAMs periphery. */
196     kPDRUNCFG_PPD_SDHC1_SRAM = MAKE_PD_BITS(PMC_PDRCFG5, 1U),  /*!< Powers down uSDHC1 RAMs periphery. */
197     kPDRUNCFG_PPD_USB0_SRAM  = MAKE_PD_BITS(PMC_PDRCFG5, 2U),  /*!< Powers down USB0 RAMs periphery. */
198     kPDRUNCFG_PPD_USB1_SRAM  = MAKE_PD_BITS(PMC_PDRCFG5, 3U),  /*!< Powers down USB1 RAMs periphery. */
199     kPDRUNCFG_PPD_JPEGDEC    = MAKE_PD_BITS(PMC_PDRCFG5, 4U),  /*!< Powers down JPEGDEC RAMs periphery. */
200     kPDRUNCFG_PPD_PNGDEC     = MAKE_PD_BITS(PMC_PDRCFG5, 5U),  /*!< Powers down PNGDEC RAMs periphery. */
201     kPDRUNCFG_PPD_MIPIDSI    = MAKE_PD_BITS(PMC_PDRCFG5, 6U),  /*!< Powers down MIPI PHY RAMs periphery. */
202     kPDRUNCFG_PPD_GPU        = MAKE_PD_BITS(PMC_PDRCFG5, 7U),  /*!< Powers down VGPU RAMs periphery. */
203     kPDRUNCFG_PPD_DMA2_3     = MAKE_PD_BITS(PMC_PDRCFG5, 8U),  /*!< Powers down DMA2 and DMA3 RAMs periphery. */
204     kPDRUNCFG_PPD_DMA0_1_PKC_ETF =
205         MAKE_PD_BITS(PMC_PDRCFG5, 9U),                         /*!< Powers down DMA0-1, PKC, and ETF RAMs periphery. */
206     kPDRUNCFG_PPD_CPU0_CODE_CACHE = MAKE_PD_BITS(PMC_PDRCFG5, 10U), /*!< Powers down CPU0 code cache RAMs periphery. */
207     kPDRUNCFG_PPD_CPU0_SYSTEM_CACHE =
208         MAKE_PD_BITS(PMC_PDRCFG5, 11U), /*!< Powers down CPU0 system cache RAMs periphery. */
209     kPDRUNCFG_PPD_DSP_ICACHE =
210         MAKE_PD_BITS(PMC_PDRCFG5, 12U), /*!< Powers down HiFi4 instruction cache RAMs periphery. */
211     kPDRUNCFG_PPD_DSP_DCACHE = MAKE_PD_BITS(PMC_PDRCFG5, 13U), /*!< Powers down HiFi4 data cache RAMs periphery. */
212     kPDRUNCFG_PPD_DSP_ITCM   = MAKE_PD_BITS(PMC_PDRCFG5, 14U), /*!< Powers down HiFi4 instruction TCM RAMs periphery. */
213     kPDRUNCFG_PPD_DSP_DTCM   = MAKE_PD_BITS(PMC_PDRCFG5, 15U), /*!< Powers down HiFi4 data TCM RAMs periphery. */
214     kPDRUNCFG_PPD_EZHV_TCM   = MAKE_PD_BITS(PMC_PDRCFG5, 16U), /*!< Powers down EZH-V TCM RAMs periphery. */
215     kPDRUNCFG_PPD_NPU        = MAKE_PD_BITS(PMC_PDRCFG5, 17U), /*!< Powers down NPU RAMs periphery. */
216     kPDRUNCFG_PPD_XSPI0 = MAKE_PD_BITS(PMC_PDRCFG5, 18U), /*!< Powers down XSPI0, MMU0, and cache RAMs periphery. */
217     kPDRUNCFG_PPD_XSPI1 = MAKE_PD_BITS(PMC_PDRCFG5, 19U), /*!< Powers down XSPI1, MMU1, and cache RAMs periphery. */
218     kPDRUNCFG_PPD_XSPI2 = MAKE_PD_BITS(PMC_PDRCFG5, 20U), /*!< Powers down XSPI2 and MMU2 RAMs periphery. */
219     kPDRUNCFG_PPD_LCDIF = MAKE_PD_BITS(PMC_PDRCFG5, 21U), /*!< Powers down LCDIF controller RAMs periphery. */
220     kPDRUNCFG_PPD_OCOTP = MAKE_PD_BITS(PMC_PDRCFG5, 22U), /*!< Powers down OCOTP shadow RAMs periphery. */
221     /*
222     This enum member has no practical meaning,it is used to avoid MISRA issue,
223     user should not trying to use it.
224     */
225     kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
226 } pd_bit_t;
227 
228 #define SHA_MED_CCTRL0_OFFSET 0U
229 #define SHA_MED_TCTRL0_OFFSET 1U
230 #define SHA_SEN_TCTRL0_OFFSET 3U
231 #define PRIVATE_CCTRL0_OFFSET 4U
232 #define PRIVATE_TCTRL0_OFFSET 5U
233 #define PRIVATE_TCTRL1_OFFSET 6U
234 #define PRIVATE_TCTRL2_OFFSET 7U
235 
236 #define SHA_MED_CSTAT0_OFFSET    0U /*0x1D0 */
237 #define SHA_MEDSEN_TSTAT0_OFFSET 1U /* 0x1D4 */
238 #define PRIVATE_CSTAT0_OFFSET    4U /* 0x1E0 */
239 #define PRIVATE_TSTAT0_OFFSET    5U /* 0x1E4 */
240 #define PRIVATE_TSTAT1_OFFSET    6U /* 0x1E8 */
241 
242 #define POWER_LP_REQ_CTRL_REG_OFFSET  (5U)
243 #define POWER_LP_REQ_STATE_REG_OFFSET (13U)
244 #define POWER_LP_REQ_STATE_BIT_OFFSET (8U)
245 #define POWER_MAKE_LP_BITS(ctrl_reg, ctrl_bit, state_reg, state_bit)                                              \
246     (((ctrl_reg) << POWER_LP_REQ_CTRL_REG_OFFSET) | (ctrl_bit) | ((state_bit) << POWER_LP_REQ_STATE_BIT_OFFSET) | \
247      ((state_reg) << POWER_LP_REQ_STATE_REG_OFFSET))
248 #define GET_LP_CTRL_REG_FROM_BITS(bit)  (((uint32_t)(bit) >> POWER_LP_REQ_CTRL_REG_OFFSET) & 0x7U)
249 #define GET_LP_CTRL_BIT_FROM_BITS(bit)  (((uint32_t)(bit)) & 0x1FU)
250 #define GET_LP_STATE_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_STATE_REG_OFFSET) & 0x7U)
251 #define GET_LP_STATE_BIT_FROM_BITS(bit) ((((uint32_t)(bit)) >> POWER_LP_REQ_STATE_BIT_OFFSET) & 0x1FU)
252 
253 /*! @brief low power control bits for modules. Bits used for modules to requesting low-power. */
254 typedef enum lp_bits
255 {
256     kPower_VGPU_LPREQ =
257         POWER_MAKE_LP_BITS(SHA_MED_CCTRL0_OFFSET, 0U, SHA_MED_CSTAT0_OFFSET, 0U), /*!< VGPU low power request. */
258     kPower_EZHV_STOP =
259         POWER_MAKE_LP_BITS(SHA_MED_CCTRL0_OFFSET, 1U, SHA_MED_CSTAT0_OFFSET, 2U), /*!< EZHV stop request. */
260     kPower_EZHV_HALT =
261         POWER_MAKE_LP_BITS(SHA_MED_CCTRL0_OFFSET, 2U, SHA_MED_CSTAT0_OFFSET, 3U), /*!< EZHV halt request. */
262     kPower_EZHV_EXIT_WAIT =
263         POWER_MAKE_LP_BITS(SHA_MED_CCTRL0_OFFSET, 3U, SHA_MED_CSTAT0_OFFSET, 4U), /*!< EZHV exit wait request. */
264 
265     kPower_XSPI2_STOP =
266         POWER_MAKE_LP_BITS(SHA_MED_TCTRL0_OFFSET, 0U, SHA_MEDSEN_TSTAT0_OFFSET, 0U), /*!< XSPI2 stop request. */
267     kPower_LPSPI14_B_LPREQ = POWER_MAKE_LP_BITS(
268         SHA_MED_TCTRL0_OFFSET, 3U, SHA_MEDSEN_TSTAT0_OFFSET, 1U),  /*!< LPSPI14 bus low power request. */
269     kPower_LPSPI14_F_LPREQ = POWER_MAKE_LP_BITS(
270         SHA_MED_TCTRL0_OFFSET, 4U, SHA_MEDSEN_TSTAT0_OFFSET, 2U),  /*!< LPSPI14 function low power request.*/
271     kPower_LPSPI16_B_LPREQ = POWER_MAKE_LP_BITS(
272         SHA_MED_TCTRL0_OFFSET, 6U, SHA_MEDSEN_TSTAT0_OFFSET, 3U),  /*!< LPSPI16 bus low power request. */
273     kPower_LPSPI16_F_LPREQ = POWER_MAKE_LP_BITS(
274         SHA_MED_TCTRL0_OFFSET, 7U, SHA_MEDSEN_TSTAT0_OFFSET, 4U),  /*!< LPSPI16 function low power request. */
275     kPower_FLEXIO_B_LPREQ = POWER_MAKE_LP_BITS(
276         SHA_MED_TCTRL0_OFFSET, 9U, SHA_MEDSEN_TSTAT0_OFFSET, 5U),  /*!< FLEXIO bus low power request. */
277     kPower_FLEXIO_F_LPREQ = POWER_MAKE_LP_BITS(
278         SHA_MED_TCTRL0_OFFSET, 10U, SHA_MEDSEN_TSTAT0_OFFSET, 6U), /*!< FLEXIO function low power request. */
279     kPower_NIC0_LPREQ =
280         POWER_MAKE_LP_BITS(SHA_MED_TCTRL0_OFFSET, 11U, SHA_MEDSEN_TSTAT0_OFFSET, 7U), /*!< NIC0 low power request. */
281     kPower_NIC1_LPREQ =
282         POWER_MAKE_LP_BITS(SHA_MED_TCTRL0_OFFSET, 12U, SHA_MEDSEN_TSTAT0_OFFSET, 8U), /*!< NIC1 low power request. */
283 
284     kPower_ADC0_STOP =
285         POWER_MAKE_LP_BITS(SHA_SEN_TCTRL0_OFFSET, 0U, SHA_MEDSEN_TSTAT0_OFFSET, 16U), /*!< ADC0 stop request. */
286     kPower_ACMP0_STOP =
287         POWER_MAKE_LP_BITS(SHA_SEN_TCTRL0_OFFSET, 2U, SHA_MEDSEN_TSTAT0_OFFSET, 17U), /*!< ACMP0 stop request. */
288     kPower_MICFIL_STOP =
289         POWER_MAKE_LP_BITS(SHA_SEN_TCTRL0_OFFSET, 3U, SHA_MEDSEN_TSTAT0_OFFSET, 18U), /*!< MICFIL stop request. */
290     kPower_LPI2C15_B_LPREQ = POWER_MAKE_LP_BITS(
291         SHA_SEN_TCTRL0_OFFSET, 5U, SHA_MEDSEN_TSTAT0_OFFSET, 19U), /*!< LPI2C15 bus low power request. */
292     kPower_LPI2C15_F_LPREQ = POWER_MAKE_LP_BITS(
293         SHA_SEN_TCTRL0_OFFSET, 7U, SHA_MEDSEN_TSTAT0_OFFSET, 20U), /*!< LPI2C15 function low power request. */
294     kPower_GDET2_LPREQ =
295         POWER_MAKE_LP_BITS(SHA_SEN_TCTRL0_OFFSET, 8U, SHA_MEDSEN_TSTAT0_OFFSET, 21U), /*!< GDET2 low power request. */
296     kPower_GDET3_LPREQ =
297         POWER_MAKE_LP_BITS(SHA_SEN_TCTRL0_OFFSET, 9U, SHA_MEDSEN_TSTAT0_OFFSET, 22U), /*!< GDET3 low power request. */
298     kPower_RTC_STOP = POWER_MAKE_LP_BITS(
299         SHA_SEN_TCTRL0_OFFSET, 31U, SHA_MEDSEN_TSTAT0_OFFSET, 31U), /*!< RTC0 and RTC1 stop request. */
300 
301 #if defined(PMC0)
302     kPower_EDMA0_STOP =
303         POWER_MAKE_LP_BITS(PRIVATE_CCTRL0_OFFSET, 0U, PRIVATE_CSTAT0_OFFSET, 0U), /*!< EDMA0 stop request. */
304     kPower_EDMA1_STOP =
305         POWER_MAKE_LP_BITS(PRIVATE_CCTRL0_OFFSET, 1U, PRIVATE_CSTAT0_OFFSET, 1U), /*!< EDMA1 stop request. */
306 
307     kPower_FC0_B_LPREQ = POWER_MAKE_LP_BITS(
308         PRIVATE_TCTRL0_OFFSET, 0U, PRIVATE_TSTAT0_OFFSET, 0U),   /*!< LP_FLEXCOMM0 bus low power request. */
309     kPower_FC1_B_LPREQ = POWER_MAKE_LP_BITS(
310         PRIVATE_TCTRL0_OFFSET, 1U, PRIVATE_TSTAT0_OFFSET, 1U),   /*!< LP_FLEXCOMM1 bus low power request. */
311     kPower_FC2_B_LPREQ = POWER_MAKE_LP_BITS(
312         PRIVATE_TCTRL0_OFFSET, 2U, PRIVATE_TSTAT0_OFFSET, 2U),   /*!< LP_FLEXCOMM2 bus low power request. */
313     kPower_FC3_B_LPREQ = POWER_MAKE_LP_BITS(
314         PRIVATE_TCTRL0_OFFSET, 3U, PRIVATE_TSTAT0_OFFSET, 3U),   /*!< LP_FLEXCOMM3 bus low power request. */
315     kPower_FC4_B_LPREQ = POWER_MAKE_LP_BITS(
316         PRIVATE_TCTRL0_OFFSET, 4U, PRIVATE_TSTAT0_OFFSET, 4U),   /*!< LP_FLEXCOMM4 bus low power request. */
317     kPower_FC5_B_LPREQ = POWER_MAKE_LP_BITS(
318         PRIVATE_TCTRL0_OFFSET, 5U, PRIVATE_TSTAT0_OFFSET, 5U),   /*!< LP_FLEXCOMM5 bus low power request. */
319     kPower_FC6_B_LPREQ = POWER_MAKE_LP_BITS(
320         PRIVATE_TCTRL0_OFFSET, 6U, PRIVATE_TSTAT0_OFFSET, 6U),   /*!< LP_FLEXCOMM6 bus low power request. */
321     kPower_FC7_B_LPREQ = POWER_MAKE_LP_BITS(
322         PRIVATE_TCTRL0_OFFSET, 7U, PRIVATE_TSTAT0_OFFSET, 7U),   /*!< LP_FLEXCOMM7 bus low power request. */
323     kPower_FC8_B_LPREQ = POWER_MAKE_LP_BITS(
324         PRIVATE_TCTRL0_OFFSET, 8U, PRIVATE_TSTAT0_OFFSET, 8U),   /*!< LP_FLEXCOMM8 bus low power request. */
325     kPower_FC9_B_LPREQ = POWER_MAKE_LP_BITS(
326         PRIVATE_TCTRL0_OFFSET, 9U, PRIVATE_TSTAT0_OFFSET, 9U),   /*!< LP_FLEXCOMM9 bus low power request. */
327     kPower_FC10_B_LPREQ = POWER_MAKE_LP_BITS(
328         PRIVATE_TCTRL0_OFFSET, 10U, PRIVATE_TSTAT0_OFFSET, 10U), /*!< LP_FLEXCOMM10 bus low power request. */
329     kPower_FC11_B_LPREQ = POWER_MAKE_LP_BITS(
330         PRIVATE_TCTRL0_OFFSET, 11U, PRIVATE_TSTAT0_OFFSET, 11U), /*!< LP_FLEXCOMM11 bus low power request. */
331     kPower_FC12_B_LPREQ = POWER_MAKE_LP_BITS(
332         PRIVATE_TCTRL0_OFFSET, 12U, PRIVATE_TSTAT0_OFFSET, 12U), /*!< LP_FLEXCOMM12 bus low power request. */
333     kPower_FC13_B_LPREQ = POWER_MAKE_LP_BITS(
334         PRIVATE_TCTRL0_OFFSET, 13U, PRIVATE_TSTAT0_OFFSET, 13U), /*!< LP_FLEXCOMM13 bus low power request. */
335     kPower_FC0_F_LPREQ = POWER_MAKE_LP_BITS(
336         PRIVATE_TCTRL1_OFFSET, 0U, PRIVATE_TSTAT0_OFFSET, 16U),  /*!< LP_FLEXCOMM0 function low power request. */
337     kPower_FC1_F_LPREQ = POWER_MAKE_LP_BITS(
338         PRIVATE_TCTRL1_OFFSET, 1U, PRIVATE_TSTAT0_OFFSET, 17U),  /*!< LP_FLEXCOMM1 function low power request. */
339     kPower_FC2_F_LPREQ = POWER_MAKE_LP_BITS(
340         PRIVATE_TCTRL1_OFFSET, 2U, PRIVATE_TSTAT0_OFFSET, 18U),  /*!< LP_FLEXCOMM2 function low power request. */
341     kPower_FC3_F_LPREQ = POWER_MAKE_LP_BITS(
342         PRIVATE_TCTRL1_OFFSET, 3U, PRIVATE_TSTAT0_OFFSET, 19U),  /*!< LP_FLEXCOMM3 function low power request. */
343     kPower_FC4_F_LPREQ = POWER_MAKE_LP_BITS(
344         PRIVATE_TCTRL1_OFFSET, 4U, PRIVATE_TSTAT0_OFFSET, 20U),  /*!< LP_FLEXCOMM4 function low power request. */
345     kPower_FC5_F_LPREQ = POWER_MAKE_LP_BITS(
346         PRIVATE_TCTRL1_OFFSET, 5U, PRIVATE_TSTAT0_OFFSET, 21U),  /*!< LP_FLEXCOMM5 function low power request. */
347     kPower_FC6_F_LPREQ = POWER_MAKE_LP_BITS(
348         PRIVATE_TCTRL1_OFFSET, 6U, PRIVATE_TSTAT0_OFFSET, 22U),  /*!< LP_FLEXCOMM6 function low power request. */
349     kPower_FC7_F_LPREQ = POWER_MAKE_LP_BITS(
350         PRIVATE_TCTRL1_OFFSET, 7U, PRIVATE_TSTAT0_OFFSET, 23U),  /*!< LP_FLEXCOMM7 function low power request. */
351     kPower_FC8_F_LPREQ = POWER_MAKE_LP_BITS(
352         PRIVATE_TCTRL1_OFFSET, 8U, PRIVATE_TSTAT0_OFFSET, 24U),  /*!< LP_FLEXCOMM8 function low power request. */
353     kPower_FC9_F_LPREQ = POWER_MAKE_LP_BITS(
354         PRIVATE_TCTRL1_OFFSET, 9U, PRIVATE_TSTAT0_OFFSET, 25U),  /*!< LP_FLEXCOMM9 function low power request. */
355     kPower_FC10_F_LPREQ = POWER_MAKE_LP_BITS(
356         PRIVATE_TCTRL1_OFFSET, 10U, PRIVATE_TSTAT0_OFFSET, 26U), /*!< LP_FLEXCOMM10 function low power request. */
357     kPower_FC11_F_LPREQ = POWER_MAKE_LP_BITS(
358         PRIVATE_TCTRL1_OFFSET, 11U, PRIVATE_TSTAT0_OFFSET, 27U), /*!< LP_FLEXCOMM11 function low power request. */
359     kPower_FC12_F_LPREQ = POWER_MAKE_LP_BITS(
360         PRIVATE_TCTRL1_OFFSET, 12U, PRIVATE_TSTAT0_OFFSET, 28U), /*!< LP_FLEXCOMM12 function low power request. */
361     kPower_FC13_F_LPREQ = POWER_MAKE_LP_BITS(
362         PRIVATE_TCTRL1_OFFSET, 13U, PRIVATE_TSTAT0_OFFSET, 29U), /*!< LP_FLEXCOMM13 function low power request. */
363 
364     kPower_GPIO0_LPREQ =
365         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 0U, PRIVATE_TSTAT1_OFFSET, 2U),   /*!< GPIO0 low power request. */
366     kPower_GPIO1_LPREQ =
367         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 1U, PRIVATE_TSTAT1_OFFSET, 3U),   /*!< GPIO1 low power request. */
368     kPower_GPIO2_LPREQ =
369         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 2U, PRIVATE_TSTAT1_OFFSET, 4U),   /*!< GPIO2 low power request. */
370     kPower_GPIO3_LPREQ =
371         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 3U, PRIVATE_TSTAT1_OFFSET, 5U),   /*!< GPIO3 low power request. */
372     kPower_GPIO4_LPREQ =
373         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 4U, PRIVATE_TSTAT1_OFFSET, 6U),   /*!< GPIO4 low power request. */
374     kPower_GPIO5_LPREQ =
375         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 5U, PRIVATE_TSTAT1_OFFSET, 7U),   /*!< GPIO5 low power request. */
376     kPower_GPIO6_LPREQ =
377         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 6U, PRIVATE_TSTAT1_OFFSET, 8U),   /*!< GPIO6 low power request. */
378     kPower_GPIO7_LPREQ =
379         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 7U, PRIVATE_TSTAT1_OFFSET, 9U),   /*!< GPIO7 low power request. */
380     kPower_SAI0_LPREQ =
381         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 8U, PRIVATE_TSTAT1_OFFSET, 10U),  /*!< SAI0 low power request. */
382     kPower_SAI1_LPREQ =
383         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 9U, PRIVATE_TSTAT1_OFFSET, 11U),  /*!< SAI1 low power request. */
384     kPower_SAI2_LPREQ =
385         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 10U, PRIVATE_TSTAT1_OFFSET, 12U), /*!< SAI2 low power request. */
386     kPower_TRNG_STOP =
387         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 11U, PRIVATE_TSTAT1_OFFSET, 13U), /*!< TRNG stop request. */
388     kPower_XSPI0_STOP =
389         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 12U, PRIVATE_TSTAT1_OFFSET, 14U), /*!< XSPI0 stop request. */
390     kPower_XSPI1_STOP =
391         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 14U, PRIVATE_TSTAT1_OFFSET, 15U), /*!< XSPI1 stop request. */
392     kPower_I3C0_STOP =
393         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 16U, PRIVATE_TSTAT1_OFFSET, 16U), /*!< I3C0 stop request. */
394     kPower_I3C1_STOP =
395         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 17U, PRIVATE_TSTAT1_OFFSET, 17U), /*!< I3C1 stop request. */
396     kPower_GDET0_LPREQ =
397         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 18U, PRIVATE_TSTAT1_OFFSET, 0U),  /*!< GDET0 low power request. */
398     kPower_GDET1_LPREQ =
399         POWER_MAKE_LP_BITS(PRIVATE_TCTRL2_OFFSET, 19U, PRIVATE_TSTAT1_OFFSET, 1U),  /*!< GDET1 low power request. */
400 #else
401     kPower_EDMA2_STOP =
402         POWER_MAKE_LP_BITS(PRIVATE_CCTRL0_OFFSET, 0U, PRIVATE_CSTAT0_OFFSET, 0U), /*!< EDMA2 stop request. */
403     kPower_EDMA3_STOP =
404         POWER_MAKE_LP_BITS(PRIVATE_CCTRL0_OFFSET, 1U, PRIVATE_CSTAT0_OFFSET, 1U), /*!< EDMA3 stop request. */
405 
406     kPower_FC17_B_LPREQ = POWER_MAKE_LP_BITS(
407         PRIVATE_TCTRL0_OFFSET, 0U, PRIVATE_TSTAT0_OFFSET, 0U),  /*!< LP_FLEXCOMM17 bus low power request. */
408     kPower_FC18_B_LPREQ = POWER_MAKE_LP_BITS(
409         PRIVATE_TCTRL0_OFFSET, 1U, PRIVATE_TSTAT0_OFFSET, 1U),  /*!< LP_FLEXCOMM18 bus low power request. */
410     kPower_FC19_B_LPREQ = POWER_MAKE_LP_BITS(
411         PRIVATE_TCTRL0_OFFSET, 2U, PRIVATE_TSTAT0_OFFSET, 2U),  /*!< LP_FLEXCOMM19 bus low power request. */
412     kPower_FC20_B_LPREQ = POWER_MAKE_LP_BITS(
413         PRIVATE_TCTRL0_OFFSET, 3U, PRIVATE_TSTAT0_OFFSET, 3U),  /*!< LP_FLEXCOMM20 bus low power request. */
414     kPower_FC17_F_LPREQ = POWER_MAKE_LP_BITS(
415         PRIVATE_TCTRL0_OFFSET, 4U, PRIVATE_TSTAT0_OFFSET, 16U), /*!< LP_FLEXCOMM17 function low power request. */
416     kPower_FC18_F_LPREQ = POWER_MAKE_LP_BITS(
417         PRIVATE_TCTRL0_OFFSET, 5U, PRIVATE_TSTAT0_OFFSET, 17U), /*!< LP_FLEXCOMM18 function low power request. */
418     kPower_FC19_F_LPREQ = POWER_MAKE_LP_BITS(
419         PRIVATE_TCTRL0_OFFSET, 6U, PRIVATE_TSTAT0_OFFSET, 18U), /*!< LP_FLEXCOMM19 function low power request. */
420     kPower_FC20_F_LPREQ = POWER_MAKE_LP_BITS(
421         PRIVATE_TCTRL0_OFFSET, 7U, PRIVATE_TSTAT0_OFFSET, 19U), /*!< LP_FLEXCOMM20 function low power request. */
422     kPower_SAI3_LPREQ =
423         POWER_MAKE_LP_BITS(PRIVATE_TCTRL0_OFFSET, 8U, PRIVATE_TSTAT0_OFFSET, 4U),  /*!< SAI3 low power request. */
424     kPower_GPIO8_LPREQ =
425         POWER_MAKE_LP_BITS(PRIVATE_TCTRL0_OFFSET, 9U, PRIVATE_TSTAT0_OFFSET, 5U),  /*!< GPIO8 low power request. */
426     kPower_GPIO9_LPREQ =
427         POWER_MAKE_LP_BITS(PRIVATE_TCTRL0_OFFSET, 10U, PRIVATE_TSTAT0_OFFSET, 6U), /*!< GPIO9 low power request. */
428     kPower_GPIO10_LPREQ =
429         POWER_MAKE_LP_BITS(PRIVATE_TCTRL0_OFFSET, 11U, PRIVATE_TSTAT0_OFFSET, 7U), /*!< GPIO10 low power request. */
430     kPower_I3C2_STOP =
431         POWER_MAKE_LP_BITS(PRIVATE_TCTRL0_OFFSET, 20U, PRIVATE_TSTAT0_OFFSET, 8U), /*!< I3C2 low power request. */
432     kPower_I3C3_STOP =
433         POWER_MAKE_LP_BITS(PRIVATE_TCTRL0_OFFSET, 21U, PRIVATE_TSTAT0_OFFSET, 9U), /*!< I3C3 low power request. */
434 #endif
435 } lp_bit_t;
436 
437 /*! @brief PMIC mode pin configuration API parameter */
438 typedef enum _pmic_mode_reg
439 {
440     kCfg_Run   = 0xA0U, /*!< PDRUNCFG0 register offset. */
441     kCfg_Sleep = 0xB8U, /*!< PDSLEEPCFG0 register offset. */
442 } pmic_mode_reg_t;
443 
444 /*! @brief Power mode configuration API parameter */
445 typedef enum _power_mode_config
446 {
447     kPower_Sleep              = 0U, /*!< Sleep mode. */
448     kPower_DeepSleep          = 1U, /*!< Deep Sleep mode. */
449     kPower_DeepSleepRetention = 2U, /*!< Deep Sleep Retention(DSR) mode. */
450     kPower_DeepPowerDown      = 3U, /*!< Deep Power Down(DPD) mode. */
451     kPower_FullDeepPowerDown  = 4U, /*!< Full Deep Power Down(FDPD) mode. */
452 } power_mode_cfg_t;
453 
454 /*!
455  * @brief DMA Wakeup sources.
456  *
457  */
458 enum _power_hwwake_src
459 {
460     kPower_HWWakeSrcMicfil     = 0x1U, /*!< Enables DMA to wakeup by MICFIL DMA request.*/
461     kPower_HWWakeSrcFlexio     = 0x2U, /*!< Enables DMA to wakeup by FLEXIO DMA request.*/
462     kPower_HWWakeSrcLpFlexcomm = 0x4U, /*!< Enables DMA to wakeup by LP_FLEXCOMM0-13(CPU0), LP_FLEXCOMM17-20(CPU1) DMA
463                                    request.*/
464 #if defined(SLEEPCON_COMPT)
465     kPower_HWWakeSrcHsSpi = 0x8U,      /*!< Enables DMA to wakeup by LPSPI14 and LPSPI16 DMA request.*/
466 #endif
467     kPower_HWWakeSrcSai = 0x10U,       /*!< Enables DMA to wakeup by SAI0-2(CPU0), SAI3(CPU1) request.*/
468 };
469 
470 /*!
471  * @brief Definition for shared resources.
472  *
473  */
474 enum _power_shared_resource_mask
475 {
476     kPower_MaskAdc0    = 0x1U,      /*!< ADC0 mask.*/
477     kPower_MaskAcmp0   = 0x2U,      /*!< ACMP0 mask.*/
478     kPower_MaskMicfil  = 0x4U,      /*!< MICFIL mask.*/
479     kPower_MaskLpi2c15 = 0x8U,      /*!< LPI2C15 mask.*/
480     kPower_MaskGdet2   = 0x10U,     /*!< GDET2 mask.*/
481     kPower_MaskGdet3   = 0x20U,     /*!< GDET3 mask.*/
482     kPower_MaskRtc     = 0x40U,     /*!< RTC mask.*/
483     kPower_MaskVgpu    = 0x10000U,  /*!< VGPU mask.*/
484     kPower_MaskEzhv    = 0x20000U,  /*!< EZHV mask.*/
485     kPower_MaskXspi2   = 0x40000U,  /*!< XSPI2 mask.*/
486     kPower_MaskLpspi14 = 0x80000U,  /*!< LPSPI14 mask.*/
487     kPower_MaskLpspi16 = 0x100000U, /*!< LPSPI16 mask.*/
488     kPower_MaskFlexio  = 0x200000U, /*!< FlexIO mask.*/
489     kPower_MaskNic0    = 0x400000U, /*!< NIC0 mask.*/
490     kPower_MaskNic1    = 0x800000U, /*!< NIC1 mask.*/
491     kPower_MaskAll     = 0xFF007FU, /*!< Mask all shared modules.*/
492 };
493 
494 /*!
495  * @brief pad voltage range value for the 3V capable IOs. To reduce power the IOs can be configured for 1.8V or 3.3V
496 operation, powering down the detector, but requiring the application to restrict the IO supply voltage to the selected
497 range.
498  */
499 typedef enum _power_pad_vrange_val
500 {
501     kPadVol_Continuous = 0U, /*!< Continuous mode, VDDE detector on. */
502     kPadVol_171_198    = 1U, /*!< Voltage from 1.71V to 1.98V. supply detector off. */
503     kPadVol_300_360    = 2U, /*!< Voltage from 3.00V to 3.60V. supply detector off. */
504 } power_pad_vrange_val_t;
505 
506 /*! @brief Body Bias domain definition */
507 enum _body_bias_domain
508 {
509     kPower_BodyBiasVdd2Sram = PMC_PDRUNCFG0_RBBSR2_PD_MASK, /*!< VDD2 domain RAMs. */
510     kPower_BodyBiasVdd1Sram = PMC_PDRUNCFG0_RBBSR1_PD_MASK, /*!< VDD1 domain RAMs. */
511     kPower_BodyBiasVddn     = PMC_PDRUNCFG0_RBBN_PD_MASK,   /*!< VDDN domain. */
512     kPower_BodyBiasVdd2     = PMC_PDRUNCFG0_RBB2_PD_MASK,   /*!< VDD2 domain. */
513     kPower_BodyBiasVdd1     = PMC_PDRUNCFG0_RBB1_PD_MASK,   /*!< VDD1 domain. */
514 };
515 
516 /*! @brief Regulator definition for Regulator and LVD configuration. */
517 typedef enum _power_regulator
518 {
519     kRegulator_DCDC    = 0U, /*!< DCDC used for VDDN. */
520     kRegulator_Vdd2LDO = 1U, /*!< VDD2 LDO. */
521     kRegulator_Vdd1LDO = 2U, /*!< VDD1 LDO. */
522 } power_regulator_t;
523 
524 /*!
525  * @brief Regulator voltage configuraton. Configure the regulator voltage in uV.
526  */
527 typedef union _power_regulator_voltage
528 {
529     struct
530     {
531         uint32_t vsel0; /*!< DCDC VSEL0. Voltage = 0.5 V + 6.25 mV * value of vsel0. Maximum value = 1150000uV. */
532         uint32_t vsel1; /*!< DCDC VSEL1. Voltage = 0.5 V + 6.25 mV * value of vsel1. Maximum value = 1150000uV. */
533     } DCDC;
534     struct
535     {
536         uint32_t vsel0; /*!< LDO VSEL0. Voltage = 0.45 V + 12.5 mV * vsel0. Maximum value = 1150000uV. */
537         uint32_t vsel1; /*!< LDO VSEL1. Voltage = 0.45 V + 12.5 mV * vsel1. Maximum value = 1150000uV.*/
538         uint32_t vsel2; /*!< LDO VSEL2. Voltage = 0.45 V + 12.5 mV * vsel2. Maximum value = 1150000uV. */
539         uint32_t vsel3; /*!< LDO VSEL3. Voltage = 0.45 V + 12.5 mV * vsel3. Maximum value = 1150000uV. */
540     } LDO;
541     uint32_t vsel[4];
542 } power_regulator_voltage_t;
543 
544 /*!
545  * @brief LDO mode definition.
546  */
547 enum _power_ldo_mode
548 {
549     kPower_LDOMode_Bypass = 0U, /*!< LDO Bypass mode. */
550     kPower_LDOMode_HP     = 1U, /*!< LDO High Power mode. */
551     kPower_LDOMode_LP     = 2U, /*!< LDO Low Power mode. */
552 };
553 
554 /*!
555  * @brief DCDC mode definition.
556  */
557 enum _power_dcdc_mode
558 {
559     kPower_DCDCMode_HP = 0U, /*!< LDO High Power mode. */
560     kPower_DCDCMode_LP = 1U, /*!< LDO Low Power mode. */
561 };
562 
563 /*! @brief VDDN, VDD1 or VDD2 supply source. */
564 typedef enum _power_vdd_src
565 {
566     kVddSrc_PMC  = 0U, /*!< Supplied by onchip regulator in PMC, DCDC for VDDN, LDO1 for VDD1, LDO2 for VDD2. */
567     kVddSrc_PMIC = 1U, /*!< Supplied by external PMIC. */
568 } power_vdd_src_t;
569 
570 /*!
571  * @brief LVD voltage configuraton. Configure the LVD voltage in uV. Falling trip = 0.5V + 10 mV * bitfield value.
572  */
573 typedef union _power_lvd_voltage
574 {
575     struct
576     {
577         uint32_t lvl0; /*!< VDDN LVD level0, uV. */
578         uint32_t lvl1; /*!< VDDN LVD level1, uV. */
579     } VDDN;
580     struct
581     {
582         uint32_t lvl0; /*!< VDD1/2 LVD level0, uV. */
583         uint32_t lvl1; /*!< VDD1/2 LVD level1, uV. */
584         uint32_t lvl2; /*!< VDD1/2 LVD level2, uV. */
585         uint32_t lvl3; /*!< VDD1/2 LVD level3, uV. */
586     } VDD12;
587     uint32_t lvl[4];
588 } power_lvd_voltage_t;
589 
590 #if defined(PMC0)
591 
592 /*! @brief Internal Regulator and LDO power control bits */
593 enum _power_regulator_pd_control
594 {
595     kPower_SCPC    = PMC_POWERCFG_SCPCPD_MASK, /*!< SCPC Power control, controls both SCPCs, for all power mode. */
596     kPower_Vdd1LDO = PMC_POWERCFG_LDO1PD_MASK, /*!< LDO VDD1 Power control, for all power mode. */
597     kPower_Vdd2LDO = PMC_POWERCFG_LDO2PD_MASK, /*!< LDO VDD2 Power control, for all power mode. */
598     kPower_DCDC    = PMC_POWERCFG_DCDCPD_MASK, /*!< DCDC Power control, for all power mode. */
599 };
600 
601 /*! @brief Internal Regulator and LDO power control bits for FDSR power mode. */
602 enum _power_regulator_pd_control_fdsr
603 {
604     kPower_Vdd1SCPC_FDSR =
605         PMC_POWERCFG_FDSCP1PD_MASK, /*!< SCPC VDD1 Power control in FDSR mode, overridden when [SCPCPD]=1. */
606     kPower_Vdd2SCPC_FDSR =
607         PMC_POWERCFG_FDSCP2PD_MASK, /*!< SCPC VDD2 Power control in FDSR mode, overridden when [SCPCPD]=1. */
608     kPower_Vdd1LDO_FDSR =
609         PMC_POWERCFG_FDLDO1PD_MASK, /*!< LDO VDD1 Power control in FDSR mode, overridden when [LPO1PD]=1. */
610     kPower_Vdd2LDO_FDSR =
611         PMC_POWERCFG_FDLDO2PD_MASK, /*!< LDO VDD2 Power control in FDSR mode, overridden when [LPO2PD]=1. */
612     kPower_DCDC_FDSR = PMC_POWERCFG_FDDCPD_MASK, /*!< DCDC Power control in FDSR mode, overridden when [DCDCPD]=1. */
613 };
614 
615 /*! @brief RBB Body Bias voltage definition */
616 typedef enum _body_bias_voltage
617 {
618     kBodyBias_1V0 = 0U, /*!< Reverse Body Bias Voltage 1.0V. */
619     kBodyBias_1V3 = 1U, /*!< Reverse Body Bias Voltage 1.3V. */
620 } body_bias_voltage_t;
621 
622 /*!
623  * @brief RBB Body Bias voltage. 0b - Voltage is set to 1.0V, 1b - Voltage is set to 1.3V.
624  */
625 typedef struct _power_rbb_voltage
626 {
627     uint32_t rbbVdd1 : 1; /*!< Reverse Body Bias Voltage for VDD1 Domain. @ref body_bias_voltage_t */
628     uint32_t : 7;         /*!< Reserved. */
629     uint32_t rbbVdd2 : 1; /*!< Reverse Body Bias Voltage for VDD2 Domain. @ref body_bias_voltage_t */
630     uint32_t : 7;         /*!< Reserved. */
631     uint32_t rbbVddn : 1; /*!< Reverse Body Bias Voltage for VDDN Domain. @ref body_bias_voltage_t */
632     uint32_t : 15;        /*!< Reserved. */
633 } power_rbb_voltage_t;
634 
635 /*!
636  * @brief POR voltage. Falling trip voltage = 0.4 + 10 mV * value.
637  */
638 typedef struct _power_por_voltage
639 {
640     uint32_t Vdd1Lvl : 5; /*!< POR falling trip value in VDD1 Domain, falling trip voltage = 0.4 + 10 mV * value. */
641     uint32_t : 3;         /*!< Reserved. */
642     uint32_t Vdd2Lvl : 5; /*!< POR falling trip value in VDD2 Domain, falling trip voltage = 0.4 + 10 mV * value. */
643     uint32_t : 3;         /*!< Reserved. */
644     uint32_t VddnLvl : 5; /*!< POR falling trip value in VDDN Domain, falling trip voltage = 0.4 + 10 mV * value. */
645 } power_por_voltage_t;
646 
647 /*! @brief IO Banking bitmask.  */
648 typedef enum _power_io_bank
649 {
650     kPower_IOBank0 = 0x1U,  /*!< Port 0/1/3 in VDD2_COM domain. */
651     kPower_IOBank1 = 0x2U,  /*!< Port 2 in VDD2_COM domain. */
652     kPower_IOBank2 = 0x4U,  /*!< Port 4 in VDDN_COM domain. */
653     kPower_IOBank3 = 0x8U,  /*!< Port 5 in VDD2_COM domain. */
654     kPower_IOBank4 = 0x10U, /*!< Port 6 in VDD2_COM domain. */
655     kPower_IOBank5 = 0x20U, /*!< Port 7 in VDD2_COM domain. */
656     kPower_IOBank6 = 0x40U, /*!< Port 8/9/10 in VDD1_SENSE domain. */
657     kPower_IOBank7 = 0x80U, /*!< PMIC_I2C in VDD1_SENSE domain. */
658 } power_io_bank_t;
659 #endif
660 
661 /*******************************************************************************
662  * API
663  ******************************************************************************/
664 
665 #ifdef __cplusplus
666 extern "C" {
667 #endif
668 
669 /*!
670  * @brief API to enable PDRUNCFG bit in the SLEEPCON and PMC. Note that enabling the bit powers down the peripheral
671  *
672  * @param en    peripheral for which to enable the PDRUNCFG bit
673  */
674 void POWER_EnablePD(pd_bit_t en);
675 
676 /*!
677  * @brief API to disable PDRUNCFG bit in the SLEEPCON and PMC. Note that disabling the bit powers up the peripheral
678  *
679  * @param en    peripheral for which to disable the PDRUNCFG bit
680  */
681 void POWER_DisablePD(pd_bit_t en);
682 
683 /*!
684  * @brief API to request a module entering low power. This API send low power/stop requests to a module and wait the
685 acknowledgement from the module. For peripherals that are being used by a domain, using this low power request handshake
686 is recommended to make sure the module is fully stopped before the module is powered down or clock gated.
687  *
688  * @param en    peripheral for which to enable the low power request.
689  * @return  kStatus_Success for succeed, kStatus_Timeout for tiemout.
690  */
691 status_t POWER_ModuleEnterLPRequest(lp_bit_t en);
692 
693 /*!
694  * @brief API to negate low power/stop requests to a module(module resume regular operation).
695  *
696  * @param en peripheral for which to disable the low power request.
697  */
698 void POWER_ModuleExitLPRequest(lp_bit_t en);
699 
700 /*!
701  * @brief   Set PMIC_MODE pins configure value.
702  * @param   mode : PMIC MODE pin value. This field is aggregated low.
703  * @param   reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
704  * @return  PMIC_MODE pins value in PDSLEEPCFG0
705  */
706 void POWER_SetPmicMode(uint32_t mode, pmic_mode_reg_t reg);
707 
708 /**
709  * @brief   Get PMIC_MODE pins configure value.
710  * @param   reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
711  * @return  PMIC_MODE pins value in PDSLEEPCFG0 or PDRUNCFG0
712  */
713 uint32_t POWER_GetPmicMode(pmic_mode_reg_t reg);
714 
715 #if defined(PMC0)
716 /*!
717  * @brief Configure pad voltage level for the 3V capable IOs(FLEXIO pads only) which have a dectector to sense the value
718  * of supply. The Continuous cost more power due to enabled voltage detector.
719  *
720  * NOTE: BE CAUTIOUS TO CALL THIS API. IF THE PAD SUPPLY IS BEYOND THE SET RANGE, SILICON MIGHT BE DAMAGED.
721  *
722  * @param vrange pad voltage range.
723  */
POWER_SetPio2VoltRange(power_pad_vrange_val_t vrange)724 static inline void POWER_SetPio2VoltRange(power_pad_vrange_val_t vrange)
725 {
726     PMC0->PADVRANGE = (uint32_t)vrange & PMC_PADVRANGE_VRANGE_MASK;
727 }
728 #endif
729 
730 /*!
731  * @brief API to enable deep sleep bit in the ARM Core.
732  */
POWER_EnableDeepSleep(void)733 static inline void POWER_EnableDeepSleep(void)
734 {
735     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
736 }
737 
738 /*!
739  * @brief API to disable deep sleep bit in the ARM Core.
740  */
POWER_DisableDeepSleep(void)741 static inline void POWER_DisableDeepSleep(void)
742 {
743     SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
744 }
745 
746 /*!
747  * @brief API to apply updated PMC PDRUNCFG bits in the Sysctl0.
748  */
749 void POWER_ApplyPD(void);
750 
751 /**
752  * @brief   Clears the PMC event flags state.
753  * @param   statusMask : A bitmask of event flags that are to be cleared.
754  */
755 void POWER_ClearEventFlags(uint32_t statusMask);
756 
757 /**
758  * @brief   Get the PMC event flags state.
759  * @return  PMC FLAGS register value
760  */
761 uint32_t POWER_GetEventFlags(void);
762 
763 /*!
764  * @brief   Enable the PMC interrupt requests.
765  * @param   interruptMask : A bitmask of interrupts to enable.
766  */
767 void POWER_EnableInterrupts(uint32_t interruptMask);
768 
769 /*!
770  * @brief   Disable the PMC interrupt requests.
771  * @param   interruptMask : A bitmask of interrupts to disable.
772  */
773 void POWER_DisableInterrupts(uint32_t interruptMask);
774 
775 /*!
776  * @brief   Enable the PMC reset requests.
777  * @param   resetMask : A bitmask of Reset to enable, refer to PMC CTRL register descritpion in RM.
778  */
779 void POWER_EnableResets(uint32_t resetMask);
780 
781 /*!
782  * @brief   Disable the PMC reset requests.
783  * @param   resetMask : A bitmask of Reset to disable, refer to PMC CTRL register descritpion in RM.
784  */
785 void POWER_DisableResets(uint32_t resetMask);
786 
787 /*!
788  * @brief Enable specific interrupt for wake-up from deep-sleep mode.
789  * Enable the interrupt for wake-up from deep sleep mode.
790  * Some interrupts are typically used in sleep mode only and will not occur during
791  * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
792  * those clocks (significantly increasing power consumption in the reduced power mode),
793  * making these wake-ups possible.
794  * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
795  * @param interrupt The IRQ number.
796  */
797 void EnableDeepSleepIRQ(IRQn_Type interrupt);
798 
799 /*!
800  * @brief Disable specific interrupt for wake-up from deep-sleep mode.
801  * Disable the interrupt for wake-up from deep sleep mode.
802  * Some interrupts are typically used in sleep mode only and will not occur during
803  * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
804  * those clocks (significantly increasing power consumption in the reduced power mode),
805  * making these wake-ups possible.
806  * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
807  * @param interrupt The IRQ number.
808  */
809 void DisableDeepSleepIRQ(IRQn_Type interrupt);
810 
811 /*!
812  * @brief Enable specific DMA channels to generate a wake-up from deep-sleep mode.
813  * DMA wakeup is an automatic hardware mechanism that handles DMA transactions for selected modules without the need for
814  * core processing. Software can configure individual DMA channels to generate a wakeup when they receive a DMA request.
815  * The DMA wakeup triggers an exit from Deep Sleep mode except the core, which remains sleeping.
816  * @param sources The bits mask for eDMA wakeup sources. Refers #_power_hwwake_src.
817  */
818 void POWER_EnableDMAHWWake(uint32_t sources);
819 
820 /*!
821  * @brief Disable specific DMA channels to generate a wake-up from deep-sleep mode.
822  * Disable the DMA channels for wake-up from deep sleep mode.
823  * @param sources The bits mask for eDMA wakeup sources. Refers #_power_hwwake_src.
824  */
825 void POWER_DisableDMAHWWake(uint32_t sources);
826 
827 /*!
828  * @brief   Configure PMC for auto wakeup.This feature allows PMC to wake up some amount of time after the domain enters
829  * Deep Sleep. The timer is clocked by PMC's internal 16 MHz clock. If both timers in compute and sense are enabled at
830  * the same time, wake-up will occur after BOTH timers time out (i.e. the max timeout value between the two is used).
831  * @param   ticks : The ticks of 16MHz PMC internal clock to wait before waking up the domain after it goes to
832  * DeepSleep.
833  */
834 void POWER_EnableAutoWake(uint16_t ticks);
835 
836 /*!
837  * @brief Enable low power request masking for shared modules.
838  * Enabling the mask will relinquish the caller domain's control over the module, and give the other domain exclusive
839  * control over low-power requests to the module.
840  * NOTE,  The masking of a shared module must NOT be disabled in both Compute and Sense domain.
841  *
842  * @param mask An OR'd bitmask of shared modules to be masked from low power request, ref @ref
843  * _power_shared_resource_mask and SLEEPCON SHARED_MASK0 register in the RM. DeepSleep.
844  */
845 void POWER_EnableLPRequestMask(uint32_t mask);
846 
847 /*!
848  * @brief Disable low power request masking for shared modules.
849  * Disabling the mask means this domain will own the module. Only one domain should own each shared module.
850  *
851  * @param mask An OR'd bitmask of shared modules to be enabled from low power request, ref @ref
852  * _power_shared_resource_mask and SLEEPCON SHARED_MASK0 register in the RM. DeepSleep.
853  */
854 void POWER_DisableLPRequestMask(uint32_t mask);
855 
856 /*!
857  * @brief Enable AFBB mode for various domains in active mode.
858  * AFBB mode should always be used for domains that are active/clocked.
859  * Note, users should call POWER_ApplyPD() to make the change take effect.
860  * @param mask : A bitmask of domains to enable AFBB mode, refer to @ref _body_bias_domain and PMC PDRUNCFG0 register
861  * descritpion in RM.
862  */
863 void POWER_EnableRunAFBB(uint32_t mask);
864 
865 /*!
866  * @brief Enable RBB mode for various domains in active mode.
867  * This function should only be used when one CPU will not be making use of one of the voltage domains.Configuring the
868  * unused voltages for RBB will allow the other domain to have full control of the body bias mode for the voltages even
869  * when both domains are in run mode.
870  * Note, users should call POWER_ApplyPD() to make the change take effect.
871  * @param mask : A bitmask of domains to enable RBB mode, refer to @ref _body_bias_domain and PMC PDRUNCFG0 register
872  * descritpion in RM.
873  */
874 void POWER_EnableRunRBB(uint32_t mask);
875 
876 /*!
877  * @brief Enable RBB mode for various domains in deep sleep mode.
878  * @param mask : A bitmask of domains to enable RBB mode, refer to @ref _body_bias_domain and PMC PDSLEEPCFG0 register
879  * descritpion in RM.
880  */
881 void POWER_EnableSleepRBB(uint32_t mask);
882 
883 /*!
884  * @brief Enable NBB mode for various domains in active mode.
885  * NBB can be a lower power option than RBB if the domain enters and exits low-power modes frequently since the wells
886  * don't charge and discharge as much on every entry/exit.
887  * @param mask : A bitmask of domains to enable NBB mode, refer to @ref _body_bias_domain and PMC PDRUNCFG0 register
888  * descritpion in RM.
889  */
890 void POWER_EnableRunNBB(uint32_t mask);
891 
892 /*!
893  * @brief Enable NBB mode for various domains in deep sleep mode.
894  * NBB can be a lower power option than RBB if the domain enters and exits low-power modes frequently since the wells
895  * don't charge and discharge as much on every entry/exit.
896  * @param mask : A bitmask of domains to enable NBB mode, refer to @ref _body_bias_domain and PMC PDSLEEPCFG0 register
897  * descritpion in RM.
898  */
899 void POWER_EnableSleepNBB(uint32_t mask);
900 
901 #if defined(PMC0)
902 
903 /*!
904  * @brief Configure the voltage used for RBB mode for each voltage domain. The voltage specified here is used for any
905  * mode where RBB is enabled.
906  * @param config Voltage selection for each voltage domain.
907  */
908 void POWER_ConfigRBBVolt(const power_rbb_voltage_t *config);
909 
910 /*!
911  * @brief Disable the on-chip regulators.
912  * This function should be used to disable the on-chip regulators for any supplies that will be powered externally
913  * (regulators are enabled by default. If disabled the regulators will keep power down until next cold reset).
914  * @param mask A bitmask of regulators to be powered down, @ref _power_regulator_pd_control and PMC POWERCFG register
915  * descripion in RM.
916  */
917 void POWER_DisableRegulators(uint32_t mask);
918 
919 /*!
920  * @brief Enable the on-chip regulators for FDSR mode.
921  * This function is used to enable the on-chip regulators for FDSR power mode.
922  * Note, If the regulator is disabled globally(by POWER_DisableRegulators), then they will automatically be powered down
923  * in all modes (using this API to request enabling them will have no effect).
924  * @param mask A bitmask of regulators to be controlled, @ref _power_regulator_pd_control_fdsr and PMC POWERCFG register
925 descripion in RM.
926 */
927 void POWER_EnableSleepRegulators(uint32_t mask);
928 
929 /*!
930  * @brief Disable the on-chip regulators for FDSR mode.
931  * This function is used to enable the on-chip regulators for FDSR power mode.
932  * Note, If the regulator is disabled globally(by POWER_DisableRegulators), then they will automatically be powered down
933  * in all modes.
934  * @param mask A bitmask of regulators to be controlled, @ref _power_regulator_control_fdsr and PMC POWERCFG register
935  * descripion in RM.
936  */
937 void POWER_DisableSleepRegulators(uint32_t mask);
938 
939 /*!
940  * @brief Set VDDN supply source, PMIC or on-chip regulator. When PMIC selected the on-chip regulator will be powered
941  * down.
942  * @param   src : #power_vdd_src_t, VDDN supply source
943  */
944 void POWER_SetVddnSupplySrc(power_vdd_src_t src);
945 
946 /*!
947  * @brief Set VDD1 supply source, PMIC or on-chip regulator. When PMIC selected the on-chip regulator will be powered
948  * down.
949  * @param   src : #power_vdd_src_t, VDDN supply source
950  */
951 void POWER_SetVdd1SupplySrc(power_vdd_src_t src);
952 
953 /*!
954  * @brief Set VDD2 supply source, PMIC or on-chip regulator. When PMIC selected the on-chip regulator will be powered
955  * down.
956  * @param   src : #power_vdd_src_t, VDDN supply source
957  */
958 void POWER_SetVdd2SupplySrc(power_vdd_src_t src);
959 
960 /*!
961  * @brief API to configure the delay for PMIC mode changes.
962  * Any time the PMIC_MODE pin values change the PMC will wait for the delay specified here to allow time for the
963  * external voltages to settle. Delay time = 250ns * 2^value. Note, need call POWER_ApplyPD() to make the change take
964  * effect.
965  *
966  * @param value Delay value, the calculated delay time(ns) = 250ns*2^value.
967  */
968 void POWER_SetPMICModeDelay(uint8_t value);
969 
970 /*!
971  * @brief Sets the POR falling trip voltages in VDD1, VDD2, and VDDN domains.
972  * When the supply voltage falls below the selected trip voltage, it triggers a cold reset.
973  * Falling trip = 0.4 + 10 mV * value
974  *
975  * @param porVolt A bitmask of values to control VDD1, VDD2, VDDN POR voltage.
976  */
977 void POWER_SetPORVoltage(const power_por_voltage_t *porVolt);
978 #endif /* PMC0 */
979 
980 /*!
981  * @brief Configure the setpoint operation for on-chip regulators and LVD.
982  * This function can configure both the target output voltages and LVD levels for each setpoint. The setpoint that is
983  * actually selected is controlled by the aggregated value of PDRUNCFG[xxx_VSEL] and PDSLEEPCFG0[xxx_VSEL]. Use the
984  * POWER_SelectRunSetpoint() or POWER_SelectSleepSetpoint() to configure the setpoint selections. The voltages selected
985  * for each regulator must also be in ascending order (VSEL0 <= VSEL1 <= VSEL2 <= VSEL3). The voltages selected for each
986  * LVD must also be in ascending order (LVL0 <= LVL1 <= LVL2 <= LVL3).
987  *
988  * NOTE, Only valid regulator for sense domain is VDD1 LDO.
989  * Note, LDOVDD1VSEL and LVDVDD1CTRL are shared between the compute and sense domains. There is no aggregation to
990  * combine the values. Whichever domain wrote the register last determines the value. It is recommended that only one
991  * domain be used to configure VDD1 setpoints.
992  *
993  * @code
994  *   const power_regulator_voltage_t regulator = {
995  *     .LDO.vsel0 = 700000,
996  *     .LDO.vsel1 = 800000,
997  *     .LDO.vsel2 = 900000,
998  *     .LDO.vsel3 = 1000000,
999  *   };
1000  *   const power_lvd_voltage_t lvd = {
1001  *     .VDD12.lvl0 = 600000,
1002  *     .VDD12.lvl1 = 700000,
1003  *     .VDD12.lvl2 = 800000,
1004  *     .VDD12.lvl3 = 900000,
1005  *   };
1006  *
1007  *   ret = POWER_ConfigRegulatorSetpoints(kRegulator_Vdd1LDO, &regulator, &lvd);
1008  * @endcode
1009  * @param regulator which regulator or power domain to configure, refer to @ref power_regulator_t.
1010  * @param volt regulator configuration pointer, refer to @ref power_regulator_voltage_t. Note, only two setpoints are
1011  * available for DCDC.
1012  * @param lvd LVD voltage configuration, refer to @ref power_lvd_voltage_t.
1013  * @return kStatus_Success for succeed, kStatus_InvalidArgument for wrong arguments.
1014  */
1015 status_t POWER_ConfigRegulatorSetpoints(power_regulator_t regulator,
1016                                         const power_regulator_voltage_t *volt,
1017                                         const power_lvd_voltage_t *lvd);
1018 
1019 /*!
1020  * @brief Configure the setpoint operation for LVD.
1021  * This function can configure LVD levels for each setpoint. The setpoint that is actually selected is controlled by
1022  * the aggregated value of PDRUNCFG[xxx_VSEL] and PDSLEEPCFG0[xxx_VSEL]. Use the POWER_SelectRunSetpoint() or
1023  * POWER_SelectSleepSetpoint() to configure the setpoint selections. The voltages selected for each LVD must be in
1024  * ascending order (LVL0 <= LVL1 <= LVL2 <= LVL3).
1025  *
1026  * NOTE, Only valid regulator for sense domain is VDD1 LDO.
1027  * Note, LDOVDD1VSEL and LVDVDD1CTRL are shared between the compute and sense domains. There is no aggregation to
1028  * combine the values. Whichever domain wrote the register last determines the value. It is recommended that only one
1029  * domain be used to configure VDD1 setpoints.
1030  *
1031  * @code
1032  *   const power_lvd_voltage_t lvd = {
1033  *     .VDD12.lvl0 = 600000,
1034  *     .VDD12.lvl1 = 700000,
1035  *     .VDD12.lvl2 = 800000,
1036  *     .VDD12.lvl3 = 900000,
1037  *   };
1038  *
1039  *   ret = POWER_ConfigLvdSetpoints(kRegulator_Vdd1LDO, &lvd);
1040  * @endcode
1041  * @param regulator which regulator or power domain to configure, refer to @ref power_regulator_t.
1042  * @param lvd LVD voltage configuration, refer to @ref power_lvd_voltage_t.
1043  * @return kStatus_Success for succeed, kStatus_InvalidArgument for wrong arguments.
1044  */
1045 status_t POWER_ConfigLvdSetpoints(power_regulator_t regulator, const power_lvd_voltage_t *lvd);
1046 
1047 /*!
1048  * @brief Get the LVD setpoints configurations.
1049  * This function can get the LVD levels for each setpoint. The setpoint that is actually selected is controlled by
1050  * the aggregated value of PDRUNCFG[xxx_VSEL] and PDSLEEPCFG0[xxx_VSEL].
1051  *
1052  * NOTE, Only valid regulator for sense domain is VDD1 LDO.
1053  *
1054  * @param regulator which regulator or power domain to get, refer to @ref power_regulator_t.
1055  * @param lvd LVD voltage configuration, refer to @ref power_lvd_voltage_t.
1056  */
1057 void POWER_GetLvdSetpoints(power_regulator_t regulator, power_lvd_voltage_t *lvd);
1058 
1059 /*!
1060  * @brief Select the setpoint(target voltage and LVD threshold) for active mode.
1061  * The requests from the compute and sense domains are aggregated, so depending on the other
1062 domain's configuration the setpoint might not change or might change later (when the other domain
1063 also requests a setpoint change).
1064  * Note, users should call POWER_ApplyPD() to make the change take effect.
1065  *
1066  * @param regulator which regulator or power domain to configure, refer to @ref power_regulator_t.
1067  * @param setpoint select which setpoint is used. Valid options for DCDC are 0-1. Valid options for VDD1/VDD2 are 0-3.
1068  */
1069 void POWER_SelectRunSetpoint(power_regulator_t regulator, uint32_t setpoint);
1070 
1071 /*!
1072  * @brief Select setpoint(target voltage and LVD threshold) in Deep Sleep (or lower) mode.
1073  * Use POWER_ConfigRegulatorSetpoints() to change the target voltage and/or LVD threshold value corresponding to each
1074  * setpoint. The requests from the compute and sense domains are aggregated,
1075  *
1076  * @param regulator which regulator or power domain to configure, refer to @ref power_regulator_t.
1077  * @param setpoint select which setpoint is used. Valid options for DCDC are 0-1. Valid options for VDD1/VDD2 are 0-3.
1078  */
1079 void POWER_SelectSleepSetpoint(power_regulator_t regulator, uint32_t setpoint);
1080 
1081 /*!
1082  * @brief Set the on-chip regulator mode in Run/Active mode.
1083  * The requests from the compute and sense domains are aggregated.
1084  *
1085  * @param regulator which regulator or power domain to configure, refer to @ref power_regulator_t.
1086  * @param mode set the workmode. Refer to @ref _power_dcdc_mode for available DCDC modes, refer to @ref _power_ldo_mode
1087  * for LDO available modes.
1088  */
1089 void POWER_SetRunRegulatorMode(power_regulator_t regulator, uint32_t mode);
1090 
1091 /*!
1092  * @brief Set the on-chip regulator mode in Deep Sleep mode.
1093  * The requests from the compute and sense domains are aggregated.
1094  *
1095  * @param regulator which regulator or power domain to configure, refer to @ref power_regulator_t.
1096  * @param mode set the workmode. Refer to @ref _power_dcdc_mode for available DCDC modes, refer to @ref _power_ldo_mode
1097  * for LDO available modes.
1098  */
1099 void POWER_SetSleepRegulatorMode(power_regulator_t regulator, uint32_t mode);
1100 
1101 /*!
1102  * @brief Reset the IO bank.
1103  * Sets the IO bank reset which tristates the ports. Intended to be used prior to powering off the VDDIO supplies.
1104  *
1105  * @param mask A bitmask of IO Banks to be reseted, @ref power_io_bank_t and PMC PADCFG register. The register reset by
1106  * cold reset.
1107  */
1108 void POWER_ResetIOBank(uint32_t mask);
1109 
1110 /*!
1111  * @brief IO Bank Isolation Hold.
1112  *  Maintains IO bank isolation state after wake-up from FDSR/DPD modes. If clear, the IO bank's state will be retained
1113  * during FDSR & DPD modes, but will be controllable after wake-up. If set, the IO bank will remain in retain mode until
1114  * ISOCTRL cleared by software.
1115  *
1116  * @param mask A bitmask of IO Banks to be set, @ref power_io_bank_t and PMC PADCFG register. The register reset by cold
1117  * reset.
1118  */
1119 void POWER_IOBankIsolationHold(uint32_t mask);
1120 
1121 /*!
1122  * @brief Clear the IO bank Isolation Hold and regain state control.
1123  * This bit cannot be cleared if associated domain is not powered.
1124  *
1125  * @param mask A bitmask of IO Banks to be clear, @ref power_io_bank_t and PMC PADCFG register. The register reset by
1126  * cold reset.
1127  */
1128 void POWER_IOBankClearIsolationHold(uint32_t mask);
1129 
1130 /**
1131  * @brief   Configures and enters in SLEEP low power mode
1132  */
1133 void POWER_EnterSleep(void);
1134 
1135 /*!
1136  * @brief PMC Deep Sleep function call
1137  *
1138  * NOTE, the body bias and DCDC, LDO configurations in PMC_PDSLEECFG0 is not covered by this API, please use
1139  * @ref POWER_EnableSleepRBB or @ref POWER_EnableSleepNBB and @ref POWER_SelectSleepSetpoint for those settings.
1140  *
1141  * NOTE, the MAINPLL and AUDIO PLL need special power up sequence, so it can't be power down/on automatically during the
1142  * mode change. Application need turn off the PLL before the low power mode entry and re-initialize the PLL after
1143  * wakeup.
1144  * @param   exclude_from_pd  Bit mask of the SLEEPCON_SLEEPCFG and PMC_PDSLEEPCFG0 ~ PMC_PDSLEEPCFG5 that needs to be
1145  * powered on during Deep Sleep mode. The configuration for PMC from Compute domain and Sense domain are aggregated, and
1146  * the higher power mode always wins.
1147  */
1148 void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[7]);
1149 
1150 #if defined(PMC0)
1151 /*!
1152  * @brief Compute domain enter Deep Sleep Retention mode API.
1153  * Deep Sleep Retention (DSR) mode is a deeper low power state than Deep Sleep mode.  DSR does not provide the option to
1154  * keep selected module clocks on for wake-up. DSR mode allows significant portions of the chip to be powered-down while
1155  * maintaining some level of state retention.
1156  *
1157  * NOTE, the body bias and DCDC, LDO configurations in PMC_PDSLEECFG0 is not covered by this API, please use
1158  * @ref POWER_EnableSleepRBB or @ref POWER_EnableSleepNBB and @ref POWER_SelectSleepSetpoint for those settings.
1159  *
1160  * NOTE, the MAINPLL and AUDIO PLL need special power up sequence, so it can't be power down/on automatically during the
1161  * mode change. Application need turn off the PLL before the low power mode entry and re-initialize the PLL after
1162  * wakeup.
1163  *
1164  * @param   exclude_from_pd  Bit mask of the SLEEPCON_SLEEPCFG and PMC_PDSLEEPCFG0 ~ PMC_PDSLEEPCFG5 that needs to be
1165  * powered on(bits cleared) during the power mode. The configuration for PMC from Compute domain and Sense domain are
1166  * aggregated, and the higher power mode always wins.
1167  */
1168 void POWER_EnterDSR(const uint32_t exclude_from_pd[7]);
1169 #else
1170 /*!
1171  * @brief Sense domain requests entering Deep Sleep Retention mode API. Deep Sleep Retention (DSR) mode is a deeper low
1172  * power state than Deep Sleep mode. DSR mode allows significant portions of the chip to be powered-down while
1173  * maintaining some level of state retention. The Sense domain can enter DSR mode only when all other domains are in DSR
1174  * mode. If the condition is false, the sense domain will be in a shallower power mode(Deep sleep mode).
1175  *
1176  * NOTE, the body bias and DCDC, LDO configurations in PMC_PDSLEECFG0 is not covered by this API, please use
1177  * @ref POWER_EnableSleepRBB or @ref POWER_EnableSleepNBB and @ref POWER_SelectSleepSetpoint for those settings.
1178  *
1179  * @param   exclude_from_pd  Bit mask of the SLEEPCON_SLEEPCFG and PMC_PDSLEEPCFG0 ~ PMC_PDSLEEPCFG5 that needs to be
1180  * powered on(bits cleared) during the power mode. The configuration for PMC from Compute domain and Sense domain are
1181  * aggregated, and the higher power mode always wins.
1182  */
1183 void POWER_RequestDSR(const uint32_t exclude_from_pd[7]);
1184 #endif
1185 /*!
1186  * @brief The domain requests to enter Deep Power Down mode.
1187  * The Deep Power Down and Full Deep Power Down can occur only when both domains signal their intent to enter these
1188  * lower power modes. The configuration for PMC from Compute domain and Sense domain are aggregated, and the higher
1189  * power mode always wins.
1190  *
1191  * @param exclude_from_pd  Bit mask of the SLEEPCON_SLEEPCFG and PMC_PDSLEEPCFG0 ~ PMC_PDSLEEPCFG5 that needs to be
1192  * powered on during Deep Power Down.
1193  */
1194 void POWER_RequestDeepPowerDown(const uint32_t exclude_from_pd[7]);
1195 
1196 /*!
1197  * @brief The domain requests to enter Full Deep Power Down mode.
1198  * The Deep Power Down and Full Deep Power Down can occur only when both domains signal their intent to enter these
1199  * lower power modes. The configuration for PMC from Compute domain and Sense domain are aggregated, and the higher
1200  * power mode always wins.
1201  *
1202  * @param   exclude_from_pd  Bit mask of the SLEEPCON_SLEEPCFG and PMC_PDSLEEPCFG0 ~ PMC_PDSLEEPCFG5 that needs to be
1203  * powered on during Deep Power Down.
1204  */
1205 void POWER_RequestFullDeepPowerDown(const uint32_t exclude_from_pd[7]);
1206 
1207 /*!
1208  * @brief Power Library API to request entering different power mode. This API is used for requesting entering the
1209  * target mode, the final SOC power mode depends on hardware aggregation. Note, the Sense domain can enter DSR mode only
1210  * when Compute domain is in DSR. The SOC enters DPD or FDPD when both domain requested entering DPD or FDPD.
1211  *
1212  * @param mode  Power mode to enter.
1213  * @param exclude_from_pd  Bit mask of the SLEEPCON_SLEEPCFG and PMC_PDSLEEPCFG0 ~ PMC_PDSLEEPCFG5 that needs to be
1214  * powered on during power mode selected.
1215  */
1216 void POWER_EnterPowerMode(power_mode_cfg_t mode, const uint32_t exclude_from_pd[7]);
1217 
1218 /*!
1219  * @brief Power Library API to return the library version.
1220  *
1221  * @return version number of the power library
1222  */
1223 uint32_t POWER_GetLibVersion(void);
1224 
1225 #ifdef __cplusplus
1226 }
1227 #endif
1228 
1229 /*!
1230  * @}
1231  */
1232 
1233 #endif /* FSL_POWER_H_ */
1234