1 /* 2 * Copyright 2024 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include "fsl_dsp.h" 9 #include "fsl_reset.h" 10 #include "fsl_common.h" 11 #include "fsl_power.h" 12 13 /******************************************************************************* 14 * Definitions 15 ******************************************************************************/ 16 17 /* Component ID definition, used by tools. */ 18 #ifndef FSL_COMPONENT_ID 19 #define FSL_COMPONENT_ID "platform.drivers.dsp" 20 #endif 21 22 /******************************************************************************* 23 * Variables 24 ******************************************************************************/ 25 26 /******************************************************************************* 27 * Prototypes 28 ******************************************************************************/ 29 #if defined(MIMXRT798S_cm33_core0_SERIES) 30 #define DSP_MEM_PD_MASKS \ 31 (PMC_PDRUNCFG4_DSP_DCACHE_MASK | PMC_PDRUNCFG4_DSP_ICACHE_MASK | PMC_PDRUNCFG4_DSP_DTCM_MASK | \ 32 PMC_PDRUNCFG4_DSP_ITCM_MASK) 33 #endif 34 /******************************************************************************* 35 * Code 36 ******************************************************************************/ 37 /*! 38 * @brief Initializing DSP core. 39 * 40 * Power up DSP TCM 41 * Enable DSP clock 42 * Reset DSP peripheral 43 */ DSP_Init(void)44void DSP_Init(void) 45 { 46 #if defined(MIMXRT798S_cm33_core0_SERIES) 47 /* Power on VDD2_DSP and HiFi4 RAM */ 48 if ((PMC0->PDRUNCFG4 & DSP_MEM_PD_MASKS) != 0U || (PMC0->PDRUNCFG5 & DSP_MEM_PD_MASKS) != 0U) 49 { 50 POWER_DisablePD(kPDRUNCFG_APD_DSP_DTCM); 51 POWER_DisablePD(kPDRUNCFG_APD_DSP_ITCM); 52 POWER_DisablePD(kPDRUNCFG_APD_DSP_DCACHE); 53 POWER_DisablePD(kPDRUNCFG_APD_DSP_ICACHE); 54 55 POWER_DisablePD(kPDRUNCFG_PPD_DSP_DTCM); 56 POWER_DisablePD(kPDRUNCFG_PPD_DSP_ITCM); 57 POWER_DisablePD(kPDRUNCFG_PPD_DSP_DCACHE); 58 POWER_DisablePD(kPDRUNCFG_PPD_DSP_ICACHE); 59 60 POWER_ApplyPD(); 61 62 RESET_PeripheralReset(kHIFI4_RST_SHIFT_RSTn); 63 RESET_PeripheralReset(kHIFI4_DEBUG_RST_SHIFT_RSTn); 64 } 65 else if ((RSTCTL0->PRSTCTL5 & RSTCTL0_PRSTCTL5_HIFI4_MASK) != 0U) /* Already power up. */ 66 { 67 RESET_ClearPeripheralReset(kHIFI4_RST_SHIFT_RSTn); 68 RESET_ClearPeripheralReset(kHIFI4_DEBUG_RST_SHIFT_RSTn); 69 } 70 else 71 { 72 /* Already powered on and reset, do nothing. */ 73 } 74 75 CLOCK_EnableClock(kCLOCK_Hifi4); 76 #elif defined(SLEEPCON1) 77 RESET_ClearPeripheralReset(kHIFI1_DEBUG_RST_SHIFT_RSTn); 78 RESET_ClearPeripheralReset(kHIFI1_RST_SHIFT_RSTn); 79 CLOCK_EnableClock(kCLOCK_Hifi1); 80 #else 81 #error "Unsupported core!" 82 #endif 83 } 84 85 /*! 86 * @brief Deinit DSP core. 87 * 88 * Power down DSP TCM 89 * Disable DSP clock 90 * Set DSP peripheral reset 91 */ DSP_Deinit(void)92void DSP_Deinit(void) 93 { 94 DSP_Stop(); 95 96 #if defined(MIMXRT798S_cm33_core0_SERIES) 97 CLOCK_DisableClock(kCLOCK_Hifi4); 98 99 POWER_EnablePD(kPDRUNCFG_APD_DSP_DTCM); 100 POWER_EnablePD(kPDRUNCFG_APD_DSP_ITCM); 101 POWER_EnablePD(kPDRUNCFG_APD_DSP_DCACHE); 102 POWER_EnablePD(kPDRUNCFG_APD_DSP_ICACHE); 103 104 POWER_EnablePD(kPDRUNCFG_PPD_DSP_DTCM); 105 POWER_EnablePD(kPDRUNCFG_PPD_DSP_ITCM); 106 POWER_EnablePD(kPDRUNCFG_PPD_DSP_DCACHE); 107 POWER_EnablePD(kPDRUNCFG_PPD_DSP_ICACHE); 108 109 POWER_ApplyPD(); 110 #elif defined(SLEEPCON1) 111 CLOCK_DisableClock(kCLOCK_Hifi1); 112 #endif 113 } 114 /*! 115 * @brief Copy DSP image to destination address. 116 * 117 * Copy DSP image from source address to destination address with given size. 118 * 119 * @param dspCopyImage Structure contains information for DSP copy image to destination address. 120 */ DSP_CopyImage(dsp_copy_image_t * dspCopyImage)121void DSP_CopyImage(dsp_copy_image_t *dspCopyImage) 122 { 123 assert(dspCopyImage != NULL); 124 assert(dspCopyImage->srcAddr != NULL); 125 assert(dspCopyImage->destAddr != NULL); 126 127 uint32_t *srcAddr = dspCopyImage->srcAddr; 128 uint32_t *destAddr = dspCopyImage->destAddr; 129 uint32_t size = dspCopyImage->size; 130 131 assert((size & 3U) == 0U); 132 133 while (size > 0U) 134 { 135 *destAddr++ = *srcAddr++; 136 size -= 4U; 137 } 138 } 139