1/* This linker script generated from xt-genldscripts.tpp for LSP gdbio */ 2/* Linker Script for ld -N */ 3MEMORY 4{ 5 iram0_0_seg : org = 0x00500000, len = 0x80000 6 iram0_1_seg : org = 0x00580000, len = 0x2E0 7 iram0_3_seg : org = 0x00580400, len = 0x178 8 iram0_4_seg : org = 0x00580578, len = 0x4 9 iram0_5_seg : org = 0x0058057C, len = 0x1C 10 iram0_6_seg : org = 0x00580598, len = 0x4 11 iram0_7_seg : org = 0x0058059C, len = 0x1C 12 iram0_8_seg : org = 0x005805B8, len = 0x4 13 iram0_9_seg : org = 0x005805BC, len = 0x1C 14 iram0_10_seg : org = 0x005805D8, len = 0x4 15 iram0_11_seg : org = 0x005805DC, len = 0x1C 16 iram0_12_seg : org = 0x005805F8, len = 0x4 17 iram0_13_seg : org = 0x005805FC, len = 0x1C 18 iram0_14_seg : org = 0x00580618, len = 0x4 19 iram0_15_seg : org = 0x0058061C, len = 0x1C 20 iram0_16_seg : org = 0x00580638, len = 0x4 21 iram0_17_seg : org = 0x0058063C, len = 0x1C 22 iram1_0_seg : org = 0x00600000, len = 0x200000 23 sram0_seg : org = 0x20000000, len = 0x500000 24 dram0_0_seg : org = 0x20500000, len = 0x100000 25 dram1_0_seg : org = 0x20600000, len = 0x200000 26} 27 28PHDRS 29{ 30 iram0_0_phdr PT_LOAD; 31 iram0_1_phdr PT_LOAD; 32 iram0_2_phdr PT_LOAD; 33 iram0_3_phdr PT_LOAD; 34 iram0_4_phdr PT_LOAD; 35 iram0_5_phdr PT_LOAD; 36 iram0_6_phdr PT_LOAD; 37 iram0_7_phdr PT_LOAD; 38 iram0_8_phdr PT_LOAD; 39 iram0_9_phdr PT_LOAD; 40 iram0_10_phdr PT_LOAD; 41 iram0_11_phdr PT_LOAD; 42 iram0_12_phdr PT_LOAD; 43 iram0_13_phdr PT_LOAD; 44 iram0_14_phdr PT_LOAD; 45 iram0_15_phdr PT_LOAD; 46 iram0_16_phdr PT_LOAD; 47 iram0_17_phdr PT_LOAD; 48 iram0_18_phdr PT_LOAD; 49 iram1_0_phdr PT_LOAD; 50 sram0_phdr PT_LOAD; 51 sram0_bss_phdr PT_LOAD; 52 dram0_0_phdr PT_LOAD; 53 dram0_0_bss_phdr PT_LOAD; 54 dram1_0_phdr PT_LOAD; 55 dram1_0_bss_phdr PT_LOAD; 56} 57 58 59/* Default entry point: */ 60ENTRY(_ResetVector) 61 62 63/* Memory boundary addresses: */ 64_memmap_mem_iram0_start = 0x500000; 65_memmap_mem_iram0_end = 0x600000; 66_memmap_mem_iram1_start = 0x600000; 67_memmap_mem_iram1_end = 0x800000; 68_memmap_mem_sram_start = 0x20000000; 69_memmap_mem_sram_end = 0x20500000; 70_memmap_mem_dram0_start = 0x20500000; 71_memmap_mem_dram0_end = 0x20600000; 72_memmap_mem_dram1_start = 0x20600000; 73_memmap_mem_dram1_end = 0x20800000; 74 75/* Memory segment boundary addresses: */ 76_memmap_seg_iram0_0_start = 0x500000; 77_memmap_seg_iram0_0_max = 0x580000; 78_memmap_seg_iram0_1_start = 0x580000; 79_memmap_seg_iram0_1_max = 0x5802e0; 80_memmap_seg_iram0_3_start = 0x580400; 81_memmap_seg_iram0_3_max = 0x580578; 82_memmap_seg_iram0_4_start = 0x580578; 83_memmap_seg_iram0_4_max = 0x58057c; 84_memmap_seg_iram0_5_start = 0x58057c; 85_memmap_seg_iram0_5_max = 0x580598; 86_memmap_seg_iram0_6_start = 0x580598; 87_memmap_seg_iram0_6_max = 0x58059c; 88_memmap_seg_iram0_7_start = 0x58059c; 89_memmap_seg_iram0_7_max = 0x5805b8; 90_memmap_seg_iram0_8_start = 0x5805b8; 91_memmap_seg_iram0_8_max = 0x5805bc; 92_memmap_seg_iram0_9_start = 0x5805bc; 93_memmap_seg_iram0_9_max = 0x5805d8; 94_memmap_seg_iram0_10_start = 0x5805d8; 95_memmap_seg_iram0_10_max = 0x5805dc; 96_memmap_seg_iram0_11_start = 0x5805dc; 97_memmap_seg_iram0_11_max = 0x5805f8; 98_memmap_seg_iram0_12_start = 0x5805f8; 99_memmap_seg_iram0_12_max = 0x5805fc; 100_memmap_seg_iram0_13_start = 0x5805fc; 101_memmap_seg_iram0_13_max = 0x580618; 102_memmap_seg_iram0_14_start = 0x580618; 103_memmap_seg_iram0_14_max = 0x58061c; 104_memmap_seg_iram0_15_start = 0x58061c; 105_memmap_seg_iram0_15_max = 0x580638; 106_memmap_seg_iram0_16_start = 0x580638; 107_memmap_seg_iram0_16_max = 0x58063c; 108_memmap_seg_iram0_17_start = 0x58063c; 109_memmap_seg_iram0_17_max = 0x580658; 110_memmap_seg_iram1_0_start = 0x600000; 111_memmap_seg_iram1_0_max = 0x800000; 112_memmap_seg_sram0_start = 0x20000000; 113_memmap_seg_sram0_max = 0x20500000; 114_memmap_seg_dram0_0_start = 0x20500000; 115_memmap_seg_dram0_0_max = 0x20600000; 116_memmap_seg_dram1_0_start = 0x20600000; 117_memmap_seg_dram1_0_max = 0x20800000; 118 119_rom_store_table = 0; 120PROVIDE(_memmap_reset_vector = 0x580000); 121PROVIDE(_memmap_vecbase_reset = 0x580400); 122/* Various memory-map dependent cache attribute settings: */ 123_memmap_cacheattr_wb_base = 0x00021012; 124_memmap_cacheattr_wt_base = 0x00021012; 125_memmap_cacheattr_bp_base = 0x00022022; 126_memmap_cacheattr_unused_mask = 0xFFF00F00; 127_memmap_cacheattr_wb_trapnull = 0x22221212; 128_memmap_cacheattr_wba_trapnull = 0x22221212; 129_memmap_cacheattr_wbna_trapnull = 0x22221212; 130_memmap_cacheattr_wt_trapnull = 0x22221212; 131_memmap_cacheattr_bp_trapnull = 0x22222222; 132_memmap_cacheattr_wb_strict = 0xFFF21F12; 133_memmap_cacheattr_wt_strict = 0xFFF21F12; 134_memmap_cacheattr_bp_strict = 0xFFF22F22; 135_memmap_cacheattr_wb_allvalid = 0x22221212; 136_memmap_cacheattr_wt_allvalid = 0x22221212; 137_memmap_cacheattr_bp_allvalid = 0x22222222; 138_memmap_region_map = 0x0000001B; 139PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 140 141SECTIONS 142{ 143 144 .iram0.text : ALIGN(4) 145 { 146 _iram0_text_start = ABSOLUTE(.); 147 *(.iram0.literal .iram0.text) 148 . = ALIGN (4); 149 _iram0_text_end = ABSOLUTE(.); 150 _memmap_seg_iram0_0_end = ALIGN(0x8); 151 } >iram0_0_seg :iram0_0_phdr 152 153 154 .ResetVector.text : ALIGN(4) 155 { 156 _ResetVector_text_start = ABSOLUTE(.); 157 KEEP (*(.ResetVector.text)) 158 . = ALIGN (4); 159 _ResetVector_text_end = ABSOLUTE(.); 160 } >iram0_1_seg :iram0_1_phdr 161 162 .ResetHandler.text : ALIGN(4) 163 { 164 _ResetHandler_text_start = ABSOLUTE(.); 165 *(.ResetHandler.literal .ResetHandler.text) 166 . = ALIGN (4); 167 _ResetHandler_text_end = ABSOLUTE(.); 168 _memmap_seg_iram0_1_end = ALIGN(0x8); 169 } >iram0_1_seg :iram0_1_phdr 170 171 172 173 .WindowVectors.text : ALIGN(4) 174 { 175 _WindowVectors_text_start = ABSOLUTE(.); 176 KEEP (*(.WindowVectors.text)) 177 . = ALIGN (4); 178 _WindowVectors_text_end = ABSOLUTE(.); 179 _memmap_seg_iram0_3_end = ALIGN(0x8); 180 } >iram0_3_seg :iram0_3_phdr 181 182 183 .Level2InterruptVector.literal : ALIGN(4) 184 { 185 _Level2InterruptVector_literal_start = ABSOLUTE(.); 186 *(.Level2InterruptVector.literal) 187 . = ALIGN (4); 188 _Level2InterruptVector_literal_end = ABSOLUTE(.); 189 _memmap_seg_iram0_4_end = ALIGN(0x8); 190 } >iram0_4_seg :iram0_4_phdr 191 192 193 .Level2InterruptVector.text : ALIGN(4) 194 { 195 _Level2InterruptVector_text_start = ABSOLUTE(.); 196 KEEP (*(.Level2InterruptVector.text)) 197 . = ALIGN (4); 198 _Level2InterruptVector_text_end = ABSOLUTE(.); 199 _memmap_seg_iram0_5_end = ALIGN(0x8); 200 } >iram0_5_seg :iram0_5_phdr 201 202 203 .Level3InterruptVector.literal : ALIGN(4) 204 { 205 _Level3InterruptVector_literal_start = ABSOLUTE(.); 206 *(.Level3InterruptVector.literal) 207 . = ALIGN (4); 208 _Level3InterruptVector_literal_end = ABSOLUTE(.); 209 _memmap_seg_iram0_6_end = ALIGN(0x8); 210 } >iram0_6_seg :iram0_6_phdr 211 212 213 .Level3InterruptVector.text : ALIGN(4) 214 { 215 _Level3InterruptVector_text_start = ABSOLUTE(.); 216 KEEP (*(.Level3InterruptVector.text)) 217 . = ALIGN (4); 218 _Level3InterruptVector_text_end = ABSOLUTE(.); 219 _memmap_seg_iram0_7_end = ALIGN(0x8); 220 } >iram0_7_seg :iram0_7_phdr 221 222 223 .DebugExceptionVector.literal : ALIGN(4) 224 { 225 _DebugExceptionVector_literal_start = ABSOLUTE(.); 226 *(.DebugExceptionVector.literal) 227 . = ALIGN (4); 228 _DebugExceptionVector_literal_end = ABSOLUTE(.); 229 _memmap_seg_iram0_8_end = ALIGN(0x8); 230 } >iram0_8_seg :iram0_8_phdr 231 232 233 .DebugExceptionVector.text : ALIGN(4) 234 { 235 _DebugExceptionVector_text_start = ABSOLUTE(.); 236 KEEP (*(.DebugExceptionVector.text)) 237 . = ALIGN (4); 238 _DebugExceptionVector_text_end = ABSOLUTE(.); 239 _memmap_seg_iram0_9_end = ALIGN(0x8); 240 } >iram0_9_seg :iram0_9_phdr 241 242 243 .NMIExceptionVector.literal : ALIGN(4) 244 { 245 _NMIExceptionVector_literal_start = ABSOLUTE(.); 246 *(.NMIExceptionVector.literal) 247 . = ALIGN (4); 248 _NMIExceptionVector_literal_end = ABSOLUTE(.); 249 _memmap_seg_iram0_10_end = ALIGN(0x8); 250 } >iram0_10_seg :iram0_10_phdr 251 252 253 .NMIExceptionVector.text : ALIGN(4) 254 { 255 _NMIExceptionVector_text_start = ABSOLUTE(.); 256 KEEP (*(.NMIExceptionVector.text)) 257 . = ALIGN (4); 258 _NMIExceptionVector_text_end = ABSOLUTE(.); 259 _memmap_seg_iram0_11_end = ALIGN(0x8); 260 } >iram0_11_seg :iram0_11_phdr 261 262 263 .KernelExceptionVector.literal : ALIGN(4) 264 { 265 _KernelExceptionVector_literal_start = ABSOLUTE(.); 266 *(.KernelExceptionVector.literal) 267 . = ALIGN (4); 268 _KernelExceptionVector_literal_end = ABSOLUTE(.); 269 _memmap_seg_iram0_12_end = ALIGN(0x8); 270 } >iram0_12_seg :iram0_12_phdr 271 272 273 .KernelExceptionVector.text : ALIGN(4) 274 { 275 _KernelExceptionVector_text_start = ABSOLUTE(.); 276 KEEP (*(.KernelExceptionVector.text)) 277 . = ALIGN (4); 278 _KernelExceptionVector_text_end = ABSOLUTE(.); 279 _memmap_seg_iram0_13_end = ALIGN(0x8); 280 } >iram0_13_seg :iram0_13_phdr 281 282 283 .UserExceptionVector.literal : ALIGN(4) 284 { 285 _UserExceptionVector_literal_start = ABSOLUTE(.); 286 *(.UserExceptionVector.literal) 287 . = ALIGN (4); 288 _UserExceptionVector_literal_end = ABSOLUTE(.); 289 _memmap_seg_iram0_14_end = ALIGN(0x8); 290 } >iram0_14_seg :iram0_14_phdr 291 292 293 .UserExceptionVector.text : ALIGN(4) 294 { 295 _UserExceptionVector_text_start = ABSOLUTE(.); 296 KEEP (*(.UserExceptionVector.text)) 297 . = ALIGN (4); 298 _UserExceptionVector_text_end = ABSOLUTE(.); 299 _memmap_seg_iram0_15_end = ALIGN(0x8); 300 } >iram0_15_seg :iram0_15_phdr 301 302 303 .DoubleExceptionVector.literal : ALIGN(4) 304 { 305 _DoubleExceptionVector_literal_start = ABSOLUTE(.); 306 *(.DoubleExceptionVector.literal) 307 . = ALIGN (4); 308 _DoubleExceptionVector_literal_end = ABSOLUTE(.); 309 _memmap_seg_iram0_16_end = ALIGN(0x8); 310 } >iram0_16_seg :iram0_16_phdr 311 312 313 .DoubleExceptionVector.text : ALIGN(4) 314 { 315 _DoubleExceptionVector_text_start = ABSOLUTE(.); 316 KEEP (*(.DoubleExceptionVector.text)) 317 . = ALIGN (4); 318 _DoubleExceptionVector_text_end = ABSOLUTE(.); 319 _memmap_seg_iram0_17_end = ALIGN(0x8); 320 } >iram0_17_seg :iram0_17_phdr 321 322 323 _memmap_mem_iram0_max = ABSOLUTE(.); 324 325 .iram1.text : ALIGN(4) 326 { 327 _iram1_text_start = ABSOLUTE(.); 328 *(.iram1.literal .iram1.text) 329 . = ALIGN (4); 330 _iram1_text_end = ABSOLUTE(.); 331 _memmap_seg_iram1_0_end = ALIGN(0x8); 332 } >iram1_0_seg :iram1_0_phdr 333 334 _memmap_mem_iram1_max = ABSOLUTE(.); 335 336 .sram.rodata : ALIGN(4) 337 { 338 _sram_rodata_start = ABSOLUTE(.); 339 *(.sram.rodata) 340 . = ALIGN (4); 341 _sram_rodata_end = ABSOLUTE(.); 342 } >sram0_seg :sram0_phdr 343 344 .clib.rodata : ALIGN(4) 345 { 346 _clib_rodata_start = ABSOLUTE(.); 347 *(.clib.rodata) 348 . = ALIGN (4); 349 _clib_rodata_end = ABSOLUTE(.); 350 } >sram0_seg :sram0_phdr 351 352 .rtos.rodata : ALIGN(4) 353 { 354 _rtos_rodata_start = ABSOLUTE(.); 355 *(.rtos.rodata) 356 . = ALIGN (4); 357 _rtos_rodata_end = ABSOLUTE(.); 358 } >sram0_seg :sram0_phdr 359 360 .rodata : ALIGN(4) 361 { 362 _rodata_start = ABSOLUTE(.); 363 *(.rodata) 364 *(SORT(.rodata.sort.*)) 365 KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*)) 366 *(.rodata.*) 367 *(.gnu.linkonce.r.*) 368 *(.rodata1) 369 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); 370 KEEP (*(.xt_except_table)) 371 KEEP (*(.gcc_except_table)) 372 *(.gnu.linkonce.e.*) 373 *(.gnu.version_r) 374 PROVIDE (__eh_frame_start = .); 375 KEEP (*(.eh_frame)) 376 PROVIDE (__eh_frame_end = .); 377 /* C++ constructor and destructor tables, properly ordered: */ 378 KEEP (*crtbegin.o(.ctors)) 379 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 380 KEEP (*(SORT(.ctors.*))) 381 KEEP (*(.ctors)) 382 KEEP (*crtbegin.o(.dtors)) 383 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 384 KEEP (*(SORT(.dtors.*))) 385 KEEP (*(.dtors)) 386 /* C++ exception handlers table: */ 387 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 388 *(.xt_except_desc) 389 *(.gnu.linkonce.h.*) 390 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); 391 *(.xt_except_desc_end) 392 *(.dynamic) 393 *(.gnu.version_d) 394 . = ALIGN(4); /* this table MUST be 4-byte aligned */ 395 _bss_table_start = ABSOLUTE(.); 396 LONG(_bss_start) 397 LONG(_bss_end) 398 LONG(_dram0_bss_start) 399 LONG(_dram0_bss_end) 400 LONG(_dram1_bss_start) 401 LONG(_dram1_bss_end) 402 _bss_table_end = ABSOLUTE(.); 403 . = ALIGN (4); 404 _rodata_end = ABSOLUTE(.); 405 } >sram0_seg :sram0_phdr 406 407 .sram.text : ALIGN(4) 408 { 409 _sram_text_start = ABSOLUTE(.); 410 *(.sram.literal .sram.text) 411 . = ALIGN (4); 412 _sram_text_end = ABSOLUTE(.); 413 } >sram0_seg :sram0_phdr 414 415 .text : ALIGN(4) 416 { 417 _stext = .; 418 _text_start = ABSOLUTE(.); 419 *(.entry.text) 420 *(.init.literal) 421 KEEP(*(.init)) 422 *(.literal.sort.* SORT(.text.sort.*)) 423 KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*)) 424 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 425 *(.fini.literal) 426 KEEP(*(.fini)) 427 *(.gnu.version) 428 . = ALIGN (4); 429 _text_end = ABSOLUTE(.); 430 _etext = .; 431 } >sram0_seg :sram0_phdr 432 433 .clib.text : ALIGN(4) 434 { 435 _clib_text_start = ABSOLUTE(.); 436 *(.clib.literal .clib.text) 437 . = ALIGN (4); 438 _clib_text_end = ABSOLUTE(.); 439 } >sram0_seg :sram0_phdr 440 441 .rtos.text : ALIGN(4) 442 { 443 _rtos_text_start = ABSOLUTE(.); 444 *(.rtos.literal .rtos.text) 445 . = ALIGN (4); 446 _rtos_text_end = ABSOLUTE(.); 447 } >sram0_seg :sram0_phdr 448 449 .clib.data : ALIGN(4) 450 { 451 _clib_data_start = ABSOLUTE(.); 452 *(.clib.data) 453 . = ALIGN (4); 454 _clib_data_end = ABSOLUTE(.); 455 } >sram0_seg :sram0_phdr 456 457 .clib.percpu.data : ALIGN(4) 458 { 459 _clib_percpu_data_start = ABSOLUTE(.); 460 *(.clib.percpu.data) 461 . = ALIGN (4); 462 _clib_percpu_data_end = ABSOLUTE(.); 463 } >sram0_seg :sram0_phdr 464 465 .rtos.percpu.data : ALIGN(4) 466 { 467 _rtos_percpu_data_start = ABSOLUTE(.); 468 *(.rtos.percpu.data) 469 . = ALIGN (4); 470 _rtos_percpu_data_end = ABSOLUTE(.); 471 } >sram0_seg :sram0_phdr 472 473 .rtos.data : ALIGN(4) 474 { 475 _rtos_data_start = ABSOLUTE(.); 476 *(.rtos.data) 477 . = ALIGN (4); 478 _rtos_data_end = ABSOLUTE(.); 479 } >sram0_seg :sram0_phdr 480 481 .sram.data : ALIGN(4) 482 { 483 _sram_data_start = ABSOLUTE(.); 484 *(.sram.data) 485 . = ALIGN (4); 486 _sram_data_end = ABSOLUTE(.); 487 } >sram0_seg :sram0_phdr 488 489 .data : ALIGN(4) 490 { 491 _data_start = ABSOLUTE(.); 492 *(.data) 493 *(SORT(.data.sort.*)) 494 KEEP (*(SORT(.data.keepsort.*) .data.keep.*)) 495 *(.data.*) 496 *(.gnu.linkonce.d.*) 497 KEEP(*(.gnu.linkonce.d.*personality*)) 498 *(.data1) 499 *(.sdata) 500 *(.sdata.*) 501 *(.gnu.linkonce.s.*) 502 *(.sdata2) 503 *(.sdata2.*) 504 *(.gnu.linkonce.s2.*) 505 KEEP(*(.jcr)) 506 *(__llvm_prf_cnts) 507 *(__llvm_prf_data) 508 *(__llvm_prf_vnds) 509 . = ALIGN (4); 510 _data_end = ABSOLUTE(.); 511 } >sram0_seg :sram0_phdr 512 513 __llvm_prf_names : ALIGN(4) 514 { 515 __llvm_prf_names_start = ABSOLUTE(.); 516 *(__llvm_prf_names) 517 . = ALIGN (4); 518 __llvm_prf_names_end = ABSOLUTE(.); 519 } >sram0_seg :sram0_phdr 520 521 __llvm_covmap : ALIGN(4) 522 { 523 __llvm_covmap_start = ABSOLUTE(.); 524 *(__llvm_covmap) 525 . = ALIGN (4); 526 __llvm_covmap_end = ABSOLUTE(.); 527 } >sram0_seg :sram0_phdr 528 529 .note.gnu.build-id : ALIGN(4) 530 { 531 _note_gnu_build-id_start = ABSOLUTE(.); 532 *(.note.gnu.build-id) 533 . = ALIGN (4); 534 _note_gnu_build-id_end = ABSOLUTE(.); 535 } >sram0_seg :sram0_phdr 536 537 .bss (NOLOAD) : ALIGN(8) 538 { 539 . = ALIGN (8); 540 _bss_start = ABSOLUTE(.); 541 *(.dynsbss) 542 *(.sbss) 543 *(.sbss.*) 544 *(.gnu.linkonce.sb.*) 545 *(.scommon) 546 *(.sbss2) 547 *(.sbss2.*) 548 *(.gnu.linkonce.sb2.*) 549 *(.dynbss) 550 *(.bss) 551 *(SORT(.bss.sort.*)) 552 KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*)) 553 *(.bss.*) 554 *(.gnu.linkonce.b.*) 555 *(COMMON) 556 *(.clib.bss) 557 *(.clib.percpu.bss) 558 *(.rtos.percpu.bss) 559 *(.rtos.bss) 560 *(.sram.bss) 561 . = ALIGN (8); 562 _bss_end = ABSOLUTE(.); 563 _end = ALIGN(0x8); 564 PROVIDE(end = ALIGN(0x8)); 565 _stack_sentry = ALIGN(0x8); 566 _memmap_seg_sram0_end = ALIGN(0x8); 567 } >sram0_seg :sram0_bss_phdr 568 569 PROVIDE(__stack = 0x20500000); 570 _heap_sentry = 0x20500000; 571 _memmap_mem_sram_max = ABSOLUTE(.); 572 573 .dram0.rodata : ALIGN(4) 574 { 575 _dram0_rodata_start = ABSOLUTE(.); 576 *(.dram0.rodata) 577 . = ALIGN (4); 578 _dram0_rodata_end = ABSOLUTE(.); 579 } >dram0_0_seg :dram0_0_phdr 580 581 .dram0.data : ALIGN(4) 582 { 583 _dram0_data_start = ABSOLUTE(.); 584 *(.dram0.data) 585 . = ALIGN (4); 586 _dram0_data_end = ABSOLUTE(.); 587 } >dram0_0_seg :dram0_0_phdr 588 589 .dram0.bss (NOLOAD) : ALIGN(8) 590 { 591 . = ALIGN (8); 592 _dram0_bss_start = ABSOLUTE(.); 593 *(.dram0.bss) 594 . = ALIGN (8); 595 _dram0_bss_end = ABSOLUTE(.); 596 _memmap_seg_dram0_0_end = ALIGN(0x8); 597 } >dram0_0_seg :dram0_0_bss_phdr 598 599 _memmap_mem_dram0_max = ABSOLUTE(.); 600 601 .dram1.rodata : ALIGN(4) 602 { 603 _dram1_rodata_start = ABSOLUTE(.); 604 *(.dram1.rodata) 605 . = ALIGN (4); 606 _dram1_rodata_end = ABSOLUTE(.); 607 } >dram1_0_seg :dram1_0_phdr 608 609 .dram1.data : ALIGN(4) 610 { 611 _dram1_data_start = ABSOLUTE(.); 612 *(.dram1.data) 613 . = ALIGN (4); 614 _dram1_data_end = ABSOLUTE(.); 615 } >dram1_0_seg :dram1_0_phdr 616 617 .dram1.bss (NOLOAD) : ALIGN(8) 618 { 619 . = ALIGN (8); 620 _dram1_bss_start = ABSOLUTE(.); 621 *(.dram1.bss) 622 . = ALIGN (8); 623 _dram1_bss_end = ABSOLUTE(.); 624 _memmap_seg_dram1_0_end = ALIGN(0x8); 625 } >dram1_0_seg :dram1_0_bss_phdr 626 627 628 _memmap_mem_dram1_max = ABSOLUTE(.); 629 630 .debug 0 : { *(.debug) } 631 .line 0 : { *(.line) } 632 .debug_srcinfo 0 : { *(.debug_srcinfo) } 633 .debug_sfnames 0 : { *(.debug_sfnames) } 634 .debug_aranges 0 : { *(.debug_aranges) } 635 .debug_ranges 0 : { *(.debug_ranges) } 636 .debug_pubnames 0 : { *(.debug_pubnames) } 637 .debug_info 0 : { *(.debug_info) } 638 .debug_abbrev 0 : { *(.debug_abbrev) } 639 .debug_line 0 : { *(.debug_line) } 640 .debug_frame 0 : { *(.debug_frame) } 641 .debug_str 0 : { *(.debug_str) } 642 .debug_loc 0 : { *(.debug_loc) } 643 .debug_macinfo 0 : { *(.debug_macinfo) } 644 .debug_weaknames 0 : { *(.debug_weaknames) } 645 .debug_funcnames 0 : { *(.debug_funcnames) } 646 .debug_typenames 0 : { *(.debug_typenames) } 647 .debug_varnames 0 : { *(.debug_varnames) } 648 .debug.xt.map 0 : { *(.debug.xt.map) } 649 .xt.insn 0 : 650 { 651 KEEP (*(.xt.insn)) 652 KEEP (*(.gnu.linkonce.x.*)) 653 } 654 .xt.prop 0 : 655 { 656 *(.xt.prop) 657 *(.xt.prop.*) 658 *(.gnu.linkonce.prop.*) 659 } 660 .xt.lit 0 : 661 { 662 *(.xt.lit) 663 *(.xt.lit.*) 664 *(.gnu.linkonce.p.*) 665 } 666 .xtensa.info 0 : 667 { 668 *(.xtensa.info) 669 } 670 .debug.xt.callgraph 0 : 671 { 672 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) 673 } 674 .comment 0 : 675 { 676 KEEP(*(.comment)) 677 } 678 .note.GNU-stack 0 : 679 { 680 *(.note.GNU-stack) 681 } 682} 683 684
