1 /*
2  * Copyright 2023-2024 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_INPUTMUX_CONNECTIONS_
9 #define _FSL_INPUTMUX_CONNECTIONS_
10 
11 #include "fsl_device_registers.h"
12 /*******************************************************************************
13  * Definitions
14  ******************************************************************************/
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
18 #endif
19 
20 /*!
21  * @addtogroup inputmux_driver
22  * @{
23  */
24 
25 /*! @brief Periphinmux IDs */
26 #define PINTSEL_PMUX_ID 0x100U
27 #define DSP_INT_PMUX_ID 0x140U
28 
29 #if defined(INPUTMUX0)
30 #define SCT0_PMUX_ID             0x00U
31 #define FLEXCOMM0_ITRIG_PMUX_ID  0x200U
32 #define FLEXCOMM1_ITRIG_PMUX_ID  0x220U
33 #define FLEXCOMM2_ITRIG_PMUX_ID  0x240U
34 #define FLEXCOMM3_ITRIG_PMUX_ID  0x260U
35 #define FLEXCOMM4_ITRIG_PMUX_ID  0x280U
36 #define FLEXCOMM5_ITRIG_PMUX_ID  0x2A0U
37 #define FLEXCOMM6_ITRIG_PMUX_ID  0x2C0U
38 #define FLEXCOMM7_ITRIG_PMUX_ID  0x2E0U
39 #define FLEXCOMM8_ITRIG_PMUX_ID  0x300U
40 #define FLEXCOMM9_ITRIG_PMUX_ID  0x320U
41 #define FLEXCOMM10_ITRIG_PMUX_ID 0x340U
42 #define FLEXCOMM11_ITRIG_PMUX_ID 0x360U
43 #define FLEXCOMM12_ITRIG_PMUX_ID 0x380U
44 #define FLEXCOMM13_ITRIG_PMUX_ID 0x3A0U
45 #define CT32BIT0_CAP_PMUX_ID     0x600U
46 #define CT32BIT1_CAP_PMUX_ID     0x620U
47 #define CT32BIT2_CAP_PMUX_ID     0x640U
48 #define CT32BIT3_CAP_PMUX_ID     0x660U
49 #define CT32BIT4_CAP_PMUX_ID     0x680U
50 #define CT32BIT0_TRIG_PMUX_ID    0x610U
51 #define CT32BIT1_TRIG_PMUX_ID    0x630U
52 #define CT32BIT2_TRIG_PMUX_ID    0x650U
53 #define CT32BIT3_TRIG_PMUX_ID    0x670U
54 #define CT32BIT4_TRIG_PMUX_ID    0x690U
55 #define FREQME_REF_PMUX_ID       0x700U
56 #define FREQME_TAR_PMUX_ID       0x704U
57 #define EZHV_PMUX_ID             0x720U
58 #define FLEXIO_PMUX_ID           0x760U
59 #elif defined(INPUTMUX1)
60 #define FLEXCOMM17_ITRIG_PMUX_ID 0x200U
61 #define FLEXCOMM18_ITRIG_PMUX_ID 0x220U
62 #define FLEXCOMM19_ITRIG_PMUX_ID 0x240U
63 #define FLEXCOMM20_ITRIG_PMUX_ID 0x260U
64 #define ADC0_TRIG_PMUX_ID        0x400U
65 #define CT32BIT5_CAP_PMUX_ID     0x600U
66 #define CT32BIT6_CAP_PMUX_ID     0x620U
67 #define CT32BIT7_CAP_PMUX_ID     0x640U
68 #define CT32BIT5_TRIG_PMUX_ID    0x610U
69 #define CT32BIT6_TRIG_PMUX_ID    0x630U
70 #define CT32BIT7_TRIG_PMUX_ID    0x650U
71 
72 #else
73 #error "Unsupported core!"
74 #endif
75 
76 #define PMUX_SHIFT 20U
77 
78 /*! @brief INPUTMUX connections type */
79 typedef enum _inputmux_connection_t
80 {
81 #if defined(INPUTMUX0)
82     /*!< SCT INMUX. */
83     kINPUTMUX_Sct0PinInp0ToSct0   = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
84     kINPUTMUX_Sct0PinInp1ToSct0   = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
85     kINPUTMUX_Sct0PinInp2ToSct0   = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
86     kINPUTMUX_Sct0PinInp3ToSct0   = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
87     kINPUTMUX_Sct0PinInp4ToSct0   = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
88     kINPUTMUX_Sct0PinInp5ToSct0   = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
89     kINPUTMUX_Sct0PinInp6ToSct0   = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
90     kINPUTMUX_Sct0PinInp7ToSct0   = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
91     kINPUTMUX_Ctimer0Mat0ToSct0   = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
92     kINPUTMUX_Ctimer1Mat0ToSct0   = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
93     kINPUTMUX_Ctimer2Mat0ToSct0   = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
94     kINPUTMUX_Ctimer3Mat0ToSct0   = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
95     kINPUTMUX_Ctimer4Mat0ToSct0   = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
96     kINPUTMUX_Usb1SofToSct0       = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
97     kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
98     kINPUTMUX_Usb0SofToSct0       = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
99     kINPUTMUX_Cmp0OutToSct0       = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
100     kINPUTMUX_Sai0TxBclkToSct0    = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
101     kINPUTMUX_Sai0RxBclkToSct0    = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
102     kINPUTMUX_Sai1TxBclkToSct0    = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
103     kINPUTMUX_Sai1RxBclkToSct0    = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
104     kINPUTMUX_Sai2TxBclkToSct0    = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
105     kINPUTMUX_Sai2RxBclkToSct0    = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
106     kINPUTMUX_MclkToSct0          = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
107     kINPUTMUX_Cpu0TxevToSct0      = 24U + (SCT0_PMUX_ID << PMUX_SHIFT),
108     kINPUTMUX_DebugHaltedToSct0   = 25U + (SCT0_PMUX_ID << PMUX_SHIFT),
109     kINPUTMUX_Adc0Tcomp0ToSct0    = 26U + (SCT0_PMUX_ID << PMUX_SHIFT),
110     kINPUTMUX_Adc0Tcomp1ToSct0    = 27U + (SCT0_PMUX_ID << PMUX_SHIFT),
111 
112     /*!< Pin Interrupt. */
113     kINPUTMUX_GpioPort0Pin0ToPintsel  = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
114     kINPUTMUX_GpioPort0Pin1ToPintsel  = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
115     kINPUTMUX_GpioPort0Pin2ToPintsel  = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
116     kINPUTMUX_GpioPort0Pin3ToPintsel  = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
117     kINPUTMUX_GpioPort0Pin4ToPintsel  = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
118     kINPUTMUX_GpioPort0Pin5ToPintsel  = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
119     kINPUTMUX_GpioPort0Pin6ToPintsel  = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
120     kINPUTMUX_GpioPort0Pin7ToPintsel  = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
121     kINPUTMUX_GpioPort0Pin8ToPintsel  = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
122     kINPUTMUX_GpioPort0Pin9ToPintsel  = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
123     kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
124     kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
125     kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
126     kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
127     kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
128     kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
129     kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
130     kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
131     kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
132     kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
133     kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
134     kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
135     kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
136     kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
137     kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
138     kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
139     kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
140     kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
141     kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
142     kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
143     kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
144     kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
145     kINPUTMUX_GpioPort1Pin0ToPintsel  = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
146     kINPUTMUX_GpioPort1Pin1ToPintsel  = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
147     kINPUTMUX_GpioPort1Pin2ToPintsel  = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
148     kINPUTMUX_GpioPort1Pin3ToPintsel  = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
149     kINPUTMUX_GpioPort1Pin4ToPintsel  = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
150     kINPUTMUX_GpioPort1Pin5ToPintsel  = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
151     kINPUTMUX_GpioPort1Pin6ToPintsel  = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
152     kINPUTMUX_GpioPort1Pin7ToPintsel  = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
153     kINPUTMUX_GpioPort1Pin8ToPintsel  = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
154     kINPUTMUX_GpioPort1Pin9ToPintsel  = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
155     kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
156     kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
157     kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
158     kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
159     kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
160     kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
161     kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
162     kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
163     kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
164     kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
165 
166     /*!< DSP Interrupt. */
167     kINPUTMUX_Flexcomm0ToDspInterrupt    = 0U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
168     kINPUTMUX_Flexcomm1ToDspInterrupt    = 1U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
169     kINPUTMUX_Flexcomm2ToDspInterrupt    = 2U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
170     kINPUTMUX_Flexcomm3ToDspInterrupt    = 3U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
171     kINPUTMUX_Flexcomm4ToDspInterrupt    = 4U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
172     kINPUTMUX_Flexcomm5ToDspInterrupt    = 5U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
173     kINPUTMUX_Flexcomm6ToDspInterrupt    = 6U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
174     kINPUTMUX_Flexcomm7ToDspInterrupt    = 7U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
175     kINPUTMUX_Flexcomm8ToDspInterrupt    = 8U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
176     kINPUTMUX_Flexcomm9ToDspInterrupt    = 9U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
177     kINPUTMUX_Flexcomm10ToDspInterrupt   = 10U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
178     kINPUTMUX_Flexcomm11ToDspInterrupt   = 11U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
179     kINPUTMUX_Flexcomm12ToDspInterrupt   = 12U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
180     kINPUTMUX_Flexcomm13ToDspInterrupt   = 13U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
181     kINPUTMUX_Mu2AToDspInterrupt         = 14U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
182     kINPUTMUX_Mu4BToDspInterrupt         = 15U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
183     kINPUTMUX_Wdt0ToDspInterrupt         = 16U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
184     kINPUTMUX_Wdt1ToDspInterrupt         = 17U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
185     kINPUTMUX_Utick0ToDspInterrupt       = 18U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
186     kINPUTMUX_Spi14ToDspInterrupt        = 19U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
187     kINPUTMUX_Mrt0ToDspInterrupt         = 20U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
188     kINPUTMUX_OsEventTimerToDspInterrupt = 21U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
189     kINPUTMUX_Ctimer0ToDspInterrupt      = 22U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
190     kINPUTMUX_Ctimer1ToDspInterrupt      = 23U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
191     kINPUTMUX_Ctimer2ToDspInterrupt      = 24U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
192     kINPUTMUX_Ctimer3ToDspInterrupt      = 25U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
193     kINPUTMUX_Ctimer4ToDspInterrupt      = 26U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
194     kINPUTMUX_Rtc0AlarmToDspInterrupt    = 27U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
195     kINPUTMUX_Rtc0WakeupToDspInterrupt   = 28U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
196     kINPUTMUX_I3c0ToDspInterrupt         = 29U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
197     kINPUTMUX_I3c1ToDspInterrupt         = 30U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
198     kINPUTMUX_MicfilToDspInterrupt       = 31U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
199     kINPUTMUX_HwvadToDspInterrupt        = 32U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
200     kINPUTMUX_LcdifToDspInterrupt        = 33U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
201     kINPUTMUX_GpuToDspInterrupt          = 34U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
202     kINPUTMUX_EzhvToDspInterrupt         = 35U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
203     kINPUTMUX_FlexioToDspInterrupt       = 36U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
204     kINPUTMUX_Spi16ToDspInterrupt        = 37U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
205     kINPUTMUX_Dma0Irq0ToDspInterrupt     = 38U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
206     kINPUTMUX_Dma0Irq1ToDspInterrupt     = 39U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
207     kINPUTMUX_Dma0Irq2ToDspInterrupt     = 40U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
208     kINPUTMUX_Dma0Irq3ToDspInterrupt     = 41U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
209     kINPUTMUX_Dma0Irq4ToDspInterrupt     = 42U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
210     kINPUTMUX_Dma0Irq5ToDspInterrupt     = 43U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
211     kINPUTMUX_Dma0Irq6ToDspInterrupt     = 44U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
212     kINPUTMUX_Dma0Irq7ToDspInterrupt     = 45U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
213     kINPUTMUX_Dma0Irq8ToDspInterrupt     = 46U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
214     kINPUTMUX_Dma0Irq9ToDspInterrupt     = 47U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
215     kINPUTMUX_Dma0Irq10ToDspInterrupt    = 48U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
216     kINPUTMUX_Dma0Irq11ToDspInterrupt    = 49U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
217     kINPUTMUX_Dma0Irq12ToDspInterrupt    = 50U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
218     kINPUTMUX_Dma0Irq13ToDspInterrupt    = 51U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
219     kINPUTMUX_Dma0Irq14ToDspInterrupt    = 52U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
220     kINPUTMUX_Dma0Irq15ToDspInterrupt    = 53U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
221     kINPUTMUX_Dma1Irq0ToDspInterrupt     = 54U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
222     kINPUTMUX_Dma1Irq1ToDspInterrupt     = 55U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
223     kINPUTMUX_Dma1Irq2ToDspInterrupt     = 56U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
224     kINPUTMUX_Dma1Irq3ToDspInterrupt     = 57U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
225     kINPUTMUX_Dma1Irq4ToDspInterrupt     = 58U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
226     kINPUTMUX_Dma1Irq5ToDspInterrupt     = 59U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
227     kINPUTMUX_Dma1Irq6ToDspInterrupt     = 60U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
228     kINPUTMUX_Dma1Irq7ToDspInterrupt     = 61U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
229     kINPUTMUX_Dma1Irq8ToDspInterrupt     = 62U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
230     kINPUTMUX_Dma1Irq9ToDspInterrupt     = 63U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
231     kINPUTMUX_Dma1Irq10ToDspInterrupt    = 64U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
232     kINPUTMUX_Dma1Irq11ToDspInterrupt    = 65U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
233     kINPUTMUX_Dma1Irq12ToDspInterrupt    = 66U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
234     kINPUTMUX_Dma1Irq13ToDspInterrupt    = 67U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
235     kINPUTMUX_Dma1Irq14ToDspInterrupt    = 68U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
236     kINPUTMUX_Dma1Irq15ToDspInterrupt    = 69U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
237     kINPUTMUX_Gpio0Irq0ToDspInterrupt    = 70U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
238     kINPUTMUX_Gpio0Irq1ToDspInterrupt    = 71U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
239     kINPUTMUX_Gpio1Irq0ToDspInterrupt    = 72U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
240     kINPUTMUX_Gpio1Irq1ToDspInterrupt    = 73U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
241     kINPUTMUX_Gpio2Irq0ToDspInterrupt    = 74U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
242     kINPUTMUX_Gpio2Irq1ToDspInterrupt    = 75U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
243     kINPUTMUX_Gpio3Irq0ToDspInterrupt    = 76U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
244     kINPUTMUX_Gpio3Irq1ToDspInterrupt    = 77U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
245     kINPUTMUX_Gpio4Irq0ToDspInterrupt    = 78U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
246     kINPUTMUX_Gpio4Irq1ToDspInterrupt    = 79U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
247     kINPUTMUX_Gpio5Irq0ToDspInterrupt    = 80U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
248     kINPUTMUX_Gpio5Irq1ToDspInterrupt    = 81U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
249     kINPUTMUX_Gpio6Irq0ToDspInterrupt    = 82U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
250     kINPUTMUX_Gpio6Irq1ToDspInterrupt    = 83U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
251     kINPUTMUX_Gpio7Irq0ToDspInterrupt    = 84U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
252     kINPUTMUX_Gpio7Irq1ToDspInterrupt    = 85U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
253     kINPUTMUX_GpioInt0ToDspInterrupt     = 86U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
254     kINPUTMUX_GpioInt1ToDspInterrupt     = 87U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
255     kINPUTMUX_GpioInt2ToDspInterrupt     = 88U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
256     kINPUTMUX_GpioInt3ToDspInterrupt     = 89U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
257     kINPUTMUX_GpioInt4ToDspInterrupt     = 90U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
258     kINPUTMUX_GpioInt5ToDspInterrupt     = 91U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
259     kINPUTMUX_GpioInt6ToDspInterrupt     = 92U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
260     kINPUTMUX_GpioInt7ToDspInterrupt     = 93U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
261     kINPUTMUX_Sai0ToDspInterrupt         = 94U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
262     kINPUTMUX_Sai1ToDspInterrupt         = 95U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
263     kINPUTMUX_Sai2ToDspInterrupt         = 96U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
264     kINPUTMUX_Sai3ToDspInterrupt         = 97U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
265     kINPUTMUX_Xspi0ToDspInterrupt        = 98U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
266     kINPUTMUX_Xspi1ToDspInterrupt        = 99U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
267     kINPUTMUX_Xspi2ToDspInterrupt        = 100U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
268     kINPUTMUX_JpegIrqToDspInterrupt      = 101U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
269     kINPUTMUX_PngIrqToDspInterrupt       = 102U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
270     kINPUTMUX_Neutron64IrqToDspInterrupt = 103U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
271     kINPUTMUX_PmcIrqToDspInterrupt       = 104U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
272 
273     /* FLEXCOMM0 TRIG input mux */
274     kINPUTMUX_CtInp0ToFlexcomm0         = 0U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
275     kINPUTMUX_CtInp1ToFlexcomm0         = 1U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
276     kINPUTMUX_CtInp2ToFlexcomm0         = 2U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
277     kINPUTMUX_CtInp3ToFlexcomm0         = 3U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
278     kINPUTMUX_Sct0Out3ToFlexcomm0       = 4U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
279     kINPUTMUX_Sct0Out6ToFlexcomm0       = 5U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
280     kINPUTMUX_Sct0Out9ToFlexcomm0       = 6U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
281     kINPUTMUX_Ct0Mat3ToFlexcomm0        = 7U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
282     kINPUTMUX_Ct1Mat3ToFlexcomm0        = 8U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
283     kINPUTMUX_Ct2Mat3ToFlexcomm0        = 9U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
284     kINPUTMUX_Ct3Mat3ToFlexcomm0        = 10U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
285     kINPUTMUX_Ct4Mat3ToFlexcomm0        = 11U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
286     kINPUTMUX_GpioInt0BMatchToFlexcomm0 = 12U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
287     kINPUTMUX_Cmp0OutToFlexcomm0        = 13U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
288     kINPUTMUX_Rtc0IrqToFlexcomm0        = 14U + (FLEXCOMM0_ITRIG_PMUX_ID << PMUX_SHIFT),
289 
290     /* FLEXCOMM1 TRIG input mux */
291     kINPUTMUX_CtInp0ToFlexcomm1         = 0U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
292     kINPUTMUX_CtInp1ToFlexcomm1         = 1U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
293     kINPUTMUX_CtInp2ToFlexcomm1         = 2U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
294     kINPUTMUX_CtInp3ToFlexcomm1         = 3U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
295     kINPUTMUX_Sct0Out3ToFlexcomm1       = 4U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
296     kINPUTMUX_Sct0Out6ToFlexcomm1       = 5U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
297     kINPUTMUX_Sct0Out9ToFlexcomm1       = 6U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
298     kINPUTMUX_Ct0Mat3ToFlexcomm1        = 7U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
299     kINPUTMUX_Ct1Mat3ToFlexcomm1        = 8U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
300     kINPUTMUX_Ct2Mat3ToFlexcomm1        = 9U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
301     kINPUTMUX_Ct3Mat3ToFlexcomm1        = 10U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
302     kINPUTMUX_Ct4Mat3ToFlexcomm1        = 11U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
303     kINPUTMUX_GpioInt0BMatchToFlexcomm1 = 12U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
304     kINPUTMUX_Cmp0OutToFlexcomm1        = 13U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
305     kINPUTMUX_Rtc0IrqToFlexcomm1        = 14U + (FLEXCOMM1_ITRIG_PMUX_ID << PMUX_SHIFT),
306 
307     /* FLEXCOMM2 TRIG input mux */
308     kINPUTMUX_CtInp0ToFlexcomm2         = 0U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
309     kINPUTMUX_CtInp1ToFlexcomm2         = 1U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
310     kINPUTMUX_CtInp2ToFlexcomm2         = 2U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
311     kINPUTMUX_CtInp3ToFlexcomm2         = 3U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
312     kINPUTMUX_Sct0Out3ToFlexcomm2       = 4U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
313     kINPUTMUX_Sct0Out6ToFlexcomm2       = 5U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
314     kINPUTMUX_Sct0Out9ToFlexcomm2       = 6U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
315     kINPUTMUX_Ct0Mat3ToFlexcomm2        = 7U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
316     kINPUTMUX_Ct1Mat3ToFlexcomm2        = 8U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
317     kINPUTMUX_Ct2Mat3ToFlexcomm2        = 9U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
318     kINPUTMUX_Ct3Mat3ToFlexcomm2        = 10U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
319     kINPUTMUX_Ct4Mat3ToFlexcomm2        = 11U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
320     kINPUTMUX_GpioInt0BMatchToFlexcomm2 = 12U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
321     kINPUTMUX_Cmp0OutToFlexcomm2        = 13U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
322     kINPUTMUX_Rtc0IrqToFlexcomm2        = 14U + (FLEXCOMM2_ITRIG_PMUX_ID << PMUX_SHIFT),
323 
324     /* FLEXCOMM3 TRIG input mux */
325     kINPUTMUX_CtInp0ToFlexcomm3         = 0U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
326     kINPUTMUX_CtInp1ToFlexcomm3         = 1U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
327     kINPUTMUX_CtInp2ToFlexcomm3         = 2U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
328     kINPUTMUX_CtInp3ToFlexcomm3         = 3U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
329     kINPUTMUX_Sct0Out3ToFlexcomm3       = 4U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
330     kINPUTMUX_Sct0Out6ToFlexcomm3       = 5U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
331     kINPUTMUX_Sct0Out9ToFlexcomm3       = 6U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
332     kINPUTMUX_Ct0Mat3ToFlexcomm3        = 7U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
333     kINPUTMUX_Ct1Mat3ToFlexcomm3        = 8U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
334     kINPUTMUX_Ct2Mat3ToFlexcomm3        = 9U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
335     kINPUTMUX_Ct3Mat3ToFlexcomm3        = 10U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
336     kINPUTMUX_Ct4Mat3ToFlexcomm3        = 11U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
337     kINPUTMUX_GpioInt0BMatchToFlexcomm3 = 12U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
338     kINPUTMUX_Cmp0OutToFlexcomm3        = 13U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
339     kINPUTMUX_Rtc0IrqToFlexcomm3        = 14U + (FLEXCOMM3_ITRIG_PMUX_ID << PMUX_SHIFT),
340 
341     /* FLEXCOMM4 TRIG input mux */
342     kINPUTMUX_CtInp0ToFlexcomm4         = 0U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
343     kINPUTMUX_CtInp1ToFlexcomm4         = 1U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
344     kINPUTMUX_CtInp2ToFlexcomm4         = 2U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
345     kINPUTMUX_CtInp3ToFlexcomm4         = 3U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
346     kINPUTMUX_Sct0Out3ToFlexcomm4       = 4U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
347     kINPUTMUX_Sct0Out6ToFlexcomm4       = 5U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
348     kINPUTMUX_Sct0Out9ToFlexcomm4       = 6U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
349     kINPUTMUX_Ct0Mat3ToFlexcomm4        = 7U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
350     kINPUTMUX_Ct1Mat3ToFlexcomm4        = 8U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
351     kINPUTMUX_Ct2Mat3ToFlexcomm4        = 9U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
352     kINPUTMUX_Ct3Mat3ToFlexcomm4        = 10U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
353     kINPUTMUX_Ct4Mat3ToFlexcomm4        = 11U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
354     kINPUTMUX_GpioInt0BMatchToFlexcomm4 = 12U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
355     kINPUTMUX_Cmp0OutToFlexcomm4        = 13U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
356     kINPUTMUX_Rtc0IrqToFlexcomm4        = 14U + (FLEXCOMM4_ITRIG_PMUX_ID << PMUX_SHIFT),
357 
358     /* FLEXCOMM5 TRIG input mux */
359     kINPUTMUX_CtInp0ToFlexcomm5         = 0U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
360     kINPUTMUX_CtInp1ToFlexcomm5         = 1U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
361     kINPUTMUX_CtInp2ToFlexcomm5         = 2U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
362     kINPUTMUX_CtInp3ToFlexcomm5         = 3U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
363     kINPUTMUX_Sct0Out3ToFlexcomm5       = 4U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
364     kINPUTMUX_Sct0Out6ToFlexcomm5       = 5U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
365     kINPUTMUX_Sct0Out9ToFlexcomm5       = 6U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
366     kINPUTMUX_Ct0Mat3ToFlexcomm5        = 7U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
367     kINPUTMUX_Ct1Mat3ToFlexcomm5        = 8U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
368     kINPUTMUX_Ct2Mat3ToFlexcomm5        = 9U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
369     kINPUTMUX_Ct3Mat3ToFlexcomm5        = 10U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
370     kINPUTMUX_Ct4Mat3ToFlexcomm5        = 11U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
371     kINPUTMUX_GpioInt0BMatchToFlexcomm5 = 12U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
372     kINPUTMUX_Cmp0OutToFlexcomm5        = 13U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
373     kINPUTMUX_Rtc0IrqToFlexcomm5        = 14U + (FLEXCOMM5_ITRIG_PMUX_ID << PMUX_SHIFT),
374 
375     /* FLEXCOMM6 TRIG input mux */
376     kINPUTMUX_CtInp0ToFlexcomm6         = 0U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
377     kINPUTMUX_CtInp1ToFlexcomm6         = 1U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
378     kINPUTMUX_CtInp2ToFlexcomm6         = 2U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
379     kINPUTMUX_CtInp3ToFlexcomm6         = 3U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
380     kINPUTMUX_Sct0Out3ToFlexcomm6       = 4U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
381     kINPUTMUX_Sct0Out6ToFlexcomm6       = 5U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
382     kINPUTMUX_Sct0Out9ToFlexcomm6       = 6U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
383     kINPUTMUX_Ct0Mat3ToFlexcomm6        = 7U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
384     kINPUTMUX_Ct1Mat3ToFlexcomm6        = 8U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
385     kINPUTMUX_Ct2Mat3ToFlexcomm6        = 9U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
386     kINPUTMUX_Ct3Mat3ToFlexcomm6        = 10U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
387     kINPUTMUX_Ct4Mat3ToFlexcomm6        = 11U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
388     kINPUTMUX_GpioInt0BMatchToFlexcomm6 = 12U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
389     kINPUTMUX_Cmp0OutToFlexcomm6        = 13U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
390     kINPUTMUX_Rtc0IrqToFlexcomm6        = 14U + (FLEXCOMM6_ITRIG_PMUX_ID << PMUX_SHIFT),
391 
392     /* FLEXCOMM7 TRIG input mux */
393     kINPUTMUX_CtInp0ToFlexcomm7         = 0U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
394     kINPUTMUX_CtInp1ToFlexcomm7         = 1U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
395     kINPUTMUX_CtInp2ToFlexcomm7         = 2U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
396     kINPUTMUX_CtInp3ToFlexcomm7         = 3U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
397     kINPUTMUX_Sct0Out3ToFlexcomm7       = 4U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
398     kINPUTMUX_Sct0Out6ToFlexcomm7       = 5U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
399     kINPUTMUX_Sct0Out9ToFlexcomm7       = 6U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
400     kINPUTMUX_Ct0Mat3ToFlexcomm7        = 7U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
401     kINPUTMUX_Ct1Mat3ToFlexcomm7        = 8U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
402     kINPUTMUX_Ct2Mat3ToFlexcomm7        = 9U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
403     kINPUTMUX_Ct3Mat3ToFlexcomm7        = 10U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
404     kINPUTMUX_Ct4Mat3ToFlexcomm7        = 11U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
405     kINPUTMUX_GpioInt0BMatchToFlexcomm7 = 12U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
406     kINPUTMUX_Cmp0OutToFlexcomm7        = 13U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
407     kINPUTMUX_Rtc0IrqToFlexcomm7        = 14U + (FLEXCOMM7_ITRIG_PMUX_ID << PMUX_SHIFT),
408 
409     /* FLEXCOMM8 TRIG input mux */
410     kINPUTMUX_CtInp0ToFlexcomm8         = 0U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
411     kINPUTMUX_CtInp1ToFlexcomm8         = 1U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
412     kINPUTMUX_CtInp2ToFlexcomm8         = 2U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
413     kINPUTMUX_CtInp3ToFlexcomm8         = 3U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
414     kINPUTMUX_Sct0Out3ToFlexcomm8       = 4U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
415     kINPUTMUX_Sct0Out6ToFlexcomm8       = 5U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
416     kINPUTMUX_Sct0Out9ToFlexcomm8       = 6U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
417     kINPUTMUX_Ct0Mat3ToFlexcomm8        = 7U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
418     kINPUTMUX_Ct1Mat3ToFlexcomm8        = 8U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
419     kINPUTMUX_Ct2Mat3ToFlexcomm8        = 9U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
420     kINPUTMUX_Ct3Mat3ToFlexcomm8        = 10U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
421     kINPUTMUX_Ct4Mat3ToFlexcomm8        = 11U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
422     kINPUTMUX_GpioInt0BMatchToFlexcomm8 = 12U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
423     kINPUTMUX_Cmp0OutToFlexcomm8        = 13U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
424     kINPUTMUX_Rtc0IrqToFlexcomm8        = 14U + (FLEXCOMM8_ITRIG_PMUX_ID << PMUX_SHIFT),
425 
426     /* FLEXCOMM9 TRIG input mux */
427     kINPUTMUX_CtInp0ToFlexcomm9         = 0U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
428     kINPUTMUX_CtInp1ToFlexcomm9         = 1U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
429     kINPUTMUX_CtInp2ToFlexcomm9         = 2U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
430     kINPUTMUX_CtInp3ToFlexcomm9         = 3U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
431     kINPUTMUX_Sct0Out3ToFlexcomm9       = 4U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
432     kINPUTMUX_Sct0Out6ToFlexcomm9       = 5U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
433     kINPUTMUX_Sct0Out9ToFlexcomm9       = 6U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
434     kINPUTMUX_Ct0Mat3ToFlexcomm9        = 7U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
435     kINPUTMUX_Ct1Mat3ToFlexcomm9        = 8U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
436     kINPUTMUX_Ct2Mat3ToFlexcomm9        = 9U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
437     kINPUTMUX_Ct3Mat3ToFlexcomm9        = 10U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
438     kINPUTMUX_Ct4Mat3ToFlexcomm9        = 11U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
439     kINPUTMUX_GpioInt0BMatchToFlexcomm9 = 12U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
440     kINPUTMUX_Cmp0OutToFlexcomm9        = 13U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
441     kINPUTMUX_Rtc0IrqToFlexcomm9        = 14U + (FLEXCOMM9_ITRIG_PMUX_ID << PMUX_SHIFT),
442 
443     /* FLEXCOMM10 TRIG input mux */
444     kINPUTMUX_CtInp0ToFlexcomm10         = 0U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
445     kINPUTMUX_CtInp1ToFlexcomm10         = 1U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
446     kINPUTMUX_CtInp2ToFlexcomm10         = 2U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
447     kINPUTMUX_CtInp3ToFlexcomm10         = 3U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
448     kINPUTMUX_Sct0Out3ToFlexcomm10       = 4U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
449     kINPUTMUX_Sct0Out6ToFlexcomm10       = 5U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
450     kINPUTMUX_Sct0Out9ToFlexcomm10       = 6U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
451     kINPUTMUX_Ct0Mat3ToFlexcomm10        = 7U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
452     kINPUTMUX_Ct1Mat3ToFlexcomm10        = 8U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
453     kINPUTMUX_Ct2Mat3ToFlexcomm10        = 9U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
454     kINPUTMUX_Ct3Mat3ToFlexcomm10        = 10U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
455     kINPUTMUX_Ct4Mat3ToFlexcomm10        = 11U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
456     kINPUTMUX_GpioInt0BMatchToFlexcomm10 = 12U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
457     kINPUTMUX_Cmp0OutToFlexcomm10        = 13U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
458     kINPUTMUX_Rtc0IrqToFlexcomm10        = 14U + (FLEXCOMM10_ITRIG_PMUX_ID << PMUX_SHIFT),
459 
460     /* FLEXCOMM11 TRIG input mux */
461     kINPUTMUX_CtInp0ToFlexcomm11         = 0U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
462     kINPUTMUX_CtInp1ToFlexcomm11         = 1U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
463     kINPUTMUX_CtInp2ToFlexcomm11         = 2U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
464     kINPUTMUX_CtInp3ToFlexcomm11         = 3U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
465     kINPUTMUX_Sct0Out3ToFlexcomm11       = 4U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
466     kINPUTMUX_Sct0Out6ToFlexcomm11       = 5U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
467     kINPUTMUX_Sct0Out9ToFlexcomm11       = 6U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
468     kINPUTMUX_Ct0Mat3ToFlexcomm11        = 7U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
469     kINPUTMUX_Ct1Mat3ToFlexcomm11        = 8U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
470     kINPUTMUX_Ct2Mat3ToFlexcomm11        = 9U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
471     kINPUTMUX_Ct3Mat3ToFlexcomm11        = 10U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
472     kINPUTMUX_Ct4Mat3ToFlexcomm11        = 11U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
473     kINPUTMUX_GpioInt0BMatchToFlexcomm11 = 12U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
474     kINPUTMUX_Cmp0OutToFlexcomm11        = 13U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
475     kINPUTMUX_Rtc0IrqToFlexcomm11        = 14U + (FLEXCOMM11_ITRIG_PMUX_ID << PMUX_SHIFT),
476 
477     /* FLEXCOMM12 TRIG input mux */
478     kINPUTMUX_CtInp0ToFlexcomm12         = 0U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
479     kINPUTMUX_CtInp1ToFlexcomm12         = 1U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
480     kINPUTMUX_CtInp2ToFlexcomm12         = 2U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
481     kINPUTMUX_CtInp3ToFlexcomm12         = 3U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
482     kINPUTMUX_Sct0Out3ToFlexcomm12       = 4U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
483     kINPUTMUX_Sct0Out6ToFlexcomm12       = 5U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
484     kINPUTMUX_Sct0Out9ToFlexcomm12       = 6U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
485     kINPUTMUX_Ct0Mat3ToFlexcomm12        = 7U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
486     kINPUTMUX_Ct1Mat3ToFlexcomm12        = 8U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
487     kINPUTMUX_Ct2Mat3ToFlexcomm12        = 9U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
488     kINPUTMUX_Ct3Mat3ToFlexcomm12        = 10U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
489     kINPUTMUX_Ct4Mat3ToFlexcomm12        = 11U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
490     kINPUTMUX_GpioInt0BMatchToFlexcomm12 = 12U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
491     kINPUTMUX_Cmp0OutToFlexcomm12        = 13U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
492     kINPUTMUX_Rtc0IrqToFlexcomm12        = 14U + (FLEXCOMM12_ITRIG_PMUX_ID << PMUX_SHIFT),
493 
494     /* FLEXCOMM13 TRIG input mux */
495     kINPUTMUX_CtInp0ToFlexcomm13         = 0U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
496     kINPUTMUX_CtInp1ToFlexcomm13         = 1U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
497     kINPUTMUX_CtInp2ToFlexcomm13         = 2U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
498     kINPUTMUX_CtInp3ToFlexcomm13         = 3U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
499     kINPUTMUX_Sct0Out3ToFlexcomm13       = 4U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
500     kINPUTMUX_Sct0Out6ToFlexcomm13       = 5U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
501     kINPUTMUX_Sct0Out9ToFlexcomm13       = 6U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
502     kINPUTMUX_Ct0Mat3ToFlexcomm13        = 7U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
503     kINPUTMUX_Ct1Mat3ToFlexcomm13        = 8U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
504     kINPUTMUX_Ct2Mat3ToFlexcomm13        = 9U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
505     kINPUTMUX_Ct3Mat3ToFlexcomm13        = 10U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
506     kINPUTMUX_Ct4Mat3ToFlexcomm13        = 11U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
507     kINPUTMUX_GpioInt0BMatchToFlexcomm13 = 12U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
508     kINPUTMUX_Cmp0OutToFlexcomm13        = 13U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
509     kINPUTMUX_Rtc0IrqToFlexcomm13        = 14U + (FLEXCOMM13_ITRIG_PMUX_ID << PMUX_SHIFT),
510 
511     /*!< CTmier0 capture input mux. */
512     kINPUTMUX_CtInp0ToTimer0CaptureChannels     = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
513     kINPUTMUX_CtInp1ToTimer0CaptureChannels     = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
514     kINPUTMUX_CtInp2ToTimer0CaptureChannels     = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
515     kINPUTMUX_CtInp3ToTimer0CaptureChannels     = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
516     kINPUTMUX_CtInp4ToTimer0CaptureChannels     = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
517     kINPUTMUX_CtInp5ToTimer0CaptureChannels     = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
518     kINPUTMUX_CtInp6ToTimer0CaptureChannels     = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
519     kINPUTMUX_CtInp7ToTimer0CaptureChannels     = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
520     kINPUTMUX_CtInp8ToTimer0CaptureChannels     = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
521     kINPUTMUX_CtInp9ToTimer0CaptureChannels     = 9U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
522     kINPUTMUX_CtInp10ToTimer0CaptureChannels    = 10U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
523     kINPUTMUX_CtInp11ToTimer0CaptureChannels    = 11U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
524     kINPUTMUX_CtInp12ToTimer0CaptureChannels    = 12U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
525     kINPUTMUX_CtInp13ToTimer0CaptureChannels    = 13U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
526     kINPUTMUX_CtInp14ToTimer0CaptureChannels    = 14U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
527     kINPUTMUX_CtInp15ToTimer0CaptureChannels    = 15U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
528     kINPUTMUX_Sai0TxSyncToTimer0CaptureChannels = 16U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
529     kINPUTMUX_Sai0RxSyncToTimer0CaptureChannels = 17U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
530     kINPUTMUX_Sai1TxSyncToTimer0CaptureChannels = 18U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
531     kINPUTMUX_Sai1RxSyncToTimer0CaptureChannels = 19U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
532     kINPUTMUX_Sai2TxSyncToTimer0CaptureChannels = 20U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
533     kINPUTMUX_Sai2RxSyncToTimer0CaptureChannels = 21U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
534     kINPUTMUX_Usb0SofToTimer0CaptureChannels    = 22U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
535     kINPUTMUX_Usb1SofToTimer0CaptureChannels    = 23U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
536     kINPUTMUX_Cmp0OutToTimer0CaptureChannels    = 24U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
537     kINPUTMUX_Adc0Tcomp0ToTimer0CaptureChannels = 25U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
538     kINPUTMUX_Adc0Tcomp1ToTimer0CaptureChannels = 26U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
539     kINPUTMUX_TmprOut0ToTimer0CaptureChannels   = 27U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
540     kINPUTMUX_TmprOut1ToTimer0CaptureChannels   = 28U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
541 
542     /*!< CTmier1 capture input mux. */
543     kINPUTMUX_CtInp0ToTimer1CaptureChannels     = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
544     kINPUTMUX_CtInp1ToTimer1CaptureChannels     = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
545     kINPUTMUX_CtInp2ToTimer1CaptureChannels     = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
546     kINPUTMUX_CtInp3ToTimer1CaptureChannels     = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
547     kINPUTMUX_CtInp4ToTimer1CaptureChannels     = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
548     kINPUTMUX_CtInp5ToTimer1CaptureChannels     = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
549     kINPUTMUX_CtInp6ToTimer1CaptureChannels     = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
550     kINPUTMUX_CtInp7ToTimer1CaptureChannels     = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
551     kINPUTMUX_CtInp8ToTimer1CaptureChannels     = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
552     kINPUTMUX_CtInp9ToTimer1CaptureChannels     = 9U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
553     kINPUTMUX_CtInp10ToTimer1CaptureChannels    = 10U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
554     kINPUTMUX_CtInp11ToTimer1CaptureChannels    = 11U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
555     kINPUTMUX_CtInp12ToTimer1CaptureChannels    = 12U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
556     kINPUTMUX_CtInp13ToTimer1CaptureChannels    = 13U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
557     kINPUTMUX_CtInp14ToTimer1CaptureChannels    = 14U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
558     kINPUTMUX_CtInp15ToTimer1CaptureChannels    = 15U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
559     kINPUTMUX_Sai0TxSyncToTimer1CaptureChannels = 16U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
560     kINPUTMUX_Sai0RxSyncToTimer1CaptureChannels = 17U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
561     kINPUTMUX_Sai1TxSyncToTimer1CaptureChannels = 18U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
562     kINPUTMUX_Sai1RxSyncToTimer1CaptureChannels = 19U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
563     kINPUTMUX_Sai2TxSyncToTimer1CaptureChannels = 20U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
564     kINPUTMUX_Sai2RxSyncToTimer1CaptureChannels = 21U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
565     kINPUTMUX_Usb0SofToTimer1CaptureChannels    = 22U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
566     kINPUTMUX_Usb1SofToTimer1CaptureChannels    = 23U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
567     kINPUTMUX_Cmp0OutToTimer1CaptureChannels    = 24U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
568     kINPUTMUX_Adc0Tcomp0ToTimer1CaptureChannels = 25U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
569     kINPUTMUX_Adc0Tcomp1ToTimer1CaptureChannels = 26U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
570     kINPUTMUX_TmprOut0ToTimer1CaptureChannels   = 27U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
571     kINPUTMUX_TmprOut1ToTimer1CaptureChannels   = 28U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
572 
573     /*!< CTmier2 capture input mux. */
574     kINPUTMUX_CtInp0ToTimer2CaptureChannels     = 0U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
575     kINPUTMUX_CtInp1ToTimer2CaptureChannels     = 1U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
576     kINPUTMUX_CtInp2ToTimer2CaptureChannels     = 2U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
577     kINPUTMUX_CtInp3ToTimer2CaptureChannels     = 3U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
578     kINPUTMUX_CtInp4ToTimer2CaptureChannels     = 4U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
579     kINPUTMUX_CtInp5ToTimer2CaptureChannels     = 5U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
580     kINPUTMUX_CtInp6ToTimer2CaptureChannels     = 6U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
581     kINPUTMUX_CtInp7ToTimer2CaptureChannels     = 7U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
582     kINPUTMUX_CtInp8ToTimer2CaptureChannels     = 8U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
583     kINPUTMUX_CtInp9ToTimer2CaptureChannels     = 9U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
584     kINPUTMUX_CtInp10ToTimer2CaptureChannels    = 10U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
585     kINPUTMUX_CtInp11ToTimer2CaptureChannels    = 11U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
586     kINPUTMUX_CtInp12ToTimer2CaptureChannels    = 12U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
587     kINPUTMUX_CtInp13ToTimer2CaptureChannels    = 13U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
588     kINPUTMUX_CtInp14ToTimer2CaptureChannels    = 14U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
589     kINPUTMUX_CtInp15ToTimer2CaptureChannels    = 15U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
590     kINPUTMUX_Sai0TxSyncToTimer2CaptureChannels = 16U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
591     kINPUTMUX_Sai0RxSyncToTimer2CaptureChannels = 17U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
592     kINPUTMUX_Sai1TxSyncToTimer2CaptureChannels = 18U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
593     kINPUTMUX_Sai1RxSyncToTimer2CaptureChannels = 19U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
594     kINPUTMUX_Sai2TxSyncToTimer2CaptureChannels = 20U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
595     kINPUTMUX_Sai2RxSyncToTimer2CaptureChannels = 21U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
596     kINPUTMUX_Usb0SofToTimer2CaptureChannels    = 22U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
597     kINPUTMUX_Usb1SofToTimer2CaptureChannels    = 23U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
598     kINPUTMUX_Cmp0OutToTimer2CaptureChannels    = 24U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
599     kINPUTMUX_Adc0Tcomp0ToTimer2CaptureChannels = 25U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
600     kINPUTMUX_Adc0Tcomp1ToTimer2CaptureChannels = 26U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
601     kINPUTMUX_TmprOut0ToTimer2CaptureChannels   = 27U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
602     kINPUTMUX_TmprOut1ToTimer2CaptureChannels   = 28U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
603 
604     /*!< CTmier3 capture input mux. */
605     kINPUTMUX_CtInp0ToTimer3CaptureChannels     = 0U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
606     kINPUTMUX_CtInp1ToTimer3CaptureChannels     = 1U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
607     kINPUTMUX_CtInp2ToTimer3CaptureChannels     = 2U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
608     kINPUTMUX_CtInp3ToTimer3CaptureChannels     = 3U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
609     kINPUTMUX_CtInp4ToTimer3CaptureChannels     = 4U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
610     kINPUTMUX_CtInp5ToTimer3CaptureChannels     = 5U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
611     kINPUTMUX_CtInp6ToTimer3CaptureChannels     = 6U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
612     kINPUTMUX_CtInp7ToTimer3CaptureChannels     = 7U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
613     kINPUTMUX_CtInp8ToTimer3CaptureChannels     = 8U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
614     kINPUTMUX_CtInp9ToTimer3CaptureChannels     = 9U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
615     kINPUTMUX_CtInp10ToTimer3CaptureChannels    = 10U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
616     kINPUTMUX_CtInp11ToTimer3CaptureChannels    = 11U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
617     kINPUTMUX_CtInp12ToTimer3CaptureChannels    = 12U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
618     kINPUTMUX_CtInp13ToTimer3CaptureChannels    = 13U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
619     kINPUTMUX_CtInp14ToTimer3CaptureChannels    = 14U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
620     kINPUTMUX_CtInp15ToTimer3CaptureChannels    = 15U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
621     kINPUTMUX_Sai0TxSyncToTimer3CaptureChannels = 16U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
622     kINPUTMUX_Sai0RxSyncToTimer3CaptureChannels = 17U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
623     kINPUTMUX_Sai1TxSyncToTimer3CaptureChannels = 18U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
624     kINPUTMUX_Sai1RxSyncToTimer3CaptureChannels = 19U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
625     kINPUTMUX_Sai2TxSyncToTimer3CaptureChannels = 20U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
626     kINPUTMUX_Sai2RxSyncToTimer3CaptureChannels = 21U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
627     kINPUTMUX_Usb0SofToTimer3CaptureChannels    = 22U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
628     kINPUTMUX_Usb1SofToTimer3CaptureChannels    = 23U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
629     kINPUTMUX_Cmp0OutToTimer3CaptureChannels    = 24U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
630     kINPUTMUX_Adc0Tcomp0ToTimer3CaptureChannels = 25U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
631     kINPUTMUX_Adc0Tcomp1ToTimer3CaptureChannels = 26U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
632     kINPUTMUX_TmprOut0ToTimer3CaptureChannels   = 27U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
633     kINPUTMUX_TmprOut1ToTimer3CaptureChannels   = 28U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
634 
635     /*!< CTmier4 capture input mux. */
636     kINPUTMUX_CtInp0ToTimer4CaptureChannels     = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
637     kINPUTMUX_CtInp1ToTimer4CaptureChannels     = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
638     kINPUTMUX_CtInp2ToTimer4CaptureChannels     = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
639     kINPUTMUX_CtInp3ToTimer4CaptureChannels     = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
640     kINPUTMUX_CtInp4ToTimer4CaptureChannels     = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
641     kINPUTMUX_CtInp5ToTimer4CaptureChannels     = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
642     kINPUTMUX_CtInp6ToTimer4CaptureChannels     = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
643     kINPUTMUX_CtInp7ToTimer4CaptureChannels     = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
644     kINPUTMUX_CtInp8ToTimer4CaptureChannels     = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
645     kINPUTMUX_CtInp9ToTimer4CaptureChannels     = 9U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
646     kINPUTMUX_CtInp10ToTimer4CaptureChannels    = 10U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
647     kINPUTMUX_CtInp11ToTimer4CaptureChannels    = 11U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
648     kINPUTMUX_CtInp12ToTimer4CaptureChannels    = 12U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
649     kINPUTMUX_CtInp13ToTimer4CaptureChannels    = 13U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
650     kINPUTMUX_CtInp14ToTimer4CaptureChannels    = 14U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
651     kINPUTMUX_CtInp15ToTimer4CaptureChannels    = 15U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
652     kINPUTMUX_Sai0TxSyncToTimer4CaptureChannels = 16U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
653     kINPUTMUX_Sai0RxSyncToTimer4CaptureChannels = 17U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
654     kINPUTMUX_Sai1TxSyncToTimer4CaptureChannels = 18U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
655     kINPUTMUX_Sai1RxSyncToTimer4CaptureChannels = 19U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
656     kINPUTMUX_Sai2TxSyncToTimer4CaptureChannels = 20U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
657     kINPUTMUX_Sai2RxSyncToTimer4CaptureChannels = 21U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
658     kINPUTMUX_Usb0SofToTimer4CaptureChannels    = 22U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
659     kINPUTMUX_Usb1SofToTimer4CaptureChannels    = 23U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
660     kINPUTMUX_Cmp0OutToTimer4CaptureChannels    = 24U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
661     kINPUTMUX_Adc0Tcomp0ToTimer4CaptureChannels = 25U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
662     kINPUTMUX_Adc0Tcomp1ToTimer4CaptureChannels = 26U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
663     kINPUTMUX_TmprOut0ToTimer4CaptureChannels   = 27U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
664     kINPUTMUX_TmprOut1ToTimer4CaptureChannels   = 28U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
665 
666     /*!< CTmier0 Input trigger mux. */
667     kINPUTMUX_CtInp0ToTimer0Trigger     = 0U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
668     kINPUTMUX_CtInp1ToTimer0Trigger     = 1U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
669     kINPUTMUX_CtInp2ToTimer0Trigger     = 2U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
670     kINPUTMUX_CtInp3ToTimer0Trigger     = 3U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
671     kINPUTMUX_CtInp4ToTimer0Trigger     = 4U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
672     kINPUTMUX_CtInp5ToTimer0Trigger     = 5U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
673     kINPUTMUX_CtInp6ToTimer0Trigger     = 6U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
674     kINPUTMUX_CtInp7ToTimer0Trigger     = 7U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
675     kINPUTMUX_CtInp8ToTimer0Trigger     = 8U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
676     kINPUTMUX_CtInp9ToTimer0Trigger     = 9U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
677     kINPUTMUX_CtInp10ToTimer0Trigger    = 10U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
678     kINPUTMUX_CtInp11ToTimer0Trigger    = 11U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
679     kINPUTMUX_CtInp12ToTimer0Trigger    = 12U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
680     kINPUTMUX_CtInp13ToTimer0Trigger    = 13U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
681     kINPUTMUX_CtInp14ToTimer0Trigger    = 14U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
682     kINPUTMUX_CtInp15ToTimer0Trigger    = 15U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
683     kINPUTMUX_Sai0TxSyncToTimer0Trigger = 16U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
684     kINPUTMUX_Sai0RxSyncToTimer0Trigger = 17U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
685     kINPUTMUX_Sai1TxSyncToTimer0Trigger = 18U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
686     kINPUTMUX_Sai1RxSyncToTimer0Trigger = 19U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
687     kINPUTMUX_Sai2TxSyncToTimer0Trigger = 20U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
688     kINPUTMUX_Sai2RxSyncToTimer0Trigger = 21U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
689     kINPUTMUX_Usb0SofToTimer0Trigger    = 22U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
690     kINPUTMUX_Usb1SofToTimer0Trigger    = 23U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
691     kINPUTMUX_Cmp0OutToTimer0Trigger    = 24U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
692     kINPUTMUX_Adc0Tcomp0ToTimer0Trigger = 25U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
693     kINPUTMUX_Adc0Tcomp1ToTimer0Trigger = 26U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
694     kINPUTMUX_TmprOut0ToTimer0Trigger   = 27U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
695     kINPUTMUX_TmprOut1ToTimer0Trigger   = 28U + (CT32BIT0_TRIG_PMUX_ID << PMUX_SHIFT),
696 
697     /*!< CTmier1 Input trigger mux. */
698     kINPUTMUX_CtInp0ToTimer1Trigger     = 0U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
699     kINPUTMUX_CtInp1ToTimer1Trigger     = 1U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
700     kINPUTMUX_CtInp2ToTimer1Trigger     = 2U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
701     kINPUTMUX_CtInp3ToTimer1Trigger     = 3U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
702     kINPUTMUX_CtInp4ToTimer1Trigger     = 4U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
703     kINPUTMUX_CtInp5ToTimer1Trigger     = 5U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
704     kINPUTMUX_CtInp6ToTimer1Trigger     = 6U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
705     kINPUTMUX_CtInp7ToTimer1Trigger     = 7U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
706     kINPUTMUX_CtInp8ToTimer1Trigger     = 8U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
707     kINPUTMUX_CtInp9ToTimer1Trigger     = 9U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
708     kINPUTMUX_CtInp10ToTimer1Trigger    = 10U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
709     kINPUTMUX_CtInp11ToTimer1Trigger    = 11U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
710     kINPUTMUX_CtInp12ToTimer1Trigger    = 12U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
711     kINPUTMUX_CtInp13ToTimer1Trigger    = 13U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
712     kINPUTMUX_CtInp14ToTimer1Trigger    = 14U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
713     kINPUTMUX_CtInp15ToTimer1Trigger    = 15U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
714     kINPUTMUX_Sai0TxSyncToTimer1Trigger = 16U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
715     kINPUTMUX_Sai0RxSyncToTimer1Trigger = 17U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
716     kINPUTMUX_Sai1TxSyncToTimer1Trigger = 18U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
717     kINPUTMUX_Sai1RxSyncToTimer1Trigger = 19U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
718     kINPUTMUX_Sai2TxSyncToTimer1Trigger = 20U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
719     kINPUTMUX_Sai2RxSyncToTimer1Trigger = 21U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
720     kINPUTMUX_Usb0SofToTimer1Trigger    = 22U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
721     kINPUTMUX_Usb1SofToTimer1Trigger    = 23U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
722     kINPUTMUX_Cmp0OutToTimer1Trigger    = 24U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
723     kINPUTMUX_Adc0Tcomp0ToTimer1Trigger = 25U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
724     kINPUTMUX_Adc0Tcomp1ToTimer1Trigger = 26U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
725     kINPUTMUX_TmprOut0ToTimer1Trigger   = 27U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
726     kINPUTMUX_TmprOut1ToTimer1Trigger   = 28U + (CT32BIT1_TRIG_PMUX_ID << PMUX_SHIFT),
727 
728     /*!< CTmier2 Input trigger mux. */
729     kINPUTMUX_CtInp0ToTimer2Trigger     = 0U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
730     kINPUTMUX_CtInp1ToTimer2Trigger     = 1U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
731     kINPUTMUX_CtInp2ToTimer2Trigger     = 2U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
732     kINPUTMUX_CtInp3ToTimer2Trigger     = 3U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
733     kINPUTMUX_CtInp4ToTimer2Trigger     = 4U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
734     kINPUTMUX_CtInp5ToTimer2Trigger     = 5U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
735     kINPUTMUX_CtInp6ToTimer2Trigger     = 6U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
736     kINPUTMUX_CtInp7ToTimer2Trigger     = 7U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
737     kINPUTMUX_CtInp8ToTimer2Trigger     = 8U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
738     kINPUTMUX_CtInp9ToTimer2Trigger     = 9U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
739     kINPUTMUX_CtInp10ToTimer2Trigger    = 10U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
740     kINPUTMUX_CtInp11ToTimer2Trigger    = 11U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
741     kINPUTMUX_CtInp12ToTimer2Trigger    = 12U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
742     kINPUTMUX_CtInp13ToTimer2Trigger    = 13U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
743     kINPUTMUX_CtInp14ToTimer2Trigger    = 14U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
744     kINPUTMUX_CtInp15ToTimer2Trigger    = 15U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
745     kINPUTMUX_Sai0TxSyncToTimer2Trigger = 16U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
746     kINPUTMUX_Sai0RxSyncToTimer2Trigger = 17U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
747     kINPUTMUX_Sai1TxSyncToTimer2Trigger = 18U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
748     kINPUTMUX_Sai1RxSyncToTimer2Trigger = 19U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
749     kINPUTMUX_Sai2TxSyncToTimer2Trigger = 20U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
750     kINPUTMUX_Sai2RxSyncToTimer2Trigger = 21U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
751     kINPUTMUX_Usb0SofToTimer2Trigger    = 22U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
752     kINPUTMUX_Usb1SofToTimer2Trigger    = 23U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
753     kINPUTMUX_Cmp0OutToTimer2Trigger    = 24U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
754     kINPUTMUX_Adc0Tcomp0ToTimer2Trigger = 25U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
755     kINPUTMUX_Adc0Tcomp1ToTimer2Trigger = 26U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
756     kINPUTMUX_TmprOut0ToTimer2Trigger   = 27U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
757     kINPUTMUX_TmprOut1ToTimer2Trigger   = 28U + (CT32BIT2_TRIG_PMUX_ID << PMUX_SHIFT),
758 
759     /*!< CTmier3 Input trigger mux. */
760     kINPUTMUX_CtInp0ToTimer3Trigger     = 0U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
761     kINPUTMUX_CtInp1ToTimer3Trigger     = 1U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
762     kINPUTMUX_CtInp2ToTimer3Trigger     = 2U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
763     kINPUTMUX_CtInp3ToTimer3Trigger     = 3U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
764     kINPUTMUX_CtInp4ToTimer3Trigger     = 4U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
765     kINPUTMUX_CtInp5ToTimer3Trigger     = 5U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
766     kINPUTMUX_CtInp6ToTimer3Trigger     = 6U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
767     kINPUTMUX_CtInp7ToTimer3Trigger     = 7U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
768     kINPUTMUX_CtInp8ToTimer3Trigger     = 8U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
769     kINPUTMUX_CtInp9ToTimer3Trigger     = 9U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
770     kINPUTMUX_CtInp10ToTimer3Trigger    = 10U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
771     kINPUTMUX_CtInp11ToTimer3Trigger    = 11U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
772     kINPUTMUX_CtInp12ToTimer3Trigger    = 12U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
773     kINPUTMUX_CtInp13ToTimer3Trigger    = 13U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
774     kINPUTMUX_CtInp14ToTimer3Trigger    = 14U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
775     kINPUTMUX_CtInp15ToTimer3Trigger    = 15U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
776     kINPUTMUX_Sai0TxSyncToTimer3Trigger = 16U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
777     kINPUTMUX_Sai0RxSyncToTimer3Trigger = 17U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
778     kINPUTMUX_Sai1TxSyncToTimer3Trigger = 18U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
779     kINPUTMUX_Sai1RxSyncToTimer3Trigger = 19U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
780     kINPUTMUX_Sai2TxSyncToTimer3Trigger = 20U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
781     kINPUTMUX_Sai2RxSyncToTimer3Trigger = 21U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
782     kINPUTMUX_Usb0SofToTimer3Trigger    = 22U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
783     kINPUTMUX_Usb1SofToTimer3Trigger    = 23U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
784     kINPUTMUX_Cmp0OutToTimer3Trigger    = 24U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
785     kINPUTMUX_Adc0Tcomp0ToTimer3Trigger = 25U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
786     kINPUTMUX_Adc0Tcomp1ToTimer3Trigger = 26U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
787     kINPUTMUX_TmprOut0ToTimer3Trigger   = 27U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
788     kINPUTMUX_TmprOut1ToTimer3Trigger   = 28U + (CT32BIT3_TRIG_PMUX_ID << PMUX_SHIFT),
789 
790     /*!< CTmier4 Input trigger mux. */
791     kINPUTMUX_CtInp0ToTimer4Trigger     = 0U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
792     kINPUTMUX_CtInp1ToTimer4Trigger     = 1U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
793     kINPUTMUX_CtInp2ToTimer4Trigger     = 2U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
794     kINPUTMUX_CtInp3ToTimer4Trigger     = 3U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
795     kINPUTMUX_CtInp4ToTimer4Trigger     = 4U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
796     kINPUTMUX_CtInp5ToTimer4Trigger     = 5U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
797     kINPUTMUX_CtInp6ToTimer4Trigger     = 6U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
798     kINPUTMUX_CtInp7ToTimer4Trigger     = 7U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
799     kINPUTMUX_CtInp8ToTimer4Trigger     = 8U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
800     kINPUTMUX_CtInp9ToTimer4Trigger     = 9U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
801     kINPUTMUX_CtInp10ToTimer4Trigger    = 10U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
802     kINPUTMUX_CtInp11ToTimer4Trigger    = 11U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
803     kINPUTMUX_CtInp12ToTimer4Trigger    = 12U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
804     kINPUTMUX_CtInp13ToTimer4Trigger    = 13U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
805     kINPUTMUX_CtInp14ToTimer4Trigger    = 14U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
806     kINPUTMUX_CtInp15ToTimer4Trigger    = 15U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
807     kINPUTMUX_Sai0TxSyncToTimer4Trigger = 16U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
808     kINPUTMUX_Sai0RxSyncToTimer4Trigger = 17U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
809     kINPUTMUX_Sai1TxSyncToTimer4Trigger = 18U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
810     kINPUTMUX_Sai1RxSyncToTimer4Trigger = 19U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
811     kINPUTMUX_Sai2TxSyncToTimer4Trigger = 20U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
812     kINPUTMUX_Sai2RxSyncToTimer4Trigger = 21U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
813     kINPUTMUX_Usb0SofToTimer4Trigger    = 22U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
814     kINPUTMUX_Usb1SofToTimer4Trigger    = 23U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
815     kINPUTMUX_Cmp0OutToTimer4Trigger    = 24U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
816     kINPUTMUX_Adc0Tcomp0ToTimer4Trigger = 25U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
817     kINPUTMUX_Adc0Tcomp1ToTimer4Trigger = 26U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
818     kINPUTMUX_TmprOut0ToTimer4Trigger   = 27U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
819     kINPUTMUX_TmprOut1ToTimer4Trigger   = 28U + (CT32BIT4_TRIG_PMUX_ID << PMUX_SHIFT),
820 
821     /*!< Frequency measurement reference clock. */
822     kINPUTMUX_OscClkToFreqmeasRef         = 0U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
823     kINPUTMUX_Fro1Div8ToFreqmeasRef       = 1U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
824     kINPUTMUX_Fro1ToFreqmeasRef           = 2U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
825     kINPUTMUX_LposcToFreqmeasRef          = 3U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
826     kINPUTMUX_32KhzOscToFreqmeasRef       = 4U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
827     kINPUTMUX_Fro0ToFreqmeasRef           = 6U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
828     kINPUTMUX_Fro2ToFreqmeasRef           = 7U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
829     kINPUTMUX_FreqmeGpioAClkToFreqmeasRef = 8U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
830     kINPUTMUX_FreqmeGpioBClkToFreqmeasRef = 9U + (FREQME_REF_PMUX_ID << PMUX_SHIFT),
831 
832     /*!< Frequency measurement target clock. */
833     kINPUTMUX_OscClkToFreqmeasTar         = 0U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
834     kINPUTMUX_Fro1Div8ToFreqmeasTar       = 1U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
835     kINPUTMUX_Fro1ToFreqmeasTar           = 2U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
836     kINPUTMUX_LposcToFreqmeasTar          = 3U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
837     kINPUTMUX_32KhzOscToFreqmeasTar       = 4U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
838     kINPUTMUX_Fro0ToFreqmeasTar           = 6U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
839     kINPUTMUX_Fro2ToFreqmeasTar           = 7U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
840     kINPUTMUX_FreqmeGpioAClkToFreqmeasTar = 8U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
841     kINPUTMUX_FreqmeGpioBClkToFreqmeasTar = 9U + (FREQME_TAR_PMUX_ID << PMUX_SHIFT),
842 
843     /*!< EZHV input mux. */
844     kINPUTMUX_GpioInt0Trig0ToEzhv    = 0U + (EZHV_PMUX_ID << PMUX_SHIFT),
845     kINPUTMUX_GpioInt0Trig1ToEzhv    = 1U + (EZHV_PMUX_ID << PMUX_SHIFT),
846     kINPUTMUX_GpioInt1Trig0ToEzhv    = 2U + (EZHV_PMUX_ID << PMUX_SHIFT),
847     kINPUTMUX_GpioInt1Trig1ToEzhv    = 3U + (EZHV_PMUX_ID << PMUX_SHIFT),
848     kINPUTMUX_GpioInt2Trig0ToEzhv    = 4U + (EZHV_PMUX_ID << PMUX_SHIFT),
849     kINPUTMUX_GpioInt2Trig1ToEzhv    = 5U + (EZHV_PMUX_ID << PMUX_SHIFT),
850     kINPUTMUX_GpioInt3Trig0ToEzhv    = 6U + (EZHV_PMUX_ID << PMUX_SHIFT),
851     kINPUTMUX_GpioInt3Trig1ToEzhv    = 7U + (EZHV_PMUX_ID << PMUX_SHIFT),
852     kINPUTMUX_GpioInt4Trig0ToEzhv    = 8U + (EZHV_PMUX_ID << PMUX_SHIFT),
853     kINPUTMUX_GpioInt4Trig1ToEzhv    = 9U + (EZHV_PMUX_ID << PMUX_SHIFT),
854     kINPUTMUX_GpioInt5Trig0ToEzhv    = 10U + (EZHV_PMUX_ID << PMUX_SHIFT),
855     kINPUTMUX_GpioInt5Trig1ToEzhv    = 11U + (EZHV_PMUX_ID << PMUX_SHIFT),
856     kINPUTMUX_GpioInt6Trig0ToEzhv    = 12U + (EZHV_PMUX_ID << PMUX_SHIFT),
857     kINPUTMUX_GpioInt6Trig1ToEzhv    = 13U + (EZHV_PMUX_ID << PMUX_SHIFT),
858     kINPUTMUX_GpioInt7Trig0ToEzhv    = 14U + (EZHV_PMUX_ID << PMUX_SHIFT),
859     kINPUTMUX_GpioInt7Trig1ToEzhv    = 15U + (EZHV_PMUX_ID << PMUX_SHIFT),
860     kINPUTMUX_Flexcomm0IrqToEzhv     = 16U + (EZHV_PMUX_ID << PMUX_SHIFT),
861     kINPUTMUX_Flexcomm1IrqToEzhv     = 17U + (EZHV_PMUX_ID << PMUX_SHIFT),
862     kINPUTMUX_Flexcomm2IrqToEzhv     = 18U + (EZHV_PMUX_ID << PMUX_SHIFT),
863     kINPUTMUX_Flexcomm3IrqToEzhv     = 19U + (EZHV_PMUX_ID << PMUX_SHIFT),
864     kINPUTMUX_Flexcomm4IrqToEzhv     = 20U + (EZHV_PMUX_ID << PMUX_SHIFT),
865     kINPUTMUX_Flexcomm5IrqToEzhv     = 21U + (EZHV_PMUX_ID << PMUX_SHIFT),
866     kINPUTMUX_Flexcomm6IrqToEzhv     = 22U + (EZHV_PMUX_ID << PMUX_SHIFT),
867     kINPUTMUX_Flexcomm7IrqToEzhv     = 23U + (EZHV_PMUX_ID << PMUX_SHIFT),
868     kINPUTMUX_Flexcomm14IrqToEzhv    = 24U + (EZHV_PMUX_ID << PMUX_SHIFT),
869     kINPUTMUX_Flexcomm16IrqToEzhv    = 25U + (EZHV_PMUX_ID << PMUX_SHIFT),
870     kINPUTMUX_I3c0IrqToEzhv          = 26U + (EZHV_PMUX_ID << PMUX_SHIFT),
871     kINPUTMUX_I3c1IrqToEzhv          = 27U + (EZHV_PMUX_ID << PMUX_SHIFT),
872     kINPUTMUX_I3c2IrqToEzhv          = 28U + (EZHV_PMUX_ID << PMUX_SHIFT),
873     kINPUTMUX_I3c3IrqToEzhv          = 29U + (EZHV_PMUX_ID << PMUX_SHIFT),
874     kINPUTMUX_FlexioIrqToEzhv        = 30U + (EZHV_PMUX_ID << PMUX_SHIFT),
875     kINPUTMUX_Gpio0IrqToEzhv         = 31U + (EZHV_PMUX_ID << PMUX_SHIFT),
876     kINPUTMUX_Gpio1IrqToEzhv         = 32U + (EZHV_PMUX_ID << PMUX_SHIFT),
877     kINPUTMUX_Gpio2IrqToEzhv         = 33U + (EZHV_PMUX_ID << PMUX_SHIFT),
878     kINPUTMUX_Gpio3IrqToEzhv         = 34U + (EZHV_PMUX_ID << PMUX_SHIFT),
879     kINPUTMUX_Gpio4IrqToEzhv         = 35U + (EZHV_PMUX_ID << PMUX_SHIFT),
880     kINPUTMUX_Gpio5IrqToEzhv         = 36U + (EZHV_PMUX_ID << PMUX_SHIFT),
881     kINPUTMUX_Gpio6IrqToEzhv         = 37U + (EZHV_PMUX_ID << PMUX_SHIFT),
882     kINPUTMUX_Gpio7IrqToEzhv         = 38U + (EZHV_PMUX_ID << PMUX_SHIFT),
883     kINPUTMUX_Gpio8IrqToEzhv         = 39U + (EZHV_PMUX_ID << PMUX_SHIFT),
884     kINPUTMUX_Gpio9IrqToEzhv         = 40U + (EZHV_PMUX_ID << PMUX_SHIFT),
885     kINPUTMUX_Gpio10IrqToEzhv        = 41U + (EZHV_PMUX_ID << PMUX_SHIFT),
886     kINPUTMUX_Sct0IrqToEzhv          = 42U + (EZHV_PMUX_ID << PMUX_SHIFT),
887     kINPUTMUX_Ctimer0IrqToEzhv       = 43U + (EZHV_PMUX_ID << PMUX_SHIFT),
888     kINPUTMUX_Ctimer1IrqToEzhv       = 44U + (EZHV_PMUX_ID << PMUX_SHIFT),
889     kINPUTMUX_Ctimer2IrqToEzhv       = 45U + (EZHV_PMUX_ID << PMUX_SHIFT),
890     kINPUTMUX_Ctimer3IrqToEzhv       = 46U + (EZHV_PMUX_ID << PMUX_SHIFT),
891     kINPUTMUX_Ctimer4IrqToEzhv       = 47U + (EZHV_PMUX_ID << PMUX_SHIFT),
892     kINPUTMUX_Ctimer5IrqToEzhv       = 48U + (EZHV_PMUX_ID << PMUX_SHIFT),
893     kINPUTMUX_Ctimer6IrqToEzhv       = 49U + (EZHV_PMUX_ID << PMUX_SHIFT),
894     kINPUTMUX_Ctimer7IrqToEzhv       = 50U + (EZHV_PMUX_ID << PMUX_SHIFT),
895     kINPUTMUX_Utick0IrqToEzhv        = 51U + (EZHV_PMUX_ID << PMUX_SHIFT),
896     kINPUTMUX_Mrt0IrqToEzhv          = 52U + (EZHV_PMUX_ID << PMUX_SHIFT),
897     kINPUTMUX_Rtc0IrqToEzhv          = 53U + (EZHV_PMUX_ID << PMUX_SHIFT),
898     kINPUTMUX_OsEventIrqToEzhv       = 54U + (EZHV_PMUX_ID << PMUX_SHIFT),
899     kINPUTMUX_Wdt0IrqToEzhv          = 55U + (EZHV_PMUX_ID << PMUX_SHIFT),
900     kINPUTMUX_Wdt1IrqToEzhv          = 56U + (EZHV_PMUX_ID << PMUX_SHIFT),
901     kINPUTMUX_Adc0IrqToEzhv          = 57U + (EZHV_PMUX_ID << PMUX_SHIFT),
902     kINPUTMUX_AcmpIrqToEzhv          = 58U + (EZHV_PMUX_ID << PMUX_SHIFT),
903     kINPUTMUX_MicfilIrqToEzhv        = 59U + (EZHV_PMUX_ID << PMUX_SHIFT),
904     kINPUTMUX_HwvadToEzhv            = 60U + (EZHV_PMUX_ID << PMUX_SHIFT),
905     kINPUTMUX_Sdio0IrqToEzhv         = 61U + (EZHV_PMUX_ID << PMUX_SHIFT),
906     kINPUTMUX_Sdio1IrqToEzhv         = 62U + (EZHV_PMUX_ID << PMUX_SHIFT),
907     kINPUTMUX_Usb0IrqToEzhv          = 63U + (EZHV_PMUX_ID << PMUX_SHIFT),
908     kINPUTMUX_Usb1IrqToEzhv          = 64U + (EZHV_PMUX_ID << PMUX_SHIFT),
909     kINPUTMUX_LcdifIrqToEzhv         = 65U + (EZHV_PMUX_ID << PMUX_SHIFT),
910     kINPUTMUX_GpuIrqToEzhv           = 66U + (EZHV_PMUX_ID << PMUX_SHIFT),
911     kINPUTMUX_Dma0Ch0IrqToEzhv       = 67U + (EZHV_PMUX_ID << PMUX_SHIFT),
912     kINPUTMUX_Dma0Ch1IrqToEzhv       = 68U + (EZHV_PMUX_ID << PMUX_SHIFT),
913     kINPUTMUX_Dma0Ch2IrqToEzhv       = 69U + (EZHV_PMUX_ID << PMUX_SHIFT),
914     kINPUTMUX_Dma0Ch3IrqToEzhv       = 70U + (EZHV_PMUX_ID << PMUX_SHIFT),
915     kINPUTMUX_Dma1Ch0IrqToEzhv       = 71U + (EZHV_PMUX_ID << PMUX_SHIFT),
916     kINPUTMUX_Dma1Ch1IrqToEzhv       = 72U + (EZHV_PMUX_ID << PMUX_SHIFT),
917     kINPUTMUX_Dma1Ch2IrqToEzhv       = 73U + (EZHV_PMUX_ID << PMUX_SHIFT),
918     kINPUTMUX_Dma1Ch3IrqToEzhv       = 74U + (EZHV_PMUX_ID << PMUX_SHIFT),
919     kINPUTMUX_Dma2Ch0IrqToEzhv       = 75U + (EZHV_PMUX_ID << PMUX_SHIFT),
920     kINPUTMUX_Dma2Ch1IrqToEzhv       = 76U + (EZHV_PMUX_ID << PMUX_SHIFT),
921     kINPUTMUX_Dma2Ch2IrqToEzhv       = 77U + (EZHV_PMUX_ID << PMUX_SHIFT),
922     kINPUTMUX_Dma2Ch3IrqToEzhv       = 78U + (EZHV_PMUX_ID << PMUX_SHIFT),
923     kINPUTMUX_Dma3Ch0IrqToEzhv       = 79U + (EZHV_PMUX_ID << PMUX_SHIFT),
924     kINPUTMUX_Dma3Ch1IrqToEzhv       = 80U + (EZHV_PMUX_ID << PMUX_SHIFT),
925     kINPUTMUX_Dma3Ch2IrqToEzhv       = 81U + (EZHV_PMUX_ID << PMUX_SHIFT),
926     kINPUTMUX_Dma3Ch3IrqToEzhv       = 82U + (EZHV_PMUX_ID << PMUX_SHIFT),
927     kINPUTMUX_Dsp0TieExpstate1ToEzhv = 83U + (EZHV_PMUX_ID << PMUX_SHIFT),
928     kINPUTMUX_Dsp1TieExpstate1ToEzhv = 84U + (EZHV_PMUX_ID << PMUX_SHIFT),
929     kINPUTMUX_SctOut8ToEzhv          = 85U + (EZHV_PMUX_ID << PMUX_SHIFT),
930     kINPUTMUX_SctOut9ToEzhv          = 86U + (EZHV_PMUX_ID << PMUX_SHIFT),
931     kINPUTMUX_Ct4Mat3ToEzhv          = 87U + (EZHV_PMUX_ID << PMUX_SHIFT),
932     kINPUTMUX_Ct4Mat2ToEzhv          = 88U + (EZHV_PMUX_ID << PMUX_SHIFT),
933     kINPUTMUX_Ct3Mat3ToEzhv          = 89U + (EZHV_PMUX_ID << PMUX_SHIFT),
934     kINPUTMUX_Ct3Mat2ToEzhv          = 90U + (EZHV_PMUX_ID << PMUX_SHIFT),
935     kINPUTMUX_Cpu0TxevToEzhv         = 91U + (EZHV_PMUX_ID << PMUX_SHIFT),
936     kINPUTMUX_GpioInt0BmatchToEzhv   = 92U + (EZHV_PMUX_ID << PMUX_SHIFT),
937     kINPUTMUX_MipiIrqToEzhv          = 93U + (EZHV_PMUX_ID << PMUX_SHIFT),
938     kINPUTMUX_Usb0SofToEzhv          = 94U + (EZHV_PMUX_ID << PMUX_SHIFT),
939     kINPUTMUX_Usb1SofToEzhv          = 95U + (EZHV_PMUX_ID << PMUX_SHIFT),
940     kINPUTMUX_TmprOut0ToEzhv         = 96U + (EZHV_PMUX_ID << PMUX_SHIFT),
941     kINPUTMUX_TmprOut1ToEzhv         = 97U + (EZHV_PMUX_ID << PMUX_SHIFT),
942 
943     /* FLEXIO0 input mux */
944     kINPUTMUX_CtInp0ToFlexio0         = 0U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
945     kINPUTMUX_CtInp1ToFlexio0         = 1U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
946     kINPUTMUX_CtInp2ToFlexio0         = 2U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
947     kINPUTMUX_CtInp3ToFlexio0         = 3U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
948     kINPUTMUX_Sct0Out6ToFlexio0       = 4U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
949     kINPUTMUX_Sct0Out7ToFlexio0       = 5U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
950     kINPUTMUX_Sct0Out8ToFlexio0       = 6U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
951     kINPUTMUX_Ct0Mat3ToFlexio0        = 7U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
952     kINPUTMUX_Ct1Mat3ToFlexio0        = 8U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
953     kINPUTMUX_Ct2Mat3ToFlexio0        = 9U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
954     kINPUTMUX_Ct3Mat3ToFlexio0        = 10U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
955     kINPUTMUX_Ct4Mat3ToFlexio0        = 11U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
956     kINPUTMUX_GpioInt0BmatchToFlexio0 = 12U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
957     kINPUTMUX_Cmp0OutToFlexio0        = 13U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
958     kINPUTMUX_EzhvOutToFlexio0        = 14U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
959     kINPUTMUX_Rtc0IrqOutToFlexio0     = 15U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
960     kINPUTMUX_Gpio0Irq0ToFlexio0      = 16U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
961     kINPUTMUX_Gpio0Irq1ToFlexio0      = 17U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
962     kINPUTMUX_Gpio1Irq0ToFlexio0      = 18U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
963     kINPUTMUX_Gpio1Irq1ToFlexio0      = 19U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
964     kINPUTMUX_Gpio2Irq0ToFlexio0      = 20U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
965     kINPUTMUX_Gpio2Irq1ToFlexio0      = 21U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
966     kINPUTMUX_Gpio3Irq0ToFlexio0      = 22U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
967     kINPUTMUX_Gpio3Irq1ToFlexio0      = 23U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
968     kINPUTMUX_Gpio4Irq0ToFlexio0      = 24U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
969     kINPUTMUX_Gpio4Irq1ToFlexio0      = 25U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
970     kINPUTMUX_Gpio5Irq0ToFlexio0      = 26U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
971     kINPUTMUX_Gpio5Irq1ToFlexio0      = 27U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
972     kINPUTMUX_Gpio6Irq0ToFlexio0      = 28U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
973     kINPUTMUX_Gpio6Irq1ToFlexio0      = 29U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
974     kINPUTMUX_Gpio7Irq0ToFlexio0      = 30U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
975     kINPUTMUX_Gpio7Irq1ToFlexio0      = 31U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
976     kINPUTMUX_Gpio8Irq0ToFlexio0      = 32U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
977     kINPUTMUX_Gpio8Irq1ToFlexio0      = 33U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
978     kINPUTMUX_Gpio9Irq0ToFlexio0      = 34U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
979     kINPUTMUX_Gpio9Irq1ToFlexio0      = 35U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
980     kINPUTMUX_Gpio10Irq0ToFlexio0     = 36U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
981     kINPUTMUX_Gpio10Irq1ToFlexio0     = 37U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
982     kINPUTMUX_TmprOut0ToFlexio0       = 38U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
983     kINPUTMUX_TmprOut1ToFlexio0       = 39U + (FLEXIO_PMUX_ID << PMUX_SHIFT),
984 #else
985     kINPUTMUX_GpioPort8Pin0ToPintsel   = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
986     kINPUTMUX_GpioPort8Pin1ToPintsel   = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
987     kINPUTMUX_GpioPort8Pin2ToPintsel   = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
988     kINPUTMUX_GpioPort8Pin3ToPintsel   = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
989     kINPUTMUX_GpioPort8Pin4ToPintsel   = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
990     kINPUTMUX_GpioPort8Pin5ToPintsel   = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
991     kINPUTMUX_GpioPort8Pin6ToPintsel   = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
992     kINPUTMUX_GpioPort8Pin7ToPintsel   = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
993     kINPUTMUX_GpioPort8Pin8ToPintsel   = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
994     kINPUTMUX_GpioPort8Pin9ToPintsel   = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
995     kINPUTMUX_GpioPort8Pin10ToPintsel  = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
996     kINPUTMUX_GpioPort8Pin11ToPintsel  = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
997     kINPUTMUX_GpioPort8Pin12ToPintsel  = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
998     kINPUTMUX_GpioPort8Pin13ToPintsel  = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
999     kINPUTMUX_GpioPort8Pin14ToPintsel  = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1000     kINPUTMUX_GpioPort8Pin15ToPintsel  = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1001     kINPUTMUX_GpioPort8Pin16ToPintsel  = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1002     kINPUTMUX_GpioPort8Pin17ToPintsel  = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1003     kINPUTMUX_GpioPort8Pin18ToPintsel  = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1004     kINPUTMUX_GpioPort8Pin19ToPintsel  = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1005     kINPUTMUX_GpioPort8Pin20ToPintsel  = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1006     kINPUTMUX_GpioPort8Pin21ToPintsel  = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1007     kINPUTMUX_GpioPort8Pin22ToPintsel  = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1008     kINPUTMUX_GpioPort8Pin23ToPintsel  = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1009     kINPUTMUX_GpioPort8Pin24ToPintsel  = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1010     kINPUTMUX_GpioPort8Pin25ToPintsel  = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1011     kINPUTMUX_GpioPort8Pin26ToPintsel  = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1012     kINPUTMUX_GpioPort8Pin27ToPintsel  = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1013     kINPUTMUX_GpioPort8Pin28ToPintsel  = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1014     kINPUTMUX_GpioPort8Pin29ToPintsel  = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1015     kINPUTMUX_GpioPort8Pin30ToPintsel  = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1016     kINPUTMUX_GpioPort8Pin31ToPintsel  = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1017     kINPUTMUX_GpioPort10Pin0ToPintsel  = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1018     kINPUTMUX_GpioPort10Pin1ToPintsel  = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1019     kINPUTMUX_GpioPort10Pin2ToPintsel  = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1020     kINPUTMUX_GpioPort10Pin3ToPintsel  = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1021     kINPUTMUX_GpioPort10Pin4ToPintsel  = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1022     kINPUTMUX_GpioPort10Pin5ToPintsel  = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1023     kINPUTMUX_GpioPort10Pin6ToPintsel  = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1024     kINPUTMUX_GpioPort10Pin7ToPintsel  = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1025     kINPUTMUX_GpioPort10Pin8ToPintsel  = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1026     kINPUTMUX_GpioPort10Pin9ToPintsel  = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1027     kINPUTMUX_GpioPort10Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1028     kINPUTMUX_GpioPort10Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1029     kINPUTMUX_GpioPort10Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1030     kINPUTMUX_GpioPort10Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1031     kINPUTMUX_GpioPort10Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1032     kINPUTMUX_GpioPort10Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1033     kINPUTMUX_GpioPort10Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1034     kINPUTMUX_GpioPort10Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
1035 
1036     /*!< DSP Interrupt. */
1037     kINPUTMUX_Flexcomm17ToDspInterrupt   = 0U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1038     kINPUTMUX_Flexcomm18ToDspInterrupt   = 1U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1039     kINPUTMUX_Flexcomm19ToDspInterrupt   = 2U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1040     kINPUTMUX_Flexcomm20ToDspInterrupt   = 3U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1041     kINPUTMUX_Pmc1ToDspInterrupt         = 4U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1042     kINPUTMUX_Gpio8Irq0ToDspInterrupt    = 7U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1043     kINPUTMUX_Gpio8Irq1ToDspInterrupt    = 8U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1044     kINPUTMUX_Gpio9Irq0ToDspInterrupt    = 9U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1045     kINPUTMUX_Gpio9Irq1ToDspInterrupt    = 10U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1046     kINPUTMUX_Gpio10Irq0ToDspInterrupt   = 11U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1047     kINPUTMUX_Gpio10Irq1ToDspInterrupt   = 12U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1048     kINPUTMUX_Wdt2ToDspInterrupt         = 13U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1049     kINPUTMUX_Wdt3ToDspInterrupt         = 14U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1050     kINPUTMUX_Mu0BToDspInterrupt         = 15U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1051     kINPUTMUX_Mu3BToDspInterrupt         = 16U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1052     kINPUTMUX_Utick1ToDspInterrupt       = 17U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1053     kINPUTMUX_Mrt1ToDspInterrupt         = 18U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1054     kINPUTMUX_OsEventTimerToDspInterrupt = 19U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1055     kINPUTMUX_Ctimer5ToDspInterrupt      = 20U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1056     kINPUTMUX_Ctimer6ToDspInterrupt      = 21U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1057     kINPUTMUX_Ctimer7ToDspInterrupt      = 22U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1058     kINPUTMUX_Rtc1AlarmToDspInterrupt    = 23U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1059     kINPUTMUX_Rtc1WakeupToDspInterrupt   = 24U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1060     kINPUTMUX_I3c2ToDspInterrupt         = 25U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1061     kINPUTMUX_I3c3ToDspInterrupt         = 26U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1062     kINPUTMUX_MicfilToDspInterrupt       = 27U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1063     kINPUTMUX_HwvadToDspInterrupt        = 28U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1064     kINPUTMUX_Dma2Irq0ToDspInterrupt     = 34U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1065     kINPUTMUX_Dma2Irq1ToDspInterrupt     = 35U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1066     kINPUTMUX_Dma2Irq2ToDspInterrupt     = 36U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1067     kINPUTMUX_Dma2Irq3ToDspInterrupt     = 37U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1068     kINPUTMUX_Dma2Irq4ToDspInterrupt     = 38U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1069     kINPUTMUX_Dma2Irq5ToDspInterrupt     = 39U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1070     kINPUTMUX_Dma2Irq6ToDspInterrupt     = 40U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1071     kINPUTMUX_Dma2Irq7ToDspInterrupt     = 41U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1072     kINPUTMUX_Dma3Irq0ToDspInterrupt     = 42U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1073     kINPUTMUX_Dma3Irq1ToDspInterrupt     = 43U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1074     kINPUTMUX_Dma3Irq2ToDspInterrupt     = 44U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1075     kINPUTMUX_Dma3Irq3ToDspInterrupt     = 45U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1076     kINPUTMUX_Dma3Irq4ToDspInterrupt     = 46U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1077     kINPUTMUX_Dma3Irq5ToDspInterrupt     = 47U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1078     kINPUTMUX_Dma3Irq6ToDspInterrupt     = 48U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1079     kINPUTMUX_Dma3Irq7ToDspInterrupt     = 49U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1080     kINPUTMUX_GpioInt0ToDspInterrupt     = 50U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1081     kINPUTMUX_GpioInt1ToDspInterrupt     = 51U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1082     kINPUTMUX_GpioInt2ToDspInterrupt     = 52U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1083     kINPUTMUX_GpioInt3ToDspInterrupt     = 53U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1084     kINPUTMUX_Sai3ToDspInterrupt         = 54U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
1085 
1086     /* FLEXCOMM17 TRIG input mux */
1087     kINPUTMUX_CtInp0ToFlexcomm17         = 0U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1088     kINPUTMUX_CtInp1ToFlexcomm17         = 1U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1089     kINPUTMUX_CtInp2ToFlexcomm17         = 2U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1090     kINPUTMUX_CtInp3ToFlexcomm17         = 3U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1091     kINPUTMUX_Ct5Mat3ToFlexcomm17        = 7U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1092     kINPUTMUX_Ct6Mat3ToFlexcomm17        = 8U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1093     kINPUTMUX_Ct7Mat3ToFlexcomm17        = 9U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1094     kINPUTMUX_GpioInt1BMatchToFlexcomm17 = 12U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1095     kINPUTMUX_Cmp0OutToFlexcomm17        = 13U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1096     kINPUTMUX_Rtc0IrqToFlexcomm17        = 14U + (FLEXCOMM17_ITRIG_PMUX_ID << PMUX_SHIFT),
1097 
1098     /* FLEXCOMM18 TRIG input mux */
1099     kINPUTMUX_CtInp0ToFlexcomm18         = 0U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1100     kINPUTMUX_CtInp1ToFlexcomm18         = 1U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1101     kINPUTMUX_CtInp2ToFlexcomm18         = 2U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1102     kINPUTMUX_CtInp3ToFlexcomm18         = 3U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1103     kINPUTMUX_Ct5Mat3ToFlexcomm18        = 7U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1104     kINPUTMUX_Ct6Mat3ToFlexcomm18        = 8U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1105     kINPUTMUX_Ct7Mat3ToFlexcomm18        = 9U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1106     kINPUTMUX_GpioInt1BMatchToFlexcomm18 = 12U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1107     kINPUTMUX_Cmp0OutToFlexcomm18        = 13U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1108     kINPUTMUX_Rtc0IrqToFlexcomm18        = 14U + (FLEXCOMM18_ITRIG_PMUX_ID << PMUX_SHIFT),
1109 
1110     /* FLEXCOMM19 TRIG input mux */
1111     kINPUTMUX_CtInp0ToFlexcomm19         = 0U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1112     kINPUTMUX_CtInp1ToFlexcomm19         = 1U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1113     kINPUTMUX_CtInp2ToFlexcomm19         = 2U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1114     kINPUTMUX_CtInp3ToFlexcomm19         = 3U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1115     kINPUTMUX_Ct5Mat3ToFlexcomm19        = 7U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1116     kINPUTMUX_Ct6Mat3ToFlexcomm19        = 8U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1117     kINPUTMUX_Ct7Mat3ToFlexcomm19        = 9U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1118     kINPUTMUX_GpioInt1BMatchToFlexcomm19 = 12U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1119     kINPUTMUX_Cmp0OutToFlexcomm19        = 13U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1120     kINPUTMUX_Rtc0IrqToFlexcomm19        = 14U + (FLEXCOMM19_ITRIG_PMUX_ID << PMUX_SHIFT),
1121 
1122     /* FLEXCOMM20 TRIG input mux */
1123     kINPUTMUX_CtInp0ToFlexcomm20         = 0U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1124     kINPUTMUX_CtInp1ToFlexcomm20         = 1U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1125     kINPUTMUX_CtInp2ToFlexcomm20         = 2U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1126     kINPUTMUX_CtInp3ToFlexcomm20         = 3U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1127     kINPUTMUX_Ct5Mat3ToFlexcomm20        = 7U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1128     kINPUTMUX_Ct6Mat3ToFlexcomm20        = 8U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1129     kINPUTMUX_Ct7Mat3ToFlexcomm20        = 9U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1130     kINPUTMUX_GpioInt1BMatchToFlexcomm20 = 12U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1131     kINPUTMUX_Cmp0OutToFlexcomm20        = 13U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1132     kINPUTMUX_Rtc0IrqToFlexcomm20        = 14U + (FLEXCOMM20_ITRIG_PMUX_ID << PMUX_SHIFT),
1133 
1134     /* ADC0 TRIG input mux */
1135     kINPUTMUX_Gpio0Irq0ToAdc0      = 0U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1136     kINPUTMUX_Gpio1Irq0ToAdc0      = 1U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1137     kINPUTMUX_Gpio2Irq0ToAdc0      = 2U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1138     kINPUTMUX_Gpio3Irq0ToAdc0      = 3U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1139     kINPUTMUX_Gpio4Irq0ToAdc0      = 4U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1140     kINPUTMUX_Gpio5Irq0ToAdc0      = 5U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1141     kINPUTMUX_Gpio6Irq0ToAdc0      = 6U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1142     kINPUTMUX_Gpio7Irq0ToAdc0      = 7U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1143     kINPUTMUX_Gpio8Irq0ToAdc0      = 8U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1144     kINPUTMUX_Gpio9Irq0ToAdc0      = 9U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1145     kINPUTMUX_Gpio10Irq0ToAdc0     = 10U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1146     kINPUTMUX_Sct0Out4ToAdc0       = 11U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1147     kINPUTMUX_Sct0Out5ToAdc0       = 12U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1148     kINPUTMUX_Sct0Out9ToAdc0       = 13U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1149     kINPUTMUX_Ct0Mat3ToAdc0        = 14U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1150     kINPUTMUX_Ct1Mat3ToAdc0        = 15U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1151     kINPUTMUX_Ct2Mat3ToAdc0        = 16U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1152     kINPUTMUX_Ct3Mat3ToAdc0        = 17U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1153     kINPUTMUX_Ct4Mat3ToAdc0        = 18U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1154     kINPUTMUX_Ct5Mat3ToAdc0        = 19U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1155     kINPUTMUX_Ct6Mat3ToAdc0        = 20U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1156     kINPUTMUX_Ct7Mat3ToAdc0        = 21U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1157     kINPUTMUX_Cmp0OutToAdc0        = 22U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1158     kINPUTMUX_Cpu0TxevToAdc0       = 23U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1159     kINPUTMUX_Cpu1TxevToAdc0       = 24U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1160     kINPUTMUX_EzhvOutToAdc0        = 25U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1161     kINPUTMUX_GpioInt0BmatchToAdc0 = 26U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1162     kINPUTMUX_GpioInt1BmatchToAdc0 = 27U + (ADC0_TRIG_PMUX_ID << PMUX_SHIFT),
1163 
1164     /*!< CTmier5 capture input mux. */
1165     kINPUTMUX_CtInp0ToTimer5CaptureChannels     = 0U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1166     kINPUTMUX_CtInp1ToTimer5CaptureChannels     = 1U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1167     kINPUTMUX_CtInp2ToTimer5CaptureChannels     = 2U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1168     kINPUTMUX_CtInp3ToTimer5CaptureChannels     = 3U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1169     kINPUTMUX_CtInp4ToTimer5CaptureChannels     = 4U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1170     kINPUTMUX_CtInp5ToTimer5CaptureChannels     = 5U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1171     kINPUTMUX_CtInp6ToTimer5CaptureChannels     = 6U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1172     kINPUTMUX_CtInp7ToTimer5CaptureChannels     = 7U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1173     kINPUTMUX_CtInp8ToTimer5CaptureChannels     = 8U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1174     kINPUTMUX_CtInp9ToTimer5CaptureChannels     = 9U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1175     kINPUTMUX_Sai3TxSyncToTimer5CaptureChannels = 16U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1176     kINPUTMUX_Sai3RxSyncToTimer5CaptureChannels = 17U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1177     kINPUTMUX_Cmp0OutToTimer5CaptureChannels    = 18U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1178     kINPUTMUX_Adc0Tcomp0ToTimer5CaptureChannels = 19U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1179     kINPUTMUX_Adc0Tcomp1ToTimer5CaptureChannels = 20U + (CT32BIT5_CAP_PMUX_ID << PMUX_SHIFT),
1180 
1181     /*!< CTmier6 capture input mux. */
1182     kINPUTMUX_CtInp0ToTimer6CaptureChannels     = 0U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1183     kINPUTMUX_CtInp1ToTimer6CaptureChannels     = 1U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1184     kINPUTMUX_CtInp2ToTimer6CaptureChannels     = 2U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1185     kINPUTMUX_CtInp3ToTimer6CaptureChannels     = 3U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1186     kINPUTMUX_CtInp4ToTimer6CaptureChannels     = 4U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1187     kINPUTMUX_CtInp5ToTimer6CaptureChannels     = 5U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1188     kINPUTMUX_CtInp6ToTimer6CaptureChannels     = 6U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1189     kINPUTMUX_CtInp7ToTimer6CaptureChannels     = 7U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1190     kINPUTMUX_CtInp8ToTimer6CaptureChannels     = 8U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1191     kINPUTMUX_CtInp9ToTimer6CaptureChannels     = 9U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1192     kINPUTMUX_Sai3TxSyncToTimer6CaptureChannels = 16U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1193     kINPUTMUX_Sai3RxSyncToTimer6CaptureChannels = 17U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1194     kINPUTMUX_Cmp0OutToTimer6CaptureChannels    = 18U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1195     kINPUTMUX_Adc0Tcomp0ToTimer6CaptureChannels = 19U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1196     kINPUTMUX_Adc0Tcomp1ToTimer6CaptureChannels = 20U + (CT32BIT6_CAP_PMUX_ID << PMUX_SHIFT),
1197 
1198     /*!< CTmier7 capture input mux. */
1199     kINPUTMUX_CtInp0ToTimer7CaptureChannels     = 0U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1200     kINPUTMUX_CtInp1ToTimer7CaptureChannels     = 1U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1201     kINPUTMUX_CtInp2ToTimer7CaptureChannels     = 2U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1202     kINPUTMUX_CtInp3ToTimer7CaptureChannels     = 3U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1203     kINPUTMUX_CtInp4ToTimer7CaptureChannels     = 4U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1204     kINPUTMUX_CtInp5ToTimer7CaptureChannels     = 5U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1205     kINPUTMUX_CtInp6ToTimer7CaptureChannels     = 6U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1206     kINPUTMUX_CtInp7ToTimer7CaptureChannels     = 7U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1207     kINPUTMUX_CtInp8ToTimer7CaptureChannels     = 8U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1208     kINPUTMUX_CtInp9ToTimer7CaptureChannels     = 9U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1209     kINPUTMUX_Sai3TxSyncToTimer7CaptureChannels = 16U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1210     kINPUTMUX_Sai3RxSyncToTimer7CaptureChannels = 17U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1211     kINPUTMUX_Cmp0OutToTimer7CaptureChannels    = 18U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1212     kINPUTMUX_Adc0Tcomp0ToTimer7CaptureChannels = 19U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1213     kINPUTMUX_Adc0Tcomp1ToTimer7CaptureChannels = 20U + (CT32BIT7_CAP_PMUX_ID << PMUX_SHIFT),
1214 
1215     /*!< CTmier5 input trigger. */
1216     kINPUTMUX_CtInp0ToTimer5Trigger     = 0U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1217     kINPUTMUX_CtInp1ToTimer5Trigger     = 1U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1218     kINPUTMUX_CtInp2ToTimer5Trigger     = 2U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1219     kINPUTMUX_CtInp3ToTimer5Trigger     = 3U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1220     kINPUTMUX_CtInp4ToTimer5Trigger     = 4U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1221     kINPUTMUX_CtInp5ToTimer5Trigger     = 5U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1222     kINPUTMUX_CtInp6ToTimer5Trigger     = 6U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1223     kINPUTMUX_CtInp7ToTimer5Trigger     = 7U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1224     kINPUTMUX_CtInp8ToTimer5Trigger     = 8U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1225     kINPUTMUX_CtInp9ToTimer5Trigger     = 9U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1226     kINPUTMUX_Sai3TxSyncToTimer5Trigger = 16U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1227     kINPUTMUX_Sai3RxSyncToTimer5Trigger = 17U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1228     kINPUTMUX_Cmp0OutToTimer5Trigger    = 18U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1229     kINPUTMUX_Adc0Tcomp0ToTimer5Trigger = 19U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1230     kINPUTMUX_Adc0Tcomp1ToTimer5Trigger = 20U + (CT32BIT5_TRIG_PMUX_ID << PMUX_SHIFT),
1231 
1232     /*!< CTmier6 input trigger. */
1233     kINPUTMUX_CtInp0ToTimer6Trigger     = 0U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1234     kINPUTMUX_CtInp1ToTimer6Trigger     = 1U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1235     kINPUTMUX_CtInp2ToTimer6Trigger     = 2U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1236     kINPUTMUX_CtInp3ToTimer6Trigger     = 3U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1237     kINPUTMUX_CtInp4ToTimer6Trigger     = 4U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1238     kINPUTMUX_CtInp5ToTimer6Trigger     = 5U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1239     kINPUTMUX_CtInp6ToTimer6Trigger     = 6U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1240     kINPUTMUX_CtInp7ToTimer6Trigger     = 7U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1241     kINPUTMUX_CtInp8ToTimer6Trigger     = 8U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1242     kINPUTMUX_CtInp9ToTimer6Trigger     = 9U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1243     kINPUTMUX_Sai3TxSyncToTimer6Trigger = 16U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1244     kINPUTMUX_Sai3RxSyncToTimer6Trigger = 17U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1245     kINPUTMUX_Cmp0OutToTimer6Trigger    = 18U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1246     kINPUTMUX_Adc0Tcomp0ToTimer6Trigger = 19U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1247     kINPUTMUX_Adc0Tcomp1ToTimer6Trigger = 20U + (CT32BIT6_TRIG_PMUX_ID << PMUX_SHIFT),
1248 
1249     /*!< CTmier7 input trigger. */
1250     kINPUTMUX_CtInp0ToTimer7Trigger     = 0U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1251     kINPUTMUX_CtInp1ToTimer7Trigger     = 1U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1252     kINPUTMUX_CtInp2ToTimer7Trigger     = 2U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1253     kINPUTMUX_CtInp3ToTimer7Trigger     = 3U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1254     kINPUTMUX_CtInp4ToTimer7Trigger     = 4U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1255     kINPUTMUX_CtInp5ToTimer7Trigger     = 5U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1256     kINPUTMUX_CtInp6ToTimer7Trigger     = 6U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1257     kINPUTMUX_CtInp7ToTimer7Trigger     = 7U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1258     kINPUTMUX_CtInp8ToTimer7Trigger     = 8U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1259     kINPUTMUX_CtInp9ToTimer7Trigger     = 9U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1260     kINPUTMUX_Sai3TxSyncToTimer7Trigger = 16U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1261     kINPUTMUX_Sai3RxSyncToTimer7Trigger = 17U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1262     kINPUTMUX_Cmp0OutToTimer7Trigger    = 18U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1263     kINPUTMUX_Adc0Tcomp0ToTimer7Trigger = 19U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1264     kINPUTMUX_Adc0Tcomp1ToTimer7Trigger = 20U + (CT32BIT7_TRIG_PMUX_ID << PMUX_SHIFT),
1265 #endif
1266 
1267 } inputmux_connection_t;
1268 
1269 /*@}*/
1270 
1271 #endif /* _FSL_INPUTMUX_CONNECTIONS_ */
1272