1 /*
2 * Copyright 2023 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_edma_soc.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.edma_soc"
18 #endif
19
20 #if defined(MIMXRT798S_hifi4_SERIES) || defined(MIMXRT798S_cm33_core0_SERIES) || \
21 defined(MIMXRT758S_cm33_core0_SERIES) || defined(MIMXRT735S_cm33_core0_SERIES)
22 #define SYSCON_BASE SYSCON0
23 #else
24 #define SYSCON_BASE SYSCON1
25 #endif
26
27 #define DMAC_EN_REG_OFFSET 0x420U
28 #define DMAC_EN_REG(instance, idx) \
29 ((volatile uint32_t *)((uint32_t)(SYSCON_BASE) + (DMAC_EN_REG_OFFSET) + 0x10U * (instance) + 4U * (idx)))
30 /*******************************************************************************
31 * Prototypes
32 ******************************************************************************/
33 extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel);
34 static DMA_Type *const s_edmaBases[] = EDMA_BASE_PTRS;
35 /*******************************************************************************
36 * Code
37 ******************************************************************************/
EDMA_GetInstance(DMA_Type * base)38 static uint32_t EDMA_GetInstance(DMA_Type *base)
39 {
40 uint32_t instance;
41
42 /* Find the instance index from base address mappings. */
43 for (instance = 0U; instance < ARRAY_SIZE(s_edmaBases); instance++)
44 {
45 if (s_edmaBases[instance] == base)
46 {
47 break;
48 }
49 }
50
51 assert(instance < ARRAY_SIZE(s_edmaBases));
52
53 return instance;
54 }
55
EDMA_EnableRequest(DMA_Type * base,dma_request_source_t requestSource)56 void EDMA_EnableRequest(DMA_Type *base, dma_request_source_t requestSource)
57 {
58 volatile uint32_t *reg;
59 uint32_t regIdx = (uint32_t)requestSource / 32U;
60
61 reg = DMAC_EN_REG(EDMA_GetInstance(base), regIdx);
62 *reg |= 0x1UL << ((uint32_t)requestSource % 32U);
63 }
64
EDMA_DisableRequest(DMA_Type * base,dma_request_source_t requestSource)65 void EDMA_DisableRequest(DMA_Type *base, dma_request_source_t requestSource)
66 {
67 volatile uint32_t *reg;
68 uint32_t regIdx = (uint32_t)requestSource / 32U;
69
70 reg = DMAC_EN_REG(EDMA_GetInstance(base), regIdx);
71 *reg &= ~(0x1UL << ((uint32_t)requestSource % 32U));
72 }
73
74 #if defined(DMA0)
75 /*!
76 * brief DMA instance 0, channel 0 IRQ handler.
77 *
78 */
79 extern void EDMA0_CH0_DriverIRQHandler(void);
EDMA0_CH0_DriverIRQHandler(void)80 void EDMA0_CH0_DriverIRQHandler(void)
81 {
82 /* Instance 0 channel 0 */
83 EDMA_DriverIRQHandler(0U, 0U);
84 }
85
86 /*!
87 * brief DMA instance 0, channel 1 IRQ handler.
88 *
89 */
90 extern void EDMA0_CH1_DriverIRQHandler(void);
EDMA0_CH1_DriverIRQHandler(void)91 void EDMA0_CH1_DriverIRQHandler(void)
92 {
93 /* Instance 0 channel 1 */
94 EDMA_DriverIRQHandler(0U, 1U);
95 }
96
97 /*!
98 * brief DMA instance 0, channel 2 IRQ handler.
99 *
100 */
101 extern void EDMA0_CH2_DriverIRQHandler(void);
EDMA0_CH2_DriverIRQHandler(void)102 void EDMA0_CH2_DriverIRQHandler(void)
103 {
104 /* Instance 0 channel 2 */
105 EDMA_DriverIRQHandler(0U, 2U);
106 }
107
108 /*!
109 * brief DMA instance 0, channel 3 IRQ handler.
110 *
111 */
112 extern void EDMA0_CH3_DriverIRQHandler(void);
EDMA0_CH3_DriverIRQHandler(void)113 void EDMA0_CH3_DriverIRQHandler(void)
114 {
115 /* Instance 0 channel 3 */
116 EDMA_DriverIRQHandler(0U, 3U);
117 }
118
119 /*!
120 * brief DMA instance 0, channel 4 IRQ handler.
121 *
122 */
123 extern void EDMA0_CH4_DriverIRQHandler(void);
EDMA0_CH4_DriverIRQHandler(void)124 void EDMA0_CH4_DriverIRQHandler(void)
125 {
126 /* Instance 0 channel 4 */
127 EDMA_DriverIRQHandler(0U, 4U);
128 }
129
130 /*!
131 * brief DMA instance 0, channel 5 IRQ handler.
132 *
133 */
134 extern void EDMA0_CH5_DriverIRQHandler(void);
EDMA0_CH5_DriverIRQHandler(void)135 void EDMA0_CH5_DriverIRQHandler(void)
136 {
137 /* Instance 0 channel 5 */
138 EDMA_DriverIRQHandler(0U, 5U);
139 }
140
141 /*!
142 * brief DMA instance 0, channel 6 IRQ handler.
143 *
144 */
145 extern void EDMA0_CH6_DriverIRQHandler(void);
EDMA0_CH6_DriverIRQHandler(void)146 void EDMA0_CH6_DriverIRQHandler(void)
147 {
148 /* Instance 0 channel 6 */
149 EDMA_DriverIRQHandler(0U, 6U);
150 }
151
152 /*!
153 * brief DMA instance 0, channel 7 IRQ handler.
154 *
155 */
156 extern void EDMA0_CH7_DriverIRQHandler(void);
EDMA0_CH7_DriverIRQHandler(void)157 void EDMA0_CH7_DriverIRQHandler(void)
158 {
159 /* Instance 0 channel 7 */
160 EDMA_DriverIRQHandler(0U, 7U);
161 }
162
163 /*!
164 * brief DMA instance 0, channel 8 IRQ handler.
165 *
166 */
167 extern void EDMA0_CH8_DriverIRQHandler(void);
EDMA0_CH8_DriverIRQHandler(void)168 void EDMA0_CH8_DriverIRQHandler(void)
169 {
170 /* Instance 0 channel 8 */
171 EDMA_DriverIRQHandler(0U, 8U);
172 }
173
174 /*!
175 * brief DMA instance 0, channel 9 IRQ handler.
176 *
177 */
178 extern void EDMA0_CH9_DriverIRQHandler(void);
EDMA0_CH9_DriverIRQHandler(void)179 void EDMA0_CH9_DriverIRQHandler(void)
180 {
181 /* Instance 0 channel 9 */
182 EDMA_DriverIRQHandler(0U, 9U);
183 }
184
185 /*!
186 * brief DMA instance 0, channel 10 IRQ handler.
187 *
188 */
189 extern void EDMA0_CH10_DriverIRQHandler(void);
EDMA0_CH10_DriverIRQHandler(void)190 void EDMA0_CH10_DriverIRQHandler(void)
191 {
192 /* Instance 0 channel 10 */
193 EDMA_DriverIRQHandler(0U, 10U);
194 }
195
196 /*!
197 * brief DMA instance 0, channel 11 IRQ handler.
198 *
199 */
200 extern void EDMA0_CH11_DriverIRQHandler(void);
EDMA0_CH11_DriverIRQHandler(void)201 void EDMA0_CH11_DriverIRQHandler(void)
202 {
203 /* Instance 0 channel 11 */
204 EDMA_DriverIRQHandler(0U, 11U);
205 }
206
207 /*!
208 * brief DMA instance 0, channel 12 IRQ handler.
209 *
210 */
211 extern void EDMA0_CH12_DriverIRQHandler(void);
EDMA0_CH12_DriverIRQHandler(void)212 void EDMA0_CH12_DriverIRQHandler(void)
213 {
214 /* Instance 0 channel 12 */
215 EDMA_DriverIRQHandler(0U, 12U);
216 }
217
218 /*!
219 * brief DMA instance 0, channel 13 IRQ handler.
220 *
221 */
222 extern void EDMA0_CH13_DriverIRQHandler(void);
EDMA0_CH13_DriverIRQHandler(void)223 void EDMA0_CH13_DriverIRQHandler(void)
224 {
225 /* Instance 0 channel 13 */
226 EDMA_DriverIRQHandler(0U, 13U);
227 }
228
229 /*!
230 * brief DMA instance 0, channel 14 IRQ handler.
231 *
232 */
233 extern void EDMA0_CH14_DriverIRQHandler(void);
EDMA0_CH14_DriverIRQHandler(void)234 void EDMA0_CH14_DriverIRQHandler(void)
235 {
236 /* Instance 0 channel 14 */
237 EDMA_DriverIRQHandler(0U, 14U);
238 }
239
240 /*!
241 * brief DMA instance 0, channel 15 IRQ handler.
242 *
243 */
244 extern void EDMA0_CH15_DriverIRQHandler(void);
EDMA0_CH15_DriverIRQHandler(void)245 void EDMA0_CH15_DriverIRQHandler(void)
246 {
247 /* Instance 0 channel 15 */
248 EDMA_DriverIRQHandler(0U, 15U);
249 }
250 #endif
251 #if defined(DMA1)
252 /*!
253 * brief DMA instance 1, channel 0 IRQ handler.
254 *
255 */
256 extern void EDMA1_CH0_DriverIRQHandler(void);
EDMA1_CH0_DriverIRQHandler(void)257 void EDMA1_CH0_DriverIRQHandler(void)
258 {
259 /* Instance 1 channel 0 */
260 EDMA_DriverIRQHandler(1U, 0U);
261 }
262
263 /*!
264 * brief DMA instance 1, channel 1 IRQ handler.
265 *
266 */
267 extern void EDMA1_CH1_DriverIRQHandler(void);
EDMA1_CH1_DriverIRQHandler(void)268 void EDMA1_CH1_DriverIRQHandler(void)
269 {
270 /* Instance 1 channel 1 */
271 EDMA_DriverIRQHandler(1U, 1U);
272 }
273
274 /*!
275 * brief DMA instance 1, channel 2 IRQ handler.
276 *
277 */
278 extern void EDMA1_CH2_DriverIRQHandler(void);
EDMA1_CH2_DriverIRQHandler(void)279 void EDMA1_CH2_DriverIRQHandler(void)
280 {
281 /* Instance 1 channel 2 */
282 EDMA_DriverIRQHandler(1U, 2U);
283 }
284
285 /*!
286 * brief DMA instance 1, channel 3 IRQ handler.
287 *
288 */
289 extern void EDMA1_CH3_DriverIRQHandler(void);
EDMA1_CH3_DriverIRQHandler(void)290 void EDMA1_CH3_DriverIRQHandler(void)
291 {
292 /* Instance 1 channel 3 */
293 EDMA_DriverIRQHandler(1U, 3U);
294 }
295
296 /*!
297 * brief DMA instance 1, channel 4 IRQ handler.
298 *
299 */
300 extern void EDMA1_CH4_DriverIRQHandler(void);
EDMA1_CH4_DriverIRQHandler(void)301 void EDMA1_CH4_DriverIRQHandler(void)
302 {
303 /* Instance 1 channel 4 */
304 EDMA_DriverIRQHandler(1U, 4U);
305 }
306
307 /*!
308 * brief DMA instance 1, channel 5 IRQ handler.
309 *
310 */
311 extern void EDMA1_CH5_DriverIRQHandler(void);
EDMA1_CH5_DriverIRQHandler(void)312 void EDMA1_CH5_DriverIRQHandler(void)
313 {
314 /* Instance 1 channel 5 */
315 EDMA_DriverIRQHandler(1U, 5U);
316 }
317
318 /*!
319 * brief DMA instance 1, channel 6 IRQ handler.
320 *
321 */
322 extern void EDMA1_CH6_DriverIRQHandler(void);
EDMA1_CH6_DriverIRQHandler(void)323 void EDMA1_CH6_DriverIRQHandler(void)
324 {
325 /* Instance 1 channel 6 */
326 EDMA_DriverIRQHandler(1U, 6U);
327 }
328
329 /*!
330 * brief DMA instance 1, channel 7 IRQ handler.
331 *
332 */
333 extern void EDMA1_CH7_DriverIRQHandler(void);
EDMA1_CH7_DriverIRQHandler(void)334 void EDMA1_CH7_DriverIRQHandler(void)
335 {
336 /* Instance 1 channel 7 */
337 EDMA_DriverIRQHandler(1U, 7U);
338 }
339
340 /*!
341 * brief DMA instance 1, channel 8 IRQ handler.
342 *
343 */
344 extern void EDMA1_CH8_DriverIRQHandler(void);
EDMA1_CH8_DriverIRQHandler(void)345 void EDMA1_CH8_DriverIRQHandler(void)
346 {
347 /* Instance 1 channel 8 */
348 EDMA_DriverIRQHandler(1U, 8U);
349 }
350
351 /*!
352 * brief DMA instance 1, channel 9 IRQ handler.
353 *
354 */
355 extern void EDMA1_CH9_DriverIRQHandler(void);
EDMA1_CH9_DriverIRQHandler(void)356 void EDMA1_CH9_DriverIRQHandler(void)
357 {
358 /* Instance 1 channel 9 */
359 EDMA_DriverIRQHandler(1U, 9U);
360 }
361
362 /*!
363 * brief DMA instance 1, channel 10 IRQ handler.
364 *
365 */
366 extern void EDMA1_CH10_DriverIRQHandler(void);
EDMA1_CH10_DriverIRQHandler(void)367 void EDMA1_CH10_DriverIRQHandler(void)
368 {
369 /* Instance 1 channel 10 */
370 EDMA_DriverIRQHandler(1U, 10U);
371 }
372
373 /*!
374 * brief DMA instance 1, channel 11 IRQ handler.
375 *
376 */
377 extern void EDMA1_CH11_DriverIRQHandler(void);
EDMA1_CH11_DriverIRQHandler(void)378 void EDMA1_CH11_DriverIRQHandler(void)
379 {
380 /* Instance 1 channel 11 */
381 EDMA_DriverIRQHandler(1U, 11U);
382 }
383
384 /*!
385 * brief DMA instance 1, channel 12 IRQ handler.
386 *
387 */
388 extern void EDMA1_CH12_DriverIRQHandler(void);
EDMA1_CH12_DriverIRQHandler(void)389 void EDMA1_CH12_DriverIRQHandler(void)
390 {
391 /* Instance 1 channel 12 */
392 EDMA_DriverIRQHandler(1U, 12U);
393 }
394
395 /*!
396 * brief DMA instance 1, channel 13 IRQ handler.
397 *
398 */
399 extern void EDMA1_CH13_DriverIRQHandler(void);
EDMA1_CH13_DriverIRQHandler(void)400 void EDMA1_CH13_DriverIRQHandler(void)
401 {
402 /* Instance 1 channel 13 */
403 EDMA_DriverIRQHandler(1U, 13U);
404 }
405
406 /*!
407 * brief DMA instance 1, channel 14 IRQ handler.
408 *
409 */
410 extern void EDMA1_CH14_DriverIRQHandler(void);
EDMA1_CH14_DriverIRQHandler(void)411 void EDMA1_CH14_DriverIRQHandler(void)
412 {
413 /* Instance 1 channel 14 */
414 EDMA_DriverIRQHandler(1U, 14U);
415 }
416
417 /*!
418 * brief DMA instance 1, channel 15 IRQ handler.
419 *
420 */
421 extern void EDMA1_CH15_DriverIRQHandler(void);
EDMA1_CH15_DriverIRQHandler(void)422 void EDMA1_CH15_DriverIRQHandler(void)
423 {
424 /* Instance 1 channel 15 */
425 EDMA_DriverIRQHandler(1U, 15U);
426 }
427 #endif
428 #if defined(DMA2)
429 /*!
430 * brief DMA instance 0, channel 0 IRQ handler.
431 *
432 */
433 extern void EDMA2_CH0_DriverIRQHandler(void);
EDMA2_CH0_DriverIRQHandler(void)434 void EDMA2_CH0_DriverIRQHandler(void)
435 {
436 /* Instance 0 channel 0 */
437 EDMA_DriverIRQHandler(0U, 0U);
438 }
439
440 /*!
441 * brief DMA instance 0, channel 1 IRQ handler.
442 *
443 */
444 extern void EDMA2_CH1_DriverIRQHandler(void);
EDMA2_CH1_DriverIRQHandler(void)445 void EDMA2_CH1_DriverIRQHandler(void)
446 {
447 /* Instance 0 channel 1 */
448 EDMA_DriverIRQHandler(0U, 1U);
449 }
450
451 /*!
452 * brief DMA instance 0, channel 2 IRQ handler.
453 *
454 */
455 extern void EDMA2_CH2_DriverIRQHandler(void);
EDMA2_CH2_DriverIRQHandler(void)456 void EDMA2_CH2_DriverIRQHandler(void)
457 {
458 /* Instance 0 channel 2 */
459 EDMA_DriverIRQHandler(0U, 2U);
460 }
461
462 /*!
463 * brief DMA instance 0, channel 3 IRQ handler.
464 *
465 */
466 extern void EDMA2_CH3_DriverIRQHandler(void);
EDMA2_CH3_DriverIRQHandler(void)467 void EDMA2_CH3_DriverIRQHandler(void)
468 {
469 /* Instance 0 channel 3 */
470 EDMA_DriverIRQHandler(0U, 3U);
471 }
472
473 /*!
474 * brief DMA instance 0, channel 4 IRQ handler.
475 *
476 */
477 extern void EDMA2_CH4_DriverIRQHandler(void);
EDMA2_CH4_DriverIRQHandler(void)478 void EDMA2_CH4_DriverIRQHandler(void)
479 {
480 /* Instance 0 channel 4 */
481 EDMA_DriverIRQHandler(0U, 4U);
482 }
483
484 /*!
485 * brief DMA instance 0, channel 5 IRQ handler.
486 *
487 */
488 extern void EDMA2_CH5_DriverIRQHandler(void);
EDMA2_CH5_DriverIRQHandler(void)489 void EDMA2_CH5_DriverIRQHandler(void)
490 {
491 /* Instance 0 channel 5 */
492 EDMA_DriverIRQHandler(0U, 5U);
493 }
494
495 /*!
496 * brief DMA instance 0, channel 6 IRQ handler.
497 *
498 */
499 extern void EDMA2_CH6_DriverIRQHandler(void);
EDMA2_CH6_DriverIRQHandler(void)500 void EDMA2_CH6_DriverIRQHandler(void)
501 {
502 /* Instance 0 channel 6 */
503 EDMA_DriverIRQHandler(0U, 6U);
504 }
505
506 /*!
507 * brief DMA instance 0, channel 7 IRQ handler.
508 *
509 */
510 extern void EDMA2_CH7_DriverIRQHandler(void);
EDMA2_CH7_DriverIRQHandler(void)511 void EDMA2_CH7_DriverIRQHandler(void)
512 {
513 /* Instance 0 channel 7 */
514 EDMA_DriverIRQHandler(0U, 7U);
515 }
516 #endif
517 #if defined(DMA3)
518 /*!
519 * brief DMA instance 1, channel 0 IRQ handler.
520 *
521 */
522 extern void EDMA3_CH0_DriverIRQHandler(void);
EDMA3_CH0_DriverIRQHandler(void)523 void EDMA3_CH0_DriverIRQHandler(void)
524 {
525 /* Instance 1 channel 0 */
526 EDMA_DriverIRQHandler(1U, 0U);
527 }
528
529 /*!
530 * brief DMA instance 1, channel 1 IRQ handler.
531 *
532 */
533 extern void EDMA3_CH1_DriverIRQHandler(void);
EDMA3_CH1_DriverIRQHandler(void)534 void EDMA3_CH1_DriverIRQHandler(void)
535 {
536 /* Instance 1 channel 1 */
537 EDMA_DriverIRQHandler(1U, 1U);
538 }
539
540 /*!
541 * brief DMA instance 1, channel 2 IRQ handler.
542 *
543 */
544 extern void EDMA3_CH2_DriverIRQHandler(void);
EDMA3_CH2_DriverIRQHandler(void)545 void EDMA3_CH2_DriverIRQHandler(void)
546 {
547 /* Instance 1 channel 2 */
548 EDMA_DriverIRQHandler(1U, 2U);
549 }
550
551 /*!
552 * brief DMA instance 1, channel 3 IRQ handler.
553 *
554 */
555 extern void EDMA3_CH3_DriverIRQHandler(void);
EDMA3_CH3_DriverIRQHandler(void)556 void EDMA3_CH3_DriverIRQHandler(void)
557 {
558 /* Instance 1 channel 3 */
559 EDMA_DriverIRQHandler(1U, 3U);
560 }
561
562 /*!
563 * brief DMA instance 1, channel 4 IRQ handler.
564 *
565 */
566 extern void EDMA3_CH4_DriverIRQHandler(void);
EDMA3_CH4_DriverIRQHandler(void)567 void EDMA3_CH4_DriverIRQHandler(void)
568 {
569 /* Instance 1 channel 4 */
570 EDMA_DriverIRQHandler(1U, 4U);
571 }
572
573 /*!
574 * brief DMA instance 1, channel 5 IRQ handler.
575 *
576 */
577 extern void EDMA3_CH5_DriverIRQHandler(void);
EDMA3_CH5_DriverIRQHandler(void)578 void EDMA3_CH5_DriverIRQHandler(void)
579 {
580 /* Instance 1 channel 5 */
581 EDMA_DriverIRQHandler(1U, 5U);
582 }
583
584 /*!
585 * brief DMA instance 1, channel 6 IRQ handler.
586 *
587 */
588 extern void EDMA3_CH6_DriverIRQHandler(void);
EDMA3_CH6_DriverIRQHandler(void)589 void EDMA3_CH6_DriverIRQHandler(void)
590 {
591 /* Instance 1 channel 6 */
592 EDMA_DriverIRQHandler(1U, 6U);
593 }
594
595 /*!
596 * brief DMA instance 1, channel 7 IRQ handler.
597 *
598 */
599 extern void EDMA3_CH7_DriverIRQHandler(void);
EDMA3_CH7_DriverIRQHandler(void)600 void EDMA3_CH7_DriverIRQHandler(void)
601 {
602 /* Instance 1 channel 7 */
603 EDMA_DriverIRQHandler(1U, 7U);
604 }
605 #endif
606
