1 /*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef _FSL_MISC_H_
8 #define _FSL_MISC_H_
9
10 #include "fsl_common.h"
11
12 /*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.misc"
18 #endif
19
20 #define BLK_CTRL_SAIMCLK_LOWBITMASK (0x7U)
21 #define BLK_CTRL_SAIMCLK_HIGHBITMASK (0x3U)
22
23 typedef enum _blk_ctrl_saimclk
24 {
25 kBLK_CTRL_SAI4MClk1Sel = BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK1_SEL_SHIFT,
26 kBLK_CTRL_SAI4MClk2Sel = BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK2_SEL_SHIFT,
27 kBLK_CTRL_SAI4MClk3Sel = BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK3_SEL_SHIFT,
28 kBLK_CTRL_SAI2MClk3Sel = BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK3_SEL_SHIFT + 8,
29 kBLK_CTRL_SAI3MClk3Sel = BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK3_SEL_SHIFT + 10,
30 } blk_ctrl_saimclk_t;
31
32 /*******************************************************************************
33 * API
34 ******************************************************************************/
35 #if defined(__cplusplus)
36 extern "C" {
37 #endif
38
39 /*!
40 * @brief Sets BLK general configuration for SAI MCLK selection.
41 *
42 * @param base The BLK CTRL base address.
43 * @param mclk The SAI MCLK.
44 * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM.
45 */
BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX_Type * base,blk_ctrl_saimclk_t mclk,uint8_t clkSrc)46 static inline void BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX_Type *base,
47 blk_ctrl_saimclk_t mclk,
48 uint8_t clkSrc)
49 {
50 uint32_t temp;
51
52 if (mclk > kBLK_CTRL_SAI2MClk3Sel)
53 {
54 temp = base->SAI3_MCLK_CTRL & ~(BLK_CTRL_SAIMCLK_HIGHBITMASK);
55 base->SAI3_MCLK_CTRL = ((uint32_t)clkSrc & BLK_CTRL_SAIMCLK_HIGHBITMASK) | temp;
56 }
57 else if (mclk > kBLK_CTRL_SAI4MClk3Sel)
58 {
59 temp = base->SAI2_MCLK_CTRL & ~(BLK_CTRL_SAIMCLK_HIGHBITMASK);
60 base->SAI2_MCLK_CTRL = ((uint32_t)clkSrc & BLK_CTRL_SAIMCLK_HIGHBITMASK) | temp;
61 }
62 else if (mclk > kBLK_CTRL_SAI4MClk2Sel)
63 {
64 temp = base->SAI4_MCLK_CTRL & ~((uint32_t)BLK_CTRL_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
65 base->SAI4_MCLK_CTRL = (((uint32_t)clkSrc & BLK_CTRL_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | temp;
66 }
67 else
68 {
69 temp = base->SAI4_MCLK_CTRL & ~((uint32_t)BLK_CTRL_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
70 base->SAI4_MCLK_CTRL = (((uint32_t)clkSrc & BLK_CTRL_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | temp;
71 }
72 }
73
74 #if defined(__cplusplus)
75 }
76 #endif /* __cplusplus */
77 #endif /* _FSL_MISC_H_ */
78
