1 /* 2 * Copyright 2022-2023 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef _FSL_EDMA_SOC_H_ 8 #define _FSL_EDMA_SOC_H_ 9 10 #include "fsl_common.h" 11 12 /*! 13 * @addtogroup edma_soc 14 * @{ 15 */ 16 17 /******************************************************************************* 18 * Definitions 19 ******************************************************************************/ 20 /*! @name Driver version */ 21 /*@{*/ 22 /*! @brief Driver version 2.1.0. */ 23 #define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) 24 /*@}*/ 25 26 /*!@brief DMA IP version */ 27 #define FSL_EDMA_SOC_IP_DMA3 (1) 28 #define FSL_EDMA_SOC_IP_DMA4 (1) 29 30 /*!@brief DMA base table */ 31 #define EDMA_BASE_PTRS \ 32 { \ 33 DMA3, DMA4 \ 34 } 35 36 #define EDMA_CHN_IRQS \ 37 { \ 38 {DMA3_CH0_IRQn, \ 39 DMA3_CH1_IRQn, \ 40 DMA3_CH2_IRQn, \ 41 DMA3_CH3_IRQn, \ 42 DMA3_CH4_IRQn, \ 43 DMA3_CH5_IRQn, \ 44 DMA3_CH6_IRQn, \ 45 DMA3_CH7_IRQn, \ 46 DMA3_CH8_IRQn, \ 47 DMA3_CH9_IRQn, \ 48 DMA3_CH10_IRQn, \ 49 DMA3_CH11_IRQn, \ 50 DMA3_CH12_IRQn, \ 51 DMA3_CH13_IRQn, \ 52 DMA3_CH14_IRQn, \ 53 DMA3_CH15_IRQn, \ 54 DMA3_CH16_IRQn, \ 55 DMA3_CH17_IRQn, \ 56 DMA3_CH18_IRQn, \ 57 DMA3_CH19_IRQn, \ 58 DMA3_CH20_IRQn, \ 59 DMA3_CH21_IRQn, \ 60 DMA3_CH22_IRQn, \ 61 DMA3_CH23_IRQn, \ 62 DMA3_CH24_IRQn, \ 63 DMA3_CH25_IRQn, \ 64 DMA3_CH26_IRQn, \ 65 DMA3_CH27_IRQn, \ 66 DMA3_CH28_IRQn, \ 67 DMA3_CH29_IRQn, \ 68 DMA3_CH30_IRQn, \ 69 DMA3_CH31_IRQn}, \ 70 { \ 71 DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, \ 72 DMA4_CH4_CH5_CH36_CH37_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, \ 73 DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, \ 74 DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, \ 75 DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, \ 76 DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, \ 77 DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, \ 78 DMA4_CH30_CH31_CH62_CH63_IRQn, DMA4_CH30_CH31_CH62_CH63_IRQn, DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH0_CH1_CH32_CH33_IRQn, \ 79 DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, \ 80 DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, \ 81 DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, \ 82 DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, \ 83 DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, \ 84 DMA4_CH20_CH21_CH52_CH53_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, \ 85 DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH26_CH27_CH58_CH59_IRQn, \ 86 DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, \ 87 DMA4_CH30_CH31_CH62_CH63_IRQn, DMA4_CH30_CH31_CH62_CH63_IRQn \ 88 } \ 89 } 90 91 /*!< Verify dma base and request source */ 92 #define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((base) == DMA3 ? ((source)&0x100U) : ((source)&0x200U)) 93 /*!@brief EDMA base address convert macro */ 94 #define EDMA_CHANNEL_OFFSET 0x10000U 95 #define EDMA_CHANNEL_ARRAY_STEP(base) ((base) == DMA3 ? 0x10000U : 0x8000U) 96 97 /******************************************************************************* 98 * API 99 ******************************************************************************/ 100 101 #ifdef __cplusplus 102 extern "C" { 103 #endif 104 105 #ifdef __cplusplus 106 } 107 #endif 108 109 /*! 110 * @} 111 */ 112 113 #endif /* _FSL_EDMA_SOC_H_ */ 114
