1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1021CAF4A
4 **                          MIMXRT1021CAF4B
5 **                          MIMXRT1021CAG4A
6 **                          MIMXRT1021CAG4B
7 **                          MIMXRT1021DAF5A
8 **                          MIMXRT1021DAF5B
9 **                          MIMXRT1021DAG5A
10 **                          MIMXRT1021DAG5B
11 **
12 **     Compilers:           Freescale C/C++ for Embedded ARM
13 **                          GNU C Compiler
14 **                          IAR ANSI C/C++ Compiler for ARM
15 **                          Keil ARM C/C++ Compiler
16 **                          MCUXpresso Compiler
17 **
18 **     Reference manual:    IMXRT1020RM Rev.2, 01/2021 | IMXRT102XSRM Rev.0
19 **     Version:             rev. 1.2, 2021-08-10
20 **     Build:               b230821
21 **
22 **     Abstract:
23 **         Provides a system configuration function and a global variable that
24 **         contains the system frequency. It configures the device and initializes
25 **         the oscillator (PLL) that is part of the microcontroller device.
26 **
27 **     Copyright 2016 Freescale Semiconductor, Inc.
28 **     Copyright 2016-2023 NXP
29 **     SPDX-License-Identifier: BSD-3-Clause
30 **
31 **     http:                 www.nxp.com
32 **     mail:                 support@nxp.com
33 **
34 **     Revisions:
35 **     - rev. 0.1 (2017-11-06)
36 **         Initial version.
37 **     - rev. 1.0 (2018-11-27)
38 **         Update header files to align with IMXRT1020RM Rev.1.
39 **     - rev. 1.1 (2019-04-29)
40 **         Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
41 **     - rev. 1.2 (2021-08-10)
42 **         Update header files to align with IMXRT1020RM Rev.2.
43 **
44 ** ###################################################################
45 */
46 
47 /*!
48  * @file MIMXRT1021
49  * @version 1.2
50  * @date 2021-08-10
51  * @brief Device specific configuration file for MIMXRT1021 (implementation file)
52  *
53  * Provides a system configuration function and a global variable that contains
54  * the system frequency. It configures the device and initializes the oscillator
55  * (PLL) that is part of the microcontroller device.
56  */
57 
58 #include <stdint.h>
59 #include "fsl_device_registers.h"
60 
61 
62 
63 /* ----------------------------------------------------------------------------
64    -- Core clock
65    ---------------------------------------------------------------------------- */
66 
67 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
68 
69 /* ----------------------------------------------------------------------------
70    -- SystemInit()
71    ---------------------------------------------------------------------------- */
72 
SystemInit(void)73 void SystemInit (void) {
74 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
75   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
76 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
77 
78 #if defined(__MCUXPRESSO)
79     extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
80     SCB->VTOR = (uint32_t)g_pfnVectors;
81 #endif
82 
83 /* Disable Watchdog Power Down Counter */
84     WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
85     WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
86 
87 /* Watchdog disable */
88 
89 #if (DISABLE_WDOG)
90     if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
91     {
92         WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
93     }
94     if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
95     {
96         WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
97     }
98     if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
99     {
100         RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
101     }
102     else
103     {
104         RTWDOG->CNT = 0xC520U;
105         RTWDOG->CNT = 0xD928U;
106     }
107     RTWDOG->TOVAL = 0xFFFF;
108     RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
109 #endif /* (DISABLE_WDOG) */
110 
111     /* Disable Systick which might be enabled by bootrom */
112     if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
113     {
114         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
115     }
116 
117 /* Enable instruction and data caches */
118 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
119     if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
120         SCB_EnableICache();
121     }
122 #endif
123 
124   SystemInitHook();
125 }
126 
127 /* ----------------------------------------------------------------------------
128    -- SystemCoreClockUpdate()
129    ---------------------------------------------------------------------------- */
130 
SystemCoreClockUpdate(void)131 void SystemCoreClockUpdate (void) {
132 
133     uint32_t freq;
134     uint32_t PLL2MainClock;
135     uint32_t PLL3MainClock;
136 
137     /* Check if system pll is bypassed */
138     if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
139     {
140         PLL2MainClock = CPU_XTAL_CLK_HZ;
141     }
142     else
143     {
144         PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
145     }
146     PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
147 
148     /* Check if usb1 pll is bypassed */
149     if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
150     {
151         PLL3MainClock = CPU_XTAL_CLK_HZ;
152     }
153     else
154     {
155         PLL3MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
156     }
157 
158     /* Periph_clk2_clk ---> Periph_clk */
159     if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
160     {
161         switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
162         {
163             /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
164             case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
165                 freq = PLL3MainClock;
166                 break;
167 
168             /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
169             case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
170                 freq = CPU_XTAL_CLK_HZ;
171                 break;
172 
173             /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
174             case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
175                 freq = CPU_XTAL_CLK_HZ;
176                 break;
177 
178             case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
179             default:
180                 freq = 0U;
181                 break;
182         }
183 
184         freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
185     }
186     /* Pre_Periph_clk ---> Periph_clk */
187     else
188     {
189         switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
190         {
191             /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
192             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
193                 freq = PLL2MainClock;
194                 break;
195 
196             /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
197             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
198                 freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U;
199                 break;
200 
201             /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
202             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
203                 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U;
204                 break;
205 
206             /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
207             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
208                 freq = 500000000U / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
209                 break;
210 
211             default:
212                 freq = 0U;
213                 break;
214         }
215     }
216 
217     SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
218 
219 }
220 
221 /* ----------------------------------------------------------------------------
222    -- SystemInitHook()
223    ---------------------------------------------------------------------------- */
224 
SystemInitHook(void)225 __attribute__ ((weak)) void SystemInitHook (void) {
226   /* Void implementation of the weak function. */
227 }
228