1 /*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef _FSL_IOMUXC_H_
7 #define _FSL_IOMUXC_H_
8
9 #include "fsl_common.h"
10
11 /*!
12 * @addtogroup iomuxc_driver
13 * @{
14 */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21 /* Component ID definition, used by tools. */
22 #ifndef FSL_COMPONENT_ID
23 #define FSL_COMPONENT_ID "platform.drivers.iomuxc"
24 #endif
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief IOMUXC driver version 1.0.0. */
29 #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
30 /*@}*/
31
32 /*!
33 * @name Pin function ID
34 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
35 *
36 * @{
37 */
38 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
39 #define IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI 0x543c0000, 0x0, 0x543c03d8, 0x0, 0x543c01b0
40 #define IOMUXC_PAD_DAP_TDI__MQS2_LEFT 0x543c0000, 0x1, 0x0, 0x0, 0x543c01b0
41 #define IOMUXC_PAD_DAP_TDI__CAN2_TX 0x543c0000, 0x3, 0x0, 0x0, 0x543c01b0
42 #define IOMUXC_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x543c0000, 0x4, 0x0, 0x0, 0x543c01b0
43 #define IOMUXC_PAD_DAP_TDI__GPIO3_IO28 0x543c0000, 0x5, 0x0, 0x0, 0x543c01b0
44 #define IOMUXC_PAD_DAP_TDI__LPUART5_RX 0x543c0000, 0x6, 0x543c0430, 0x0, 0x543c01b0
45 #define IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x543c0004, 0x0, 0x543c03dc, 0x0, 0x543c01b4
46 #define IOMUXC_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x543c0004, 0x4, 0x0, 0x0, 0x543c01b4
47 #define IOMUXC_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x543c0004, 0x5, 0x0, 0x0, 0x543c01b4
48 #define IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x543c0004, 0x6, 0x0, 0x0, 0x543c01b4
49 #define IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x543c0008, 0x0, 0x543c03d4, 0x0, 0x543c01b8
50 #define IOMUXC_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x543c0008, 0x4, 0x0, 0x0, 0x543c01b8
51 #define IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x543c0008, 0x5, 0x0, 0x0, 0x543c01b8
52 #define IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x543c0008, 0x6, 0x543c042c, 0x0, 0x543c01b8
53 #define IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x543c000c, 0x0, 0x0, 0x0, 0x543c01bc
54 #define IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x543c000c, 0x1, 0x0, 0x0, 0x543c01bc
55 #define IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x543c000c, 0x3, 0x543c0364, 0x0, 0x543c01bc
56 #define IOMUXC_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x543c000c, 0x4, 0x0, 0x0, 0x543c01bc
57 #define IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x543c000c, 0x5, 0x0, 0x0, 0x543c01bc
58 #define IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x543c000c, 0x6, 0x543c0434, 0x0, 0x543c01bc
59 #define IOMUXC_PAD_GPIO_IO00__GPIO2_IO00 0x543c0010, 0x0, 0x0, 0x0, 0x543c01c0
60 #define IOMUXC_PAD_GPIO_IO00__LPI2C3_SDA 0x543c0010, 0x1, 0x543c03e4, 0x0, 0x543c01c0
61 #define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x543c0010, 0x2, 0x0, 0x0, 0x543c01c0
62 #define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x543c0010, 0x3, 0x0, 0x0, 0x543c01c0
63 #define IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0 0x543c0010, 0x4, 0x0, 0x0, 0x543c01c0
64 #define IOMUXC_PAD_GPIO_IO00__LPUART5_TX 0x543c0010, 0x5, 0x543c0434, 0x1, 0x543c01c0
65 #define IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA 0x543c0010, 0x6, 0x543c03ec, 0x0, 0x543c01c0
66 #define IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x543c0010, 0x7, 0x543c036c, 0x0, 0x543c01c0
67 #define IOMUXC_PAD_GPIO_IO01__GPIO2_IO01 0x543c0014, 0x0, 0x0, 0x0, 0x543c01c4
68 #define IOMUXC_PAD_GPIO_IO01__LPI2C3_SCL 0x543c0014, 0x1, 0x543c03e0, 0x0, 0x543c01c4
69 #define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x543c0014, 0x2, 0x0, 0x0, 0x543c01c4
70 #define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x543c0014, 0x3, 0x0, 0x0, 0x543c01c4
71 #define IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN 0x543c0014, 0x4, 0x0, 0x0, 0x543c01c4
72 #define IOMUXC_PAD_GPIO_IO01__LPUART5_RX 0x543c0014, 0x5, 0x543c0430, 0x1, 0x543c01c4
73 #define IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL 0x543c0014, 0x6, 0x543c03e8, 0x0, 0x543c01c4
74 #define IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x543c0014, 0x7, 0x543c0370, 0x0, 0x543c01c4
75 #define IOMUXC_PAD_GPIO_IO02__GPIO2_IO02 0x543c0018, 0x0, 0x0, 0x0, 0x543c01c8
76 #define IOMUXC_PAD_GPIO_IO02__LPI2C4_SDA 0x543c0018, 0x1, 0x0, 0x0, 0x543c01c8
77 #define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x543c0018, 0x2, 0x0, 0x0, 0x543c01c8
78 #define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x543c0018, 0x3, 0x0, 0x0, 0x543c01c8
79 #define IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT 0x543c0018, 0x4, 0x0, 0x0, 0x543c01c8
80 #define IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B 0x543c0018, 0x5, 0x543c042c, 0x1, 0x543c01c8
81 #define IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA 0x543c0018, 0x6, 0x543c03f4, 0x0, 0x543c01c8
82 #define IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x543c0018, 0x7, 0x543c0374, 0x0, 0x543c01c8
83 #define IOMUXC_PAD_GPIO_IO03__GPIO2_IO03 0x543c001c, 0x0, 0x0, 0x0, 0x543c01cc
84 #define IOMUXC_PAD_GPIO_IO03__LPI2C4_SCL 0x543c001c, 0x1, 0x0, 0x0, 0x543c01cc
85 #define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x543c001c, 0x2, 0x0, 0x0, 0x543c01cc
86 #define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x543c001c, 0x3, 0x0, 0x0, 0x543c01cc
87 #define IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK 0x543c001c, 0x4, 0x0, 0x0, 0x543c01cc
88 #define IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B 0x543c001c, 0x5, 0x0, 0x0, 0x543c01cc
89 #define IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL 0x543c001c, 0x6, 0x543c03f0, 0x0, 0x543c01cc
90 #define IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x543c001c, 0x7, 0x543c0378, 0x0, 0x543c01cc
91 #define IOMUXC_PAD_GPIO_IO04__GPIO2_IO04 0x543c0020, 0x0, 0x0, 0x0, 0x543c01d0
92 #define IOMUXC_PAD_GPIO_IO04__TPM3_CH0 0x543c0020, 0x1, 0x0, 0x0, 0x543c01d0
93 #define IOMUXC_PAD_GPIO_IO04__PDM_CLK 0x543c0020, 0x2, 0x0, 0x0, 0x543c01d0
94 #define IOMUXC_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x543c0020, 0x3, 0x0, 0x0, 0x543c01d0
95 #define IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0 0x543c0020, 0x4, 0x0, 0x0, 0x543c01d0
96 #define IOMUXC_PAD_GPIO_IO04__LPUART6_TX 0x543c0020, 0x5, 0x0, 0x0, 0x543c01d0
97 #define IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA 0x543c0020, 0x6, 0x543c03f4, 0x1, 0x543c01d0
98 #define IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x543c0020, 0x7, 0x543c037c, 0x0, 0x543c01d0
99 #define IOMUXC_PAD_GPIO_IO05__GPIO2_IO05 0x543c0024, 0x0, 0x0, 0x0, 0x543c01d4
100 #define IOMUXC_PAD_GPIO_IO05__TPM4_CH0 0x543c0024, 0x1, 0x0, 0x0, 0x543c01d4
101 #define IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x543c0024, 0x2, 0x543c0438, 0x0, 0x543c01d4
102 #define IOMUXC_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x543c0024, 0x3, 0x0, 0x0, 0x543c01d4
103 #define IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN 0x543c0024, 0x4, 0x0, 0x0, 0x543c01d4
104 #define IOMUXC_PAD_GPIO_IO05__LPUART6_RX 0x543c0024, 0x5, 0x0, 0x0, 0x543c01d4
105 #define IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL 0x543c0024, 0x6, 0x543c03f0, 0x1, 0x543c01d4
106 #define IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x543c0024, 0x7, 0x543c0380, 0x0, 0x543c01d4
107 #define IOMUXC_PAD_GPIO_IO06__GPIO2_IO06 0x543c0028, 0x0, 0x0, 0x0, 0x543c01d8
108 #define IOMUXC_PAD_GPIO_IO06__TPM5_CH0 0x543c0028, 0x1, 0x0, 0x0, 0x543c01d8
109 #define IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x543c0028, 0x2, 0x543c043c, 0x0, 0x543c01d8
110 #define IOMUXC_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x543c0028, 0x3, 0x0, 0x0, 0x543c01d8
111 #define IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT 0x543c0028, 0x4, 0x0, 0x0, 0x543c01d8
112 #define IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B 0x543c0028, 0x5, 0x0, 0x0, 0x543c01d8
113 #define IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA 0x543c0028, 0x6, 0x543c03fc, 0x0, 0x543c01d8
114 #define IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x543c0028, 0x7, 0x543c0384, 0x0, 0x543c01d8
115 #define IOMUXC_PAD_GPIO_IO07__GPIO2_IO07 0x543c002c, 0x0, 0x0, 0x0, 0x543c01dc
116 #define IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1 0x543c002c, 0x1, 0x0, 0x0, 0x543c01dc
117 #define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x543c002c, 0x2, 0x0, 0x0, 0x543c01dc
118 #define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x543c002c, 0x3, 0x0, 0x0, 0x543c01dc
119 #define IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK 0x543c002c, 0x4, 0x0, 0x0, 0x543c01dc
120 #define IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B 0x543c002c, 0x5, 0x0, 0x0, 0x543c01dc
121 #define IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL 0x543c002c, 0x6, 0x543c03f8, 0x0, 0x543c01dc
122 #define IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x543c002c, 0x7, 0x543c0388, 0x0, 0x543c01dc
123 #define IOMUXC_PAD_GPIO_IO08__GPIO2_IO08 0x543c0030, 0x0, 0x0, 0x0, 0x543c01e0
124 #define IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0 0x543c0030, 0x1, 0x0, 0x0, 0x543c01e0
125 #define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x543c0030, 0x2, 0x0, 0x0, 0x543c01e0
126 #define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x543c0030, 0x3, 0x0, 0x0, 0x543c01e0
127 #define IOMUXC_PAD_GPIO_IO08__TPM6_CH0 0x543c0030, 0x4, 0x0, 0x0, 0x543c01e0
128 #define IOMUXC_PAD_GPIO_IO08__LPUART7_TX 0x543c0030, 0x5, 0x0, 0x0, 0x543c01e0
129 #define IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA 0x543c0030, 0x6, 0x543c03fc, 0x1, 0x543c01e0
130 #define IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x543c0030, 0x7, 0x543c038c, 0x0, 0x543c01e0
131 #define IOMUXC_PAD_GPIO_IO09__GPIO2_IO09 0x543c0034, 0x0, 0x0, 0x0, 0x543c01e4
132 #define IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN 0x543c0034, 0x1, 0x0, 0x0, 0x543c01e4
133 #define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x543c0034, 0x2, 0x0, 0x0, 0x543c01e4
134 #define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x543c0034, 0x3, 0x0, 0x0, 0x543c01e4
135 #define IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK 0x543c0034, 0x4, 0x0, 0x0, 0x543c01e4
136 #define IOMUXC_PAD_GPIO_IO09__LPUART7_RX 0x543c0034, 0x5, 0x0, 0x0, 0x543c01e4
137 #define IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL 0x543c0034, 0x6, 0x543c03f8, 0x1, 0x543c01e4
138 #define IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x543c0034, 0x7, 0x543c0390, 0x0, 0x543c01e4
139 #define IOMUXC_PAD_GPIO_IO10__GPIO2_IO10 0x543c0038, 0x0, 0x0, 0x0, 0x543c01e8
140 #define IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT 0x543c0038, 0x1, 0x0, 0x0, 0x543c01e8
141 #define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x543c0038, 0x2, 0x0, 0x0, 0x543c01e8
142 #define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x543c0038, 0x3, 0x0, 0x0, 0x543c01e8
143 #define IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK 0x543c0038, 0x4, 0x0, 0x0, 0x543c01e8
144 #define IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B 0x543c0038, 0x5, 0x0, 0x0, 0x543c01e8
145 #define IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA 0x543c0038, 0x6, 0x543c0404, 0x0, 0x543c01e8
146 #define IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x543c0038, 0x7, 0x543c0394, 0x0, 0x543c01e8
147 #define IOMUXC_PAD_GPIO_IO11__GPIO2_IO11 0x543c003c, 0x0, 0x0, 0x0, 0x543c01ec
148 #define IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK 0x543c003c, 0x1, 0x0, 0x0, 0x543c01ec
149 #define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x543c003c, 0x2, 0x0, 0x0, 0x543c01ec
150 #define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x543c003c, 0x3, 0x0, 0x0, 0x543c01ec
151 #define IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK 0x543c003c, 0x4, 0x0, 0x0, 0x543c01ec
152 #define IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B 0x543c003c, 0x5, 0x0, 0x0, 0x543c01ec
153 #define IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL 0x543c003c, 0x6, 0x543c0400, 0x0, 0x543c01ec
154 #define IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x543c003c, 0x7, 0x543c0398, 0x0, 0x543c01ec
155 #define IOMUXC_PAD_GPIO_IO12__GPIO2_IO12 0x543c0040, 0x0, 0x0, 0x0, 0x543c01f0
156 #define IOMUXC_PAD_GPIO_IO12__TPM3_CH2 0x543c0040, 0x1, 0x0, 0x0, 0x543c01f0
157 #define IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x543c0040, 0x2, 0x543c0440, 0x0, 0x543c01f0
158 #define IOMUXC_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x543c0040, 0x3, 0x0, 0x0, 0x543c01f0
159 #define IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0 0x543c0040, 0x4, 0x0, 0x0, 0x543c01f0
160 #define IOMUXC_PAD_GPIO_IO12__LPUART8_TX 0x543c0040, 0x5, 0x0, 0x0, 0x543c01f0
161 #define IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA 0x543c0040, 0x6, 0x543c0404, 0x1, 0x543c01f0
162 #define IOMUXC_PAD_GPIO_IO12__SAI3_RX_SYNC 0x543c0040, 0x7, 0x543c0450, 0x0, 0x543c01f0
163 #define IOMUXC_PAD_GPIO_IO13__GPIO2_IO13 0x543c0044, 0x0, 0x0, 0x0, 0x543c01f4
164 #define IOMUXC_PAD_GPIO_IO13__TPM4_CH2 0x543c0044, 0x1, 0x0, 0x0, 0x543c01f4
165 #define IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x543c0044, 0x2, 0x543c0444, 0x0, 0x543c01f4
166 #define IOMUXC_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x543c0044, 0x3, 0x0, 0x0, 0x543c01f4
167 #define IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN 0x543c0044, 0x4, 0x0, 0x0, 0x543c01f4
168 #define IOMUXC_PAD_GPIO_IO13__LPUART8_RX 0x543c0044, 0x5, 0x0, 0x0, 0x543c01f4
169 #define IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL 0x543c0044, 0x6, 0x543c0400, 0x1, 0x543c01f4
170 #define IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x543c0044, 0x7, 0x543c039c, 0x0, 0x543c01f4
171 #define IOMUXC_PAD_GPIO_IO14__GPIO2_IO14 0x543c0048, 0x0, 0x0, 0x0, 0x543c01f8
172 #define IOMUXC_PAD_GPIO_IO14__LPUART3_TX 0x543c0048, 0x1, 0x543c041c, 0x0, 0x543c01f8
173 #define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x543c0048, 0x2, 0x0, 0x0, 0x543c01f8
174 #define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x543c0048, 0x3, 0x0, 0x0, 0x543c01f8
175 #define IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT 0x543c0048, 0x4, 0x0, 0x0, 0x543c01f8
176 #define IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B 0x543c0048, 0x5, 0x0, 0x0, 0x543c01f8
177 #define IOMUXC_PAD_GPIO_IO14__LPUART4_TX 0x543c0048, 0x6, 0x543c0428, 0x0, 0x543c01f8
178 #define IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x543c0048, 0x7, 0x543c03a0, 0x0, 0x543c01f8
179 #define IOMUXC_PAD_GPIO_IO15__GPIO2_IO15 0x543c004c, 0x0, 0x0, 0x0, 0x543c01fc
180 #define IOMUXC_PAD_GPIO_IO15__LPUART3_RX 0x543c004c, 0x1, 0x543c0418, 0x0, 0x543c01fc
181 #define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x543c004c, 0x2, 0x0, 0x0, 0x543c01fc
182 #define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x543c004c, 0x3, 0x0, 0x0, 0x543c01fc
183 #define IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK 0x543c004c, 0x4, 0x0, 0x0, 0x543c01fc
184 #define IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B 0x543c004c, 0x5, 0x0, 0x0, 0x543c01fc
185 #define IOMUXC_PAD_GPIO_IO15__LPUART4_RX 0x543c004c, 0x6, 0x543c0424, 0x0, 0x543c01fc
186 #define IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x543c004c, 0x7, 0x543c03a4, 0x0, 0x543c01fc
187 #define IOMUXC_PAD_GPIO_IO16__GPIO2_IO16 0x543c0050, 0x0, 0x0, 0x0, 0x543c0200
188 #define IOMUXC_PAD_GPIO_IO16__SAI3_TX_BCLK 0x543c0050, 0x1, 0x0, 0x0, 0x543c0200
189 #define IOMUXC_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x543c0050, 0x2, 0x543c0440, 0x1, 0x543c0200
190 #define IOMUXC_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x543c0050, 0x3, 0x0, 0x0, 0x543c0200
191 #define IOMUXC_PAD_GPIO_IO16__LPUART3_CTS_B 0x543c0050, 0x4, 0x543c0414, 0x0, 0x543c0200
192 #define IOMUXC_PAD_GPIO_IO16__LPSPI4_PCS2 0x543c0050, 0x5, 0x0, 0x0, 0x543c0200
193 #define IOMUXC_PAD_GPIO_IO16__LPUART4_CTS_B 0x543c0050, 0x6, 0x543c0420, 0x0, 0x543c0200
194 #define IOMUXC_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x543c0050, 0x7, 0x543c03a8, 0x0, 0x543c0200
195 #define IOMUXC_PAD_GPIO_IO17__GPIO2_IO17 0x543c0054, 0x0, 0x0, 0x0, 0x543c0204
196 #define IOMUXC_PAD_GPIO_IO17__SAI3_MCLK 0x543c0054, 0x1, 0x0, 0x0, 0x543c0204
197 #define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x543c0054, 0x2, 0x0, 0x0, 0x543c0204
198 #define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x543c0054, 0x3, 0x0, 0x0, 0x543c0204
199 #define IOMUXC_PAD_GPIO_IO17__LPUART3_RTS_B 0x543c0054, 0x4, 0x0, 0x0, 0x543c0204
200 #define IOMUXC_PAD_GPIO_IO17__LPSPI4_PCS1 0x543c0054, 0x5, 0x0, 0x0, 0x543c0204
201 #define IOMUXC_PAD_GPIO_IO17__LPUART4_RTS_B 0x543c0054, 0x6, 0x0, 0x0, 0x543c0204
202 #define IOMUXC_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x543c0054, 0x7, 0x543c03ac, 0x0, 0x543c0204
203 #define IOMUXC_PAD_GPIO_IO18__GPIO2_IO18 0x543c0058, 0x0, 0x0, 0x0, 0x543c0208
204 #define IOMUXC_PAD_GPIO_IO18__SAI3_RX_BCLK 0x543c0058, 0x1, 0x543c044c, 0x0, 0x543c0208
205 #define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x543c0058, 0x2, 0x0, 0x0, 0x543c0208
206 #define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x543c0058, 0x3, 0x0, 0x0, 0x543c0208
207 #define IOMUXC_PAD_GPIO_IO18__LPSPI5_PCS0 0x543c0058, 0x4, 0x0, 0x0, 0x543c0208
208 #define IOMUXC_PAD_GPIO_IO18__LPSPI4_PCS0 0x543c0058, 0x5, 0x0, 0x0, 0x543c0208
209 #define IOMUXC_PAD_GPIO_IO18__TPM5_CH2 0x543c0058, 0x6, 0x0, 0x0, 0x543c0208
210 #define IOMUXC_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x543c0058, 0x7, 0x543c03b0, 0x0, 0x543c0208
211 #define IOMUXC_PAD_GPIO_IO19__GPIO2_IO19 0x543c005c, 0x0, 0x0, 0x0, 0x543c020c
212 #define IOMUXC_PAD_GPIO_IO19__SAI3_RX_SYNC 0x543c005c, 0x1, 0x543c0450, 0x1, 0x543c020c
213 #define IOMUXC_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x543c005c, 0x2, 0x543c0444, 0x1, 0x543c020c
214 #define IOMUXC_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x543c005c, 0x3, 0x0, 0x0, 0x543c020c
215 #define IOMUXC_PAD_GPIO_IO19__LPSPI5_SIN 0x543c005c, 0x4, 0x0, 0x0, 0x543c020c
216 #define IOMUXC_PAD_GPIO_IO19__LPSPI4_SIN 0x543c005c, 0x5, 0x0, 0x0, 0x543c020c
217 #define IOMUXC_PAD_GPIO_IO19__TPM6_CH2 0x543c005c, 0x6, 0x0, 0x0, 0x543c020c
218 #define IOMUXC_PAD_GPIO_IO19__SAI3_TX_DATA00 0x543c005c, 0x7, 0x0, 0x0, 0x543c020c
219 #define IOMUXC_PAD_GPIO_IO20__GPIO2_IO20 0x543c0060, 0x0, 0x0, 0x0, 0x543c0210
220 #define IOMUXC_PAD_GPIO_IO20__SAI3_RX_DATA00 0x543c0060, 0x1, 0x0, 0x0, 0x543c0210
221 #define IOMUXC_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x543c0060, 0x2, 0x543c0438, 0x1, 0x543c0210
222 #define IOMUXC_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x543c0060, 0x3, 0x0, 0x0, 0x543c0210
223 #define IOMUXC_PAD_GPIO_IO20__LPSPI5_SOUT 0x543c0060, 0x4, 0x0, 0x0, 0x543c0210
224 #define IOMUXC_PAD_GPIO_IO20__LPSPI4_SOUT 0x543c0060, 0x5, 0x0, 0x0, 0x543c0210
225 #define IOMUXC_PAD_GPIO_IO20__TPM3_CH1 0x543c0060, 0x6, 0x0, 0x0, 0x543c0210
226 #define IOMUXC_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x543c0060, 0x7, 0x543c03b4, 0x0, 0x543c0210
227 #define IOMUXC_PAD_GPIO_IO21__GPIO2_IO21 0x543c0064, 0x0, 0x0, 0x0, 0x543c0214
228 #define IOMUXC_PAD_GPIO_IO21__SAI3_TX_DATA00 0x543c0064, 0x1, 0x0, 0x0, 0x543c0214
229 #define IOMUXC_PAD_GPIO_IO21__PDM_CLK 0x543c0064, 0x2, 0x0, 0x0, 0x543c0214
230 #define IOMUXC_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x543c0064, 0x3, 0x0, 0x0, 0x543c0214
231 #define IOMUXC_PAD_GPIO_IO21__LPSPI5_SCK 0x543c0064, 0x4, 0x0, 0x0, 0x543c0214
232 #define IOMUXC_PAD_GPIO_IO21__LPSPI4_SCK 0x543c0064, 0x5, 0x0, 0x0, 0x543c0214
233 #define IOMUXC_PAD_GPIO_IO21__TPM4_CH1 0x543c0064, 0x6, 0x0, 0x0, 0x543c0214
234 #define IOMUXC_PAD_GPIO_IO21__SAI3_RX_BCLK 0x543c0064, 0x7, 0x543c044c, 0x1, 0x543c0214
235 #define IOMUXC_PAD_GPIO_IO22__GPIO2_IO22 0x543c0068, 0x0, 0x0, 0x0, 0x543c0218
236 #define IOMUXC_PAD_GPIO_IO22__USDHC3_CLK 0x543c0068, 0x1, 0x543c0458, 0x0, 0x543c0218
237 #define IOMUXC_PAD_GPIO_IO22__SPDIF_IN 0x543c0068, 0x2, 0x543c0454, 0x0, 0x543c0218
238 #define IOMUXC_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x543c0068, 0x3, 0x0, 0x0, 0x543c0218
239 #define IOMUXC_PAD_GPIO_IO22__TPM5_CH1 0x543c0068, 0x4, 0x0, 0x0, 0x543c0218
240 #define IOMUXC_PAD_GPIO_IO22__TPM6_EXTCLK 0x543c0068, 0x5, 0x0, 0x0, 0x543c0218
241 #define IOMUXC_PAD_GPIO_IO22__LPI2C5_SDA 0x543c0068, 0x6, 0x543c03ec, 0x1, 0x543c0218
242 #define IOMUXC_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x543c0068, 0x7, 0x543c03b8, 0x0, 0x543c0218
243 #define IOMUXC_PAD_GPIO_IO23__GPIO2_IO23 0x543c006c, 0x0, 0x0, 0x0, 0x543c021c
244 #define IOMUXC_PAD_GPIO_IO23__USDHC3_CMD 0x543c006c, 0x1, 0x543c045c, 0x0, 0x543c021c
245 #define IOMUXC_PAD_GPIO_IO23__SPDIF_OUT 0x543c006c, 0x2, 0x0, 0x0, 0x543c021c
246 #define IOMUXC_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x543c006c, 0x3, 0x0, 0x0, 0x543c021c
247 #define IOMUXC_PAD_GPIO_IO23__TPM6_CH1 0x543c006c, 0x4, 0x0, 0x0, 0x543c021c
248 #define IOMUXC_PAD_GPIO_IO23__LPI2C5_SCL 0x543c006c, 0x6, 0x543c03e8, 0x1, 0x543c021c
249 #define IOMUXC_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x543c006c, 0x7, 0x543c03bc, 0x0, 0x543c021c
250 #define IOMUXC_PAD_GPIO_IO24__GPIO2_IO24 0x543c0070, 0x0, 0x0, 0x0, 0x543c0220
251 #define IOMUXC_PAD_GPIO_IO24__USDHC3_DATA0 0x543c0070, 0x1, 0x543c0460, 0x0, 0x543c0220
252 #define IOMUXC_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x543c0070, 0x3, 0x0, 0x0, 0x543c0220
253 #define IOMUXC_PAD_GPIO_IO24__TPM3_CH3 0x543c0070, 0x4, 0x0, 0x0, 0x543c0220
254 #define IOMUXC_PAD_GPIO_IO24__JTAG_MUX_TDO 0x543c0070, 0x5, 0x0, 0x0, 0x543c0220
255 #define IOMUXC_PAD_GPIO_IO24__LPSPI6_PCS1 0x543c0070, 0x6, 0x0, 0x0, 0x543c0220
256 #define IOMUXC_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x543c0070, 0x7, 0x543c03c0, 0x0, 0x543c0220
257 #define IOMUXC_PAD_GPIO_IO25__GPIO2_IO25 0x543c0074, 0x0, 0x0, 0x0, 0x543c0224
258 #define IOMUXC_PAD_GPIO_IO25__USDHC3_DATA1 0x543c0074, 0x1, 0x543c0464, 0x0, 0x543c0224
259 #define IOMUXC_PAD_GPIO_IO25__CAN2_TX 0x543c0074, 0x2, 0x0, 0x0, 0x543c0224
260 #define IOMUXC_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x543c0074, 0x3, 0x0, 0x0, 0x543c0224
261 #define IOMUXC_PAD_GPIO_IO25__TPM4_CH3 0x543c0074, 0x4, 0x0, 0x0, 0x543c0224
262 #define IOMUXC_PAD_GPIO_IO25__JTAG_MUX_TCK 0x543c0074, 0x5, 0x543c03d4, 0x1, 0x543c0224
263 #define IOMUXC_PAD_GPIO_IO25__LPSPI7_PCS1 0x543c0074, 0x6, 0x0, 0x0, 0x543c0224
264 #define IOMUXC_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x543c0074, 0x7, 0x543c03c4, 0x0, 0x543c0224
265 #define IOMUXC_PAD_GPIO_IO26__GPIO2_IO26 0x543c0078, 0x0, 0x0, 0x0, 0x543c0228
266 #define IOMUXC_PAD_GPIO_IO26__USDHC3_DATA2 0x543c0078, 0x1, 0x543c0468, 0x0, 0x543c0228
267 #define IOMUXC_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x543c0078, 0x2, 0x543c043c, 0x1, 0x543c0228
268 #define IOMUXC_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x543c0078, 0x3, 0x0, 0x0, 0x543c0228
269 #define IOMUXC_PAD_GPIO_IO26__TPM5_CH3 0x543c0078, 0x4, 0x0, 0x0, 0x543c0228
270 #define IOMUXC_PAD_GPIO_IO26__JTAG_MUX_TDI 0x543c0078, 0x5, 0x543c03d8, 0x1, 0x543c0228
271 #define IOMUXC_PAD_GPIO_IO26__LPSPI8_PCS1 0x543c0078, 0x6, 0x0, 0x0, 0x543c0228
272 #define IOMUXC_PAD_GPIO_IO26__SAI3_TX_SYNC 0x543c0078, 0x7, 0x0, 0x0, 0x543c0228
273 #define IOMUXC_PAD_GPIO_IO27__GPIO2_IO27 0x543c007c, 0x0, 0x0, 0x0, 0x543c022c
274 #define IOMUXC_PAD_GPIO_IO27__USDHC3_DATA3 0x543c007c, 0x1, 0x543c046c, 0x0, 0x543c022c
275 #define IOMUXC_PAD_GPIO_IO27__CAN2_RX 0x543c007c, 0x2, 0x543c0364, 0x1, 0x543c022c
276 #define IOMUXC_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x543c007c, 0x3, 0x0, 0x0, 0x543c022c
277 #define IOMUXC_PAD_GPIO_IO27__TPM6_CH3 0x543c007c, 0x4, 0x0, 0x0, 0x543c022c
278 #define IOMUXC_PAD_GPIO_IO27__JTAG_MUX_TMS 0x543c007c, 0x5, 0x543c03dc, 0x1, 0x543c022c
279 #define IOMUXC_PAD_GPIO_IO27__LPSPI5_PCS1 0x543c007c, 0x6, 0x0, 0x0, 0x543c022c
280 #define IOMUXC_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x543c007c, 0x7, 0x543c03c8, 0x0, 0x543c022c
281 #define IOMUXC_PAD_GPIO_IO28__GPIO2_IO28 0x543c0080, 0x0, 0x0, 0x0, 0x543c0230
282 #define IOMUXC_PAD_GPIO_IO28__LPI2C3_SDA 0x543c0080, 0x1, 0x543c03e4, 0x1, 0x543c0230
283 #define IOMUXC_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x543c0080, 0x7, 0x0, 0x0, 0x543c0230
284 #define IOMUXC_PAD_GPIO_IO29__GPIO2_IO29 0x543c0084, 0x0, 0x0, 0x0, 0x543c0234
285 #define IOMUXC_PAD_GPIO_IO29__LPI2C3_SCL 0x543c0084, 0x1, 0x543c03e0, 0x1, 0x543c0234
286 #define IOMUXC_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x543c0084, 0x7, 0x0, 0x0, 0x543c0234
287 #define IOMUXC_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x543c0088, 0x0, 0x0, 0x0, 0x543c0238
288 #define IOMUXC_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x543c0088, 0x4, 0x0, 0x0, 0x543c0238
289 #define IOMUXC_PAD_CCM_CLKO1__GPIO3_IO26 0x543c0088, 0x5, 0x0, 0x0, 0x543c0238
290 #define IOMUXC_PAD_CCM_CLKO2__GPIO3_IO27 0x543c008c, 0x5, 0x0, 0x0, 0x543c023c
291 #define IOMUXC_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x543c008c, 0x0, 0x0, 0x0, 0x543c023c
292 #define IOMUXC_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x543c008c, 0x4, 0x543c03c8, 0x1, 0x543c023c
293 #define IOMUXC_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x543c0090, 0x0, 0x0, 0x0, 0x543c0240
294 #define IOMUXC_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x543c0090, 0x4, 0x0, 0x0, 0x543c0240
295 #define IOMUXC_PAD_CCM_CLKO3__GPIO4_IO28 0x543c0090, 0x5, 0x0, 0x0, 0x543c0240
296 #define IOMUXC_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x543c0094, 0x0, 0x0, 0x0, 0x543c0244
297 #define IOMUXC_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x543c0094, 0x4, 0x0, 0x0, 0x543c0244
298 #define IOMUXC_PAD_CCM_CLKO4__GPIO4_IO29 0x543c0094, 0x5, 0x0, 0x0, 0x543c0244
299 #define IOMUXC_PAD_ENET1_MDC__ENET_QOS_MDC 0x543c0098, 0x0, 0x0, 0x0, 0x543c0248
300 #define IOMUXC_PAD_ENET1_MDC__LPUART3_DCB_B 0x543c0098, 0x1, 0x0, 0x0, 0x543c0248
301 #define IOMUXC_PAD_ENET1_MDC__I3C2_SCL 0x543c0098, 0x2, 0x543c03cc, 0x0, 0x543c0248
302 #define IOMUXC_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x543c0098, 0x3, 0x0, 0x0, 0x543c0248
303 #define IOMUXC_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x543c0098, 0x4, 0x0, 0x0, 0x543c0248
304 #define IOMUXC_PAD_ENET1_MDC__GPIO4_IO00 0x543c0098, 0x5, 0x0, 0x0, 0x543c0248
305 #define IOMUXC_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x543c009c, 0x0, 0x0, 0x0, 0x543c024c
306 #define IOMUXC_PAD_ENET1_MDIO__LPUART3_RIN_B 0x543c009c, 0x1, 0x0, 0x0, 0x543c024c
307 #define IOMUXC_PAD_ENET1_MDIO__I3C2_SDA 0x543c009c, 0x2, 0x543c03d0, 0x0, 0x543c024c
308 #define IOMUXC_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x543c009c, 0x3, 0x0, 0x0, 0x543c024c
309 #define IOMUXC_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x543c009c, 0x4, 0x0, 0x0, 0x543c024c
310 #define IOMUXC_PAD_ENET1_MDIO__GPIO4_IO01 0x543c009c, 0x5, 0x0, 0x0, 0x543c024c
311 #define IOMUXC_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x543c00a0, 0x0, 0x0, 0x0, 0x543c0250
312 #define IOMUXC_PAD_ENET1_TD3__CAN2_TX 0x543c00a0, 0x2, 0x0, 0x0, 0x543c0250
313 #define IOMUXC_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x543c00a0, 0x3, 0x0, 0x0, 0x543c0250
314 #define IOMUXC_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x543c00a0, 0x4, 0x0, 0x0, 0x543c0250
315 #define IOMUXC_PAD_ENET1_TD3__GPIO4_IO02 0x543c00a0, 0x5, 0x0, 0x0, 0x543c0250
316 #define IOMUXC_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x543c00a4, 0x0, 0x0, 0x0, 0x543c0254
317 #define IOMUXC_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x543c00a4, 0x1, 0x0, 0x0, 0x543c0254
318 #define IOMUXC_PAD_ENET1_TD2__CAN2_RX 0x543c00a4, 0x2, 0x543c0364, 0x2, 0x543c0254
319 #define IOMUXC_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x543c00a4, 0x3, 0x0, 0x0, 0x543c0254
320 #define IOMUXC_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x543c00a4, 0x4, 0x0, 0x0, 0x543c0254
321 #define IOMUXC_PAD_ENET1_TD2__GPIO4_IO03 0x543c00a4, 0x5, 0x0, 0x0, 0x543c0254
322 #define IOMUXC_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x543c00a8, 0x0, 0x0, 0x0, 0x543c0258
323 #define IOMUXC_PAD_ENET1_TD1__LPUART3_RTS_B 0x543c00a8, 0x1, 0x0, 0x0, 0x543c0258
324 #define IOMUXC_PAD_ENET1_TD1__I3C2_PUR 0x543c00a8, 0x2, 0x0, 0x0, 0x543c0258
325 #define IOMUXC_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x543c00a8, 0x3, 0x0, 0x0, 0x543c0258
326 #define IOMUXC_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x543c00a8, 0x4, 0x0, 0x0, 0x543c0258
327 #define IOMUXC_PAD_ENET1_TD1__GPIO4_IO04 0x543c00a8, 0x5, 0x0, 0x0, 0x543c0258
328 #define IOMUXC_PAD_ENET1_TD1__I3C2_PUR_B 0x543c00a8, 0x6, 0x0, 0x0, 0x543c0258
329 #define IOMUXC_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x543c00ac, 0x0, 0x0, 0x0, 0x543c025c
330 #define IOMUXC_PAD_ENET1_TD0__LPUART3_TX 0x543c00ac, 0x1, 0x543c041c, 0x1, 0x543c025c
331 #define IOMUXC_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x543c00ac, 0x4, 0x0, 0x0, 0x543c025c
332 #define IOMUXC_PAD_ENET1_TD0__GPIO4_IO05 0x543c00ac, 0x5, 0x0, 0x0, 0x543c025c
333 #define IOMUXC_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x543c00b0, 0x0, 0x0, 0x0, 0x543c0260
334 #define IOMUXC_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x543c00b0, 0x1, 0x0, 0x0, 0x543c0260
335 #define IOMUXC_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x543c00b0, 0x4, 0x0, 0x0, 0x543c0260
336 #define IOMUXC_PAD_ENET1_TX_CTL__GPIO4_IO06 0x543c00b0, 0x5, 0x0, 0x0, 0x543c0260
337 #define IOMUXC_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x543c00b4, 0x0, 0x0, 0x0, 0x543c0264
338 #define IOMUXC_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x543c00b4, 0x1, 0x0, 0x0, 0x543c0264
339 #define IOMUXC_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x543c00b4, 0x4, 0x0, 0x0, 0x543c0264
340 #define IOMUXC_PAD_ENET1_TXC__GPIO4_IO07 0x543c00b4, 0x5, 0x0, 0x0, 0x543c0264
341 #define IOMUXC_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x543c00b8, 0x0, 0x0, 0x0, 0x543c0268
342 #define IOMUXC_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x543c00b8, 0x1, 0x0, 0x0, 0x543c0268
343 #define IOMUXC_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x543c00b8, 0x3, 0x0, 0x0, 0x543c0268
344 #define IOMUXC_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x543c00b8, 0x4, 0x0, 0x0, 0x543c0268
345 #define IOMUXC_PAD_ENET1_RX_CTL__GPIO4_IO08 0x543c00b8, 0x5, 0x0, 0x0, 0x543c0268
346 #define IOMUXC_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x543c00bc, 0x0, 0x0, 0x0, 0x543c026c
347 #define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x543c00bc, 0x1, 0x0, 0x0, 0x543c026c
348 #define IOMUXC_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x543c00bc, 0x4, 0x0, 0x0, 0x543c026c
349 #define IOMUXC_PAD_ENET1_RXC__GPIO4_IO09 0x543c00bc, 0x5, 0x0, 0x0, 0x543c026c
350 #define IOMUXC_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x543c00c0, 0x0, 0x0, 0x0, 0x543c0270
351 #define IOMUXC_PAD_ENET1_RD0__LPUART3_RX 0x543c00c0, 0x1, 0x543c0418, 0x1, 0x543c0270
352 #define IOMUXC_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x543c00c0, 0x4, 0x0, 0x0, 0x543c0270
353 #define IOMUXC_PAD_ENET1_RD0__GPIO4_IO10 0x543c00c0, 0x5, 0x0, 0x0, 0x543c0270
354 #define IOMUXC_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x543c00c4, 0x0, 0x0, 0x0, 0x543c0274
355 #define IOMUXC_PAD_ENET1_RD1__LPUART3_CTS_B 0x543c00c4, 0x1, 0x543c0414, 0x1, 0x543c0274
356 #define IOMUXC_PAD_ENET1_RD1__LPTMR2_ALT1 0x543c00c4, 0x3, 0x543c0408, 0x0, 0x543c0274
357 #define IOMUXC_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x543c00c4, 0x4, 0x0, 0x0, 0x543c0274
358 #define IOMUXC_PAD_ENET1_RD1__GPIO4_IO11 0x543c00c4, 0x5, 0x0, 0x0, 0x543c0274
359 #define IOMUXC_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x543c00c8, 0x0, 0x0, 0x0, 0x543c0278
360 #define IOMUXC_PAD_ENET1_RD2__LPTMR2_ALT2 0x543c00c8, 0x3, 0x543c040c, 0x0, 0x543c0278
361 #define IOMUXC_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x543c00c8, 0x4, 0x0, 0x0, 0x543c0278
362 #define IOMUXC_PAD_ENET1_RD2__GPIO4_IO12 0x543c00c8, 0x5, 0x0, 0x0, 0x543c0278
363 #define IOMUXC_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x543c00cc, 0x0, 0x0, 0x0, 0x543c027c
364 #define IOMUXC_PAD_ENET1_RD3__LPTMR2_ALT3 0x543c00cc, 0x3, 0x543c0410, 0x0, 0x543c027c
365 #define IOMUXC_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x543c00cc, 0x4, 0x0, 0x0, 0x543c027c
366 #define IOMUXC_PAD_ENET1_RD3__GPIO4_IO13 0x543c00cc, 0x5, 0x0, 0x0, 0x543c027c
367 #define IOMUXC_PAD_ENET2_MDC__ENET1_MDC 0x543c00d0, 0x0, 0x0, 0x0, 0x543c0280
368 #define IOMUXC_PAD_ENET2_MDC__LPUART4_DCB_B 0x543c00d0, 0x1, 0x0, 0x0, 0x543c0280
369 #define IOMUXC_PAD_ENET2_MDC__SAI2_RX_SYNC 0x543c00d0, 0x2, 0x0, 0x0, 0x543c0280
370 #define IOMUXC_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x543c00d0, 0x4, 0x0, 0x0, 0x543c0280
371 #define IOMUXC_PAD_ENET2_MDC__GPIO4_IO14 0x543c00d0, 0x5, 0x0, 0x0, 0x543c0280
372 #define IOMUXC_PAD_ENET2_MDIO__ENET1_MDIO 0x543c00d4, 0x0, 0x0, 0x0, 0x543c0284
373 #define IOMUXC_PAD_ENET2_MDIO__LPUART4_RIN_B 0x543c00d4, 0x1, 0x0, 0x0, 0x543c0284
374 #define IOMUXC_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x543c00d4, 0x2, 0x0, 0x0, 0x543c0284
375 #define IOMUXC_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x543c00d4, 0x4, 0x0, 0x0, 0x543c0284
376 #define IOMUXC_PAD_ENET2_MDIO__GPIO4_IO15 0x543c00d4, 0x5, 0x0, 0x0, 0x543c0284
377 #define IOMUXC_PAD_ENET2_TD3__SAI2_RX_DATA00 0x543c00d8, 0x2, 0x0, 0x0, 0x543c0288
378 #define IOMUXC_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x543c00d8, 0x4, 0x0, 0x0, 0x543c0288
379 #define IOMUXC_PAD_ENET2_TD3__GPIO4_IO16 0x543c00d8, 0x5, 0x0, 0x0, 0x543c0288
380 #define IOMUXC_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x543c00d8, 0x0, 0x0, 0x0, 0x543c0288
381 #define IOMUXC_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x543c00dc, 0x0, 0x0, 0x0, 0x543c028c
382 #define IOMUXC_PAD_ENET2_TD2__ENET1_TX_CLK 0x543c00dc, 0x1, 0x0, 0x0, 0x543c028c
383 #define IOMUXC_PAD_ENET2_TD2__SAI2_RX_DATA01 0x543c00dc, 0x2, 0x0, 0x0, 0x543c028c
384 #define IOMUXC_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x543c00dc, 0x4, 0x0, 0x0, 0x543c028c
385 #define IOMUXC_PAD_ENET2_TD2__GPIO4_IO17 0x543c00dc, 0x5, 0x0, 0x0, 0x543c028c
386 #define IOMUXC_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x543c00e0, 0x0, 0x0, 0x0, 0x543c0290
387 #define IOMUXC_PAD_ENET2_TD1__LPUART4_RTS_B 0x543c00e0, 0x1, 0x0, 0x0, 0x543c0290
388 #define IOMUXC_PAD_ENET2_TD1__SAI2_RX_DATA02 0x543c00e0, 0x2, 0x0, 0x0, 0x543c0290
389 #define IOMUXC_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x543c00e0, 0x4, 0x0, 0x0, 0x543c0290
390 #define IOMUXC_PAD_ENET2_TD1__GPIO4_IO18 0x543c00e0, 0x5, 0x0, 0x0, 0x543c0290
391 #define IOMUXC_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x543c00e4, 0x0, 0x0, 0x0, 0x543c0294
392 #define IOMUXC_PAD_ENET2_TD0__LPUART4_TX 0x543c00e4, 0x1, 0x543c0428, 0x1, 0x543c0294
393 #define IOMUXC_PAD_ENET2_TD0__SAI2_RX_DATA03 0x543c00e4, 0x2, 0x0, 0x0, 0x543c0294
394 #define IOMUXC_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x543c00e4, 0x4, 0x0, 0x0, 0x543c0294
395 #define IOMUXC_PAD_ENET2_TD0__GPIO4_IO19 0x543c00e4, 0x5, 0x0, 0x0, 0x543c0294
396 #define IOMUXC_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x543c00e8, 0x0, 0x0, 0x0, 0x543c0298
397 #define IOMUXC_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x543c00e8, 0x1, 0x0, 0x0, 0x543c0298
398 #define IOMUXC_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x543c00e8, 0x2, 0x0, 0x0, 0x543c0298
399 #define IOMUXC_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x543c00e8, 0x4, 0x0, 0x0, 0x543c0298
400 #define IOMUXC_PAD_ENET2_TX_CTL__GPIO4_IO20 0x543c00e8, 0x5, 0x0, 0x0, 0x543c0298
401 #define IOMUXC_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x543c00ec, 0x0, 0x0, 0x0, 0x543c029c
402 #define IOMUXC_PAD_ENET2_TXC__ENET1_TX_ER 0x543c00ec, 0x1, 0x0, 0x0, 0x543c029c
403 #define IOMUXC_PAD_ENET2_TXC__SAI2_TX_BCLK 0x543c00ec, 0x2, 0x0, 0x0, 0x543c029c
404 #define IOMUXC_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x543c00ec, 0x4, 0x0, 0x0, 0x543c029c
405 #define IOMUXC_PAD_ENET2_TXC__GPIO4_IO21 0x543c00ec, 0x5, 0x0, 0x0, 0x543c029c
406 #define IOMUXC_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x543c00f0, 0x0, 0x0, 0x0, 0x543c02a0
407 #define IOMUXC_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x543c00f0, 0x1, 0x0, 0x0, 0x543c02a0
408 #define IOMUXC_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x543c00f0, 0x2, 0x0, 0x0, 0x543c02a0
409 #define IOMUXC_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x543c00f0, 0x4, 0x0, 0x0, 0x543c02a0
410 #define IOMUXC_PAD_ENET2_RX_CTL__GPIO4_IO22 0x543c00f0, 0x5, 0x0, 0x0, 0x543c02a0
411 #define IOMUXC_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x543c00f4, 0x0, 0x0, 0x0, 0x543c02a4
412 #define IOMUXC_PAD_ENET2_RXC__ENET1_RX_ER 0x543c00f4, 0x1, 0x0, 0x0, 0x543c02a4
413 #define IOMUXC_PAD_ENET2_RXC__SAI2_TX_DATA01 0x543c00f4, 0x2, 0x0, 0x0, 0x543c02a4
414 #define IOMUXC_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x543c00f4, 0x4, 0x0, 0x0, 0x543c02a4
415 #define IOMUXC_PAD_ENET2_RXC__GPIO4_IO23 0x543c00f4, 0x5, 0x0, 0x0, 0x543c02a4
416 #define IOMUXC_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x543c00f8, 0x0, 0x0, 0x0, 0x543c02a8
417 #define IOMUXC_PAD_ENET2_RD0__LPUART4_RX 0x543c00f8, 0x1, 0x543c0424, 0x1, 0x543c02a8
418 #define IOMUXC_PAD_ENET2_RD0__SAI2_TX_DATA02 0x543c00f8, 0x2, 0x0, 0x0, 0x543c02a8
419 #define IOMUXC_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x543c00f8, 0x4, 0x0, 0x0, 0x543c02a8
420 #define IOMUXC_PAD_ENET2_RD0__GPIO4_IO24 0x543c00f8, 0x5, 0x0, 0x0, 0x543c02a8
421 #define IOMUXC_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x543c00fc, 0x0, 0x0, 0x0, 0x543c02ac
422 #define IOMUXC_PAD_ENET2_RD1__SPDIF_IN 0x543c00fc, 0x1, 0x543c0454, 0x1, 0x543c02ac
423 #define IOMUXC_PAD_ENET2_RD1__SAI2_TX_DATA03 0x543c00fc, 0x2, 0x0, 0x0, 0x543c02ac
424 #define IOMUXC_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x543c00fc, 0x4, 0x0, 0x0, 0x543c02ac
425 #define IOMUXC_PAD_ENET2_RD1__GPIO4_IO25 0x543c00fc, 0x5, 0x0, 0x0, 0x543c02ac
426 #define IOMUXC_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x543c0100, 0x0, 0x0, 0x0, 0x543c02b0
427 #define IOMUXC_PAD_ENET2_RD2__LPUART4_CTS_B 0x543c0100, 0x1, 0x543c0420, 0x1, 0x543c02b0
428 #define IOMUXC_PAD_ENET2_RD2__SAI2_MCLK 0x543c0100, 0x2, 0x0, 0x0, 0x543c02b0
429 #define IOMUXC_PAD_ENET2_RD2__MQS2_RIGHT 0x543c0100, 0x3, 0x0, 0x0, 0x543c02b0
430 #define IOMUXC_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x543c0100, 0x4, 0x0, 0x0, 0x543c02b0
431 #define IOMUXC_PAD_ENET2_RD2__GPIO4_IO26 0x543c0100, 0x5, 0x0, 0x0, 0x543c02b0
432 #define IOMUXC_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x543c0104, 0x0, 0x0, 0x0, 0x543c02b4
433 #define IOMUXC_PAD_ENET2_RD3__SPDIF_OUT 0x543c0104, 0x1, 0x0, 0x0, 0x543c02b4
434 #define IOMUXC_PAD_ENET2_RD3__SPDIF_IN 0x543c0104, 0x2, 0x543c0454, 0x2, 0x543c02b4
435 #define IOMUXC_PAD_ENET2_RD3__MQS2_LEFT 0x543c0104, 0x3, 0x0, 0x0, 0x543c02b4
436 #define IOMUXC_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x543c0104, 0x4, 0x0, 0x0, 0x543c02b4
437 #define IOMUXC_PAD_ENET2_RD3__GPIO4_IO27 0x543c0104, 0x5, 0x0, 0x0, 0x543c02b4
438 #define IOMUXC_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x543c0108, 0x4, 0x543c038c, 0x1, 0x543c02b8
439 #define IOMUXC_PAD_SD1_CLK__GPIO3_IO08 0x543c0108, 0x5, 0x0, 0x0, 0x543c02b8
440 #define IOMUXC_PAD_SD1_CLK__USDHC1_CLK 0x543c0108, 0x0, 0x0, 0x0, 0x543c02b8
441 #define IOMUXC_PAD_SD1_CMD__USDHC1_CMD 0x543c010c, 0x0, 0x0, 0x0, 0x543c02bc
442 #define IOMUXC_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x543c010c, 0x4, 0x543c0390, 0x1, 0x543c02bc
443 #define IOMUXC_PAD_SD1_CMD__GPIO3_IO09 0x543c010c, 0x5, 0x0, 0x0, 0x543c02bc
444 #define IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0 0x543c0110, 0x0, 0x0, 0x0, 0x543c02c0
445 #define IOMUXC_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x543c0110, 0x4, 0x543c0394, 0x1, 0x543c02c0
446 #define IOMUXC_PAD_SD1_DATA0__GPIO3_IO10 0x543c0110, 0x5, 0x0, 0x0, 0x543c02c0
447 #define IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1 0x543c0114, 0x0, 0x0, 0x0, 0x543c02c4
448 #define IOMUXC_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x543c0114, 0x4, 0x543c0398, 0x1, 0x543c02c4
449 #define IOMUXC_PAD_SD1_DATA1__GPIO3_IO11 0x543c0114, 0x5, 0x0, 0x0, 0x543c02c4
450 #define IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2 0x543c0118, 0x0, 0x0, 0x0, 0x543c02c8
451 #define IOMUXC_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x543c0118, 0x4, 0x0, 0x0, 0x543c02c8
452 #define IOMUXC_PAD_SD1_DATA2__GPIO3_IO12 0x543c0118, 0x5, 0x0, 0x0, 0x543c02c8
453 #define IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3 0x543c011c, 0x0, 0x0, 0x0, 0x543c02cc
454 #define IOMUXC_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x543c011c, 0x1, 0x0, 0x0, 0x543c02cc
455 #define IOMUXC_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x543c011c, 0x4, 0x543c039c, 0x1, 0x543c02cc
456 #define IOMUXC_PAD_SD1_DATA3__GPIO3_IO13 0x543c011c, 0x5, 0x0, 0x0, 0x543c02cc
457 #define IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4 0x543c0120, 0x0, 0x0, 0x0, 0x543c02d0
458 #define IOMUXC_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x543c0120, 0x1, 0x0, 0x0, 0x543c02d0
459 #define IOMUXC_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x543c0120, 0x4, 0x543c03a0, 0x1, 0x543c02d0
460 #define IOMUXC_PAD_SD1_DATA4__GPIO3_IO14 0x543c0120, 0x5, 0x0, 0x0, 0x543c02d0
461 #define IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5 0x543c0124, 0x0, 0x0, 0x0, 0x543c02d4
462 #define IOMUXC_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x543c0124, 0x1, 0x0, 0x0, 0x543c02d4
463 #define IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B 0x543c0124, 0x2, 0x0, 0x0, 0x543c02d4
464 #define IOMUXC_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x543c0124, 0x4, 0x543c03a4, 0x1, 0x543c02d4
465 #define IOMUXC_PAD_SD1_DATA5__GPIO3_IO15 0x543c0124, 0x5, 0x0, 0x0, 0x543c02d4
466 #define IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6 0x543c0128, 0x0, 0x0, 0x0, 0x543c02d8
467 #define IOMUXC_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x543c0128, 0x1, 0x0, 0x0, 0x543c02d8
468 #define IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B 0x543c0128, 0x2, 0x0, 0x0, 0x543c02d8
469 #define IOMUXC_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x543c0128, 0x4, 0x543c03a8, 0x1, 0x543c02d8
470 #define IOMUXC_PAD_SD1_DATA6__GPIO3_IO16 0x543c0128, 0x5, 0x0, 0x0, 0x543c02d8
471 #define IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7 0x543c012c, 0x0, 0x0, 0x0, 0x543c02dc
472 #define IOMUXC_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x543c012c, 0x1, 0x0, 0x0, 0x543c02dc
473 #define IOMUXC_PAD_SD1_DATA7__USDHC1_WP 0x543c012c, 0x2, 0x0, 0x0, 0x543c02dc
474 #define IOMUXC_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x543c012c, 0x4, 0x543c03ac, 0x1, 0x543c02dc
475 #define IOMUXC_PAD_SD1_DATA7__GPIO3_IO17 0x543c012c, 0x5, 0x0, 0x0, 0x543c02dc
476 #define IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE 0x543c0130, 0x0, 0x0, 0x0, 0x543c02e0
477 #define IOMUXC_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x543c0130, 0x1, 0x0, 0x0, 0x543c02e0
478 #define IOMUXC_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x543c0130, 0x4, 0x543c03b0, 0x1, 0x543c02e0
479 #define IOMUXC_PAD_SD1_STROBE__GPIO3_IO18 0x543c0130, 0x5, 0x0, 0x0, 0x543c02e0
480 #define IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT 0x543c0134, 0x0, 0x0, 0x0, 0x543c02e4
481 #define IOMUXC_PAD_SD2_VSELECT__USDHC2_WP 0x543c0134, 0x1, 0x0, 0x0, 0x543c02e4
482 #define IOMUXC_PAD_SD2_VSELECT__LPTMR2_ALT3 0x543c0134, 0x2, 0x543c0410, 0x1, 0x543c02e4
483 #define IOMUXC_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x543c0134, 0x4, 0x0, 0x0, 0x543c02e4
484 #define IOMUXC_PAD_SD2_VSELECT__GPIO3_IO19 0x543c0134, 0x5, 0x0, 0x0, 0x543c02e4
485 #define IOMUXC_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x543c0134, 0x6, 0x543c0368, 0x0, 0x543c02e4
486 #define IOMUXC_PAD_SD3_CLK__USDHC3_CLK 0x543c0138, 0x0, 0x543c0458, 0x1, 0x543c02e8
487 #define IOMUXC_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x543c0138, 0x1, 0x0, 0x0, 0x543c02e8
488 #define IOMUXC_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x543c0138, 0x4, 0x543c03b4, 0x1, 0x543c02e8
489 #define IOMUXC_PAD_SD3_CLK__GPIO3_IO20 0x543c0138, 0x5, 0x0, 0x0, 0x543c02e8
490 #define IOMUXC_PAD_SD3_CMD__USDHC3_CMD 0x543c013c, 0x0, 0x543c045c, 0x1, 0x543c02ec
491 #define IOMUXC_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x543c013c, 0x1, 0x0, 0x0, 0x543c02ec
492 #define IOMUXC_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x543c013c, 0x4, 0x0, 0x0, 0x543c02ec
493 #define IOMUXC_PAD_SD3_CMD__GPIO3_IO21 0x543c013c, 0x5, 0x0, 0x0, 0x543c02ec
494 #define IOMUXC_PAD_SD3_DATA0__USDHC3_DATA0 0x543c0140, 0x0, 0x543c0460, 0x1, 0x543c02f0
495 #define IOMUXC_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x543c0140, 0x1, 0x0, 0x0, 0x543c02f0
496 #define IOMUXC_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x543c0140, 0x4, 0x543c03b8, 0x1, 0x543c02f0
497 #define IOMUXC_PAD_SD3_DATA0__GPIO3_IO22 0x543c0140, 0x5, 0x0, 0x0, 0x543c02f0
498 #define IOMUXC_PAD_SD3_DATA1__USDHC3_DATA1 0x543c0144, 0x0, 0x543c0464, 0x1, 0x543c02f4
499 #define IOMUXC_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x543c0144, 0x1, 0x0, 0x0, 0x543c02f4
500 #define IOMUXC_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x543c0144, 0x4, 0x543c03bc, 0x1, 0x543c02f4
501 #define IOMUXC_PAD_SD3_DATA1__GPIO3_IO23 0x543c0144, 0x5, 0x0, 0x0, 0x543c02f4
502 #define IOMUXC_PAD_SD3_DATA2__USDHC3_DATA2 0x543c0148, 0x0, 0x543c0468, 0x1, 0x543c02f8
503 #define IOMUXC_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x543c0148, 0x1, 0x0, 0x0, 0x543c02f8
504 #define IOMUXC_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x543c0148, 0x4, 0x543c03c0, 0x1, 0x543c02f8
505 #define IOMUXC_PAD_SD3_DATA2__GPIO3_IO24 0x543c0148, 0x5, 0x0, 0x0, 0x543c02f8
506 #define IOMUXC_PAD_SD3_DATA3__USDHC3_DATA3 0x543c014c, 0x0, 0x543c046c, 0x1, 0x543c02fc
507 #define IOMUXC_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x543c014c, 0x1, 0x0, 0x0, 0x543c02fc
508 #define IOMUXC_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x543c014c, 0x4, 0x543c03c4, 0x1, 0x543c02fc
509 #define IOMUXC_PAD_SD3_DATA3__GPIO3_IO25 0x543c014c, 0x5, 0x0, 0x0, 0x543c02fc
510 #define IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B 0x543c0150, 0x0, 0x0, 0x0, 0x543c0300
511 #define IOMUXC_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x543c0150, 0x1, 0x0, 0x0, 0x543c0300
512 #define IOMUXC_PAD_SD2_CD_B__I3C2_SCL 0x543c0150, 0x2, 0x543c03cc, 0x1, 0x543c0300
513 #define IOMUXC_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x543c0150, 0x4, 0x543c036c, 0x1, 0x543c0300
514 #define IOMUXC_PAD_SD2_CD_B__GPIO3_IO00 0x543c0150, 0x5, 0x0, 0x0, 0x543c0300
515 #define IOMUXC_PAD_SD2_CLK__USDHC2_CLK 0x543c0154, 0x0, 0x0, 0x0, 0x543c0304
516 #define IOMUXC_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x543c0154, 0x1, 0x0, 0x0, 0x543c0304
517 #define IOMUXC_PAD_SD2_CLK__I3C2_SDA 0x543c0154, 0x2, 0x543c03d0, 0x1, 0x543c0304
518 #define IOMUXC_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x543c0154, 0x4, 0x543c0370, 0x1, 0x543c0304
519 #define IOMUXC_PAD_SD2_CLK__GPIO3_IO01 0x543c0154, 0x5, 0x0, 0x0, 0x543c0304
520 #define IOMUXC_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x543c0154, 0x6, 0x0, 0x0, 0x543c0304
521 #define IOMUXC_PAD_SD2_CMD__USDHC2_CMD 0x543c0158, 0x0, 0x0, 0x0, 0x543c0308
522 #define IOMUXC_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x543c0158, 0x1, 0x0, 0x0, 0x543c0308
523 #define IOMUXC_PAD_SD2_CMD__I3C2_PUR 0x543c0158, 0x2, 0x0, 0x0, 0x543c0308
524 #define IOMUXC_PAD_SD2_CMD__I3C2_PUR_B 0x543c0158, 0x3, 0x0, 0x0, 0x543c0308
525 #define IOMUXC_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x543c0158, 0x4, 0x543c0374, 0x1, 0x543c0308
526 #define IOMUXC_PAD_SD2_CMD__GPIO3_IO02 0x543c0158, 0x5, 0x0, 0x0, 0x543c0308
527 #define IOMUXC_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x543c0158, 0x6, 0x0, 0x0, 0x543c0308
528 #define IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0 0x543c015c, 0x0, 0x0, 0x0, 0x543c030c
529 #define IOMUXC_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x543c015c, 0x1, 0x0, 0x0, 0x543c030c
530 #define IOMUXC_PAD_SD2_DATA0__CAN2_TX 0x543c015c, 0x2, 0x0, 0x0, 0x543c030c
531 #define IOMUXC_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x543c015c, 0x4, 0x543c0378, 0x1, 0x543c030c
532 #define IOMUXC_PAD_SD2_DATA0__GPIO3_IO03 0x543c015c, 0x5, 0x0, 0x0, 0x543c030c
533 #define IOMUXC_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x543c015c, 0x6, 0x0, 0x0, 0x543c030c
534 #define IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1 0x543c0160, 0x0, 0x0, 0x0, 0x543c0310
535 #define IOMUXC_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x543c0160, 0x1, 0x0, 0x0, 0x543c0310
536 #define IOMUXC_PAD_SD2_DATA1__CAN2_RX 0x543c0160, 0x2, 0x543c0364, 0x3, 0x543c0310
537 #define IOMUXC_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x543c0160, 0x4, 0x543c037c, 0x1, 0x543c0310
538 #define IOMUXC_PAD_SD2_DATA1__GPIO3_IO04 0x543c0160, 0x5, 0x0, 0x0, 0x543c0310
539 #define IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2 0x543c0164, 0x0, 0x0, 0x0, 0x543c0314
540 #define IOMUXC_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x543c0164, 0x1, 0x0, 0x0, 0x543c0314
541 #define IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT 0x543c0164, 0x2, 0x0, 0x0, 0x543c0314
542 #define IOMUXC_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x543c0164, 0x4, 0x543c0380, 0x1, 0x543c0314
543 #define IOMUXC_PAD_SD2_DATA2__GPIO3_IO05 0x543c0164, 0x5, 0x0, 0x0, 0x543c0314
544 #define IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3 0x543c0168, 0x0, 0x0, 0x0, 0x543c0318
545 #define IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT1 0x543c0168, 0x1, 0x543c0408, 0x1, 0x543c0318
546 #define IOMUXC_PAD_SD2_DATA3__MQS2_LEFT 0x543c0168, 0x2, 0x0, 0x0, 0x543c0318
547 #define IOMUXC_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x543c0168, 0x4, 0x543c0384, 0x1, 0x543c0318
548 #define IOMUXC_PAD_SD2_DATA3__GPIO3_IO06 0x543c0168, 0x5, 0x0, 0x0, 0x543c0318
549 #define IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B 0x543c016c, 0x0, 0x0, 0x0, 0x543c031c
550 #define IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT2 0x543c016c, 0x1, 0x543c040c, 0x1, 0x543c031c
551 #define IOMUXC_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x543c016c, 0x4, 0x543c0388, 0x1, 0x543c031c
552 #define IOMUXC_PAD_SD2_RESET_B__GPIO3_IO07 0x543c016c, 0x5, 0x0, 0x0, 0x543c031c
553 #define IOMUXC_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x543c016c, 0x6, 0x0, 0x0, 0x543c031c
554 #define IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL 0x543c0170, 0x0, 0x0, 0x0, 0x543c0320
555 #define IOMUXC_PAD_I2C1_SCL__I3C1_SCL 0x543c0170, 0x1, 0x0, 0x0, 0x543c0320
556 #define IOMUXC_PAD_I2C1_SCL__LPUART1_DCB_B 0x543c0170, 0x2, 0x0, 0x0, 0x543c0320
557 #define IOMUXC_PAD_I2C1_SCL__TPM2_CH0 0x543c0170, 0x3, 0x0, 0x0, 0x543c0320
558 #define IOMUXC_PAD_I2C1_SCL__GPIO1_IO00 0x543c0170, 0x5, 0x0, 0x0, 0x543c0320
559 #define IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA 0x543c0174, 0x0, 0x0, 0x0, 0x543c0324
560 #define IOMUXC_PAD_I2C1_SDA__I3C1_SDA 0x543c0174, 0x1, 0x0, 0x0, 0x543c0324
561 #define IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B 0x543c0174, 0x2, 0x0, 0x0, 0x543c0324
562 #define IOMUXC_PAD_I2C1_SDA__TPM2_CH1 0x543c0174, 0x3, 0x0, 0x0, 0x543c0324
563 #define IOMUXC_PAD_I2C1_SDA__GPIO1_IO01 0x543c0174, 0x5, 0x0, 0x0, 0x543c0324
564 #define IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL 0x543c0178, 0x0, 0x0, 0x0, 0x543c0328
565 #define IOMUXC_PAD_I2C2_SCL__I3C1_PUR 0x543c0178, 0x1, 0x0, 0x0, 0x543c0328
566 #define IOMUXC_PAD_I2C2_SCL__LPUART2_DCB_B 0x543c0178, 0x2, 0x0, 0x0, 0x543c0328
567 #define IOMUXC_PAD_I2C2_SCL__TPM2_CH2 0x543c0178, 0x3, 0x0, 0x0, 0x543c0328
568 #define IOMUXC_PAD_I2C2_SCL__SAI1_RX_SYNC 0x543c0178, 0x4, 0x0, 0x0, 0x543c0328
569 #define IOMUXC_PAD_I2C2_SCL__GPIO1_IO02 0x543c0178, 0x5, 0x0, 0x0, 0x543c0328
570 #define IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B 0x543c0178, 0x6, 0x0, 0x0, 0x543c0328
571 #define IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA 0x543c017c, 0x0, 0x0, 0x0, 0x543c032c
572 #define IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B 0x543c017c, 0x2, 0x0, 0x0, 0x543c032c
573 #define IOMUXC_PAD_I2C2_SDA__TPM2_CH3 0x543c017c, 0x3, 0x0, 0x0, 0x543c032c
574 #define IOMUXC_PAD_I2C2_SDA__SAI1_RX_BCLK 0x543c017c, 0x4, 0x0, 0x0, 0x543c032c
575 #define IOMUXC_PAD_I2C2_SDA__GPIO1_IO03 0x543c017c, 0x5, 0x0, 0x0, 0x543c032c
576 #define IOMUXC_PAD_UART1_RXD__LPUART1_RX 0x543c0180, 0x0, 0x0, 0x0, 0x543c0330
577 #define IOMUXC_PAD_UART1_RXD__S400_UART_RX 0x543c0180, 0x1, 0x0, 0x0, 0x543c0330
578 #define IOMUXC_PAD_UART1_RXD__LPSPI2_SIN 0x543c0180, 0x2, 0x0, 0x0, 0x543c0330
579 #define IOMUXC_PAD_UART1_RXD__TPM1_CH0 0x543c0180, 0x3, 0x0, 0x0, 0x543c0330
580 #define IOMUXC_PAD_UART1_RXD__GPIO1_IO04 0x543c0180, 0x5, 0x0, 0x0, 0x543c0330
581 #define IOMUXC_PAD_UART1_TXD__LPUART1_TX 0x543c0184, 0x0, 0x0, 0x0, 0x543c0334
582 #define IOMUXC_PAD_UART1_TXD__S400_UART_TX 0x543c0184, 0x1, 0x0, 0x0, 0x543c0334
583 #define IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0 0x543c0184, 0x2, 0x0, 0x0, 0x543c0334
584 #define IOMUXC_PAD_UART1_TXD__TPM1_CH1 0x543c0184, 0x3, 0x0, 0x0, 0x543c0334
585 #define IOMUXC_PAD_UART1_TXD__GPIO1_IO05 0x543c0184, 0x5, 0x0, 0x0, 0x543c0334
586 #define IOMUXC_PAD_UART2_RXD__LPUART2_RX 0x543c0188, 0x0, 0x0, 0x0, 0x543c0338
587 #define IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B 0x543c0188, 0x1, 0x0, 0x0, 0x543c0338
588 #define IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT 0x543c0188, 0x2, 0x0, 0x0, 0x543c0338
589 #define IOMUXC_PAD_UART2_RXD__TPM1_CH2 0x543c0188, 0x3, 0x0, 0x0, 0x543c0338
590 #define IOMUXC_PAD_UART2_RXD__SAI1_MCLK 0x543c0188, 0x4, 0x543c0448, 0x0, 0x543c0338
591 #define IOMUXC_PAD_UART2_RXD__GPIO1_IO06 0x543c0188, 0x5, 0x0, 0x0, 0x543c0338
592 #define IOMUXC_PAD_UART2_TXD__LPUART2_TX 0x543c018c, 0x0, 0x0, 0x0, 0x543c033c
593 #define IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B 0x543c018c, 0x1, 0x0, 0x0, 0x543c033c
594 #define IOMUXC_PAD_UART2_TXD__LPSPI2_SCK 0x543c018c, 0x2, 0x0, 0x0, 0x543c033c
595 #define IOMUXC_PAD_UART2_TXD__TPM1_CH3 0x543c018c, 0x3, 0x0, 0x0, 0x543c033c
596 #define IOMUXC_PAD_UART2_TXD__GPIO1_IO07 0x543c018c, 0x5, 0x0, 0x0, 0x543c033c
597 #define IOMUXC_PAD_PDM_CLK__PDM_CLK 0x543c0190, 0x0, 0x0, 0x0, 0x543c0340
598 #define IOMUXC_PAD_PDM_CLK__MQS1_LEFT 0x543c0190, 0x1, 0x0, 0x0, 0x543c0340
599 #define IOMUXC_PAD_PDM_CLK__LPTMR1_ALT1 0x543c0190, 0x4, 0x0, 0x0, 0x543c0340
600 #define IOMUXC_PAD_PDM_CLK__GPIO1_IO08 0x543c0190, 0x5, 0x0, 0x0, 0x543c0340
601 #define IOMUXC_PAD_PDM_CLK__CAN1_TX 0x543c0190, 0x6, 0x0, 0x0, 0x543c0340
602 #define IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x543c0194, 0x0, 0x543c0438, 0x2, 0x543c0344
603 #define IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x543c0194, 0x1, 0x0, 0x0, 0x543c0344
604 #define IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x543c0194, 0x2, 0x0, 0x0, 0x543c0344
605 #define IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x543c0194, 0x3, 0x0, 0x0, 0x543c0344
606 #define IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x543c0194, 0x4, 0x0, 0x0, 0x543c0344
607 #define IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x543c0194, 0x5, 0x0, 0x0, 0x543c0344
608 #define IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX 0x543c0194, 0x6, 0x543c0360, 0x0, 0x543c0344
609 #define IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x543c0198, 0x0, 0x543c043c, 0x2, 0x543c0348
610 #define IOMUXC_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x543c0198, 0x1, 0x0, 0x0, 0x543c0348
611 #define IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x543c0198, 0x2, 0x0, 0x0, 0x543c0348
612 #define IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x543c0198, 0x3, 0x0, 0x0, 0x543c0348
613 #define IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x543c0198, 0x4, 0x0, 0x0, 0x543c0348
614 #define IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x543c0198, 0x5, 0x0, 0x0, 0x543c0348
615 #define IOMUXC_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x543c0198, 0x6, 0x543c0368, 0x1, 0x543c0348
616 #define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x543c019c, 0x0, 0x0, 0x0, 0x543c034c
617 #define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x543c019c, 0x1, 0x0, 0x0, 0x543c034c
618 #define IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0 0x543c019c, 0x2, 0x0, 0x0, 0x543c034c
619 #define IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B 0x543c019c, 0x3, 0x0, 0x0, 0x543c034c
620 #define IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT 0x543c019c, 0x4, 0x0, 0x0, 0x543c034c
621 #define IOMUXC_PAD_SAI1_TXFS__GPIO1_IO11 0x543c019c, 0x5, 0x0, 0x0, 0x543c034c
622 #define IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK 0x543c01a0, 0x0, 0x0, 0x0, 0x543c0350
623 #define IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B 0x543c01a0, 0x1, 0x0, 0x0, 0x543c0350
624 #define IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN 0x543c01a0, 0x2, 0x0, 0x0, 0x543c0350
625 #define IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B 0x543c01a0, 0x3, 0x0, 0x0, 0x543c0350
626 #define IOMUXC_PAD_SAI1_TXC__CAN1_RX 0x543c01a0, 0x4, 0x543c0360, 0x1, 0x543c0350
627 #define IOMUXC_PAD_SAI1_TXC__GPIO1_IO12 0x543c01a0, 0x5, 0x0, 0x0, 0x543c0350
628 #define IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x543c01a4, 0x0, 0x0, 0x0, 0x543c0354
629 #define IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B 0x543c01a4, 0x1, 0x0, 0x0, 0x543c0354
630 #define IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK 0x543c01a4, 0x2, 0x0, 0x0, 0x543c0354
631 #define IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B 0x543c01a4, 0x3, 0x0, 0x0, 0x543c0354
632 #define IOMUXC_PAD_SAI1_TXD0__CAN1_TX 0x543c01a4, 0x4, 0x0, 0x0, 0x543c0354
633 #define IOMUXC_PAD_SAI1_TXD0__GPIO1_IO13 0x543c01a4, 0x5, 0x0, 0x0, 0x543c0354
634 #define IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x543c01a8, 0x0, 0x0, 0x0, 0x543c0358
635 #define IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK 0x543c01a8, 0x1, 0x543c0448, 0x1, 0x543c0358
636 #define IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT 0x543c01a8, 0x2, 0x0, 0x0, 0x543c0358
637 #define IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B 0x543c01a8, 0x3, 0x0, 0x0, 0x543c0358
638 #define IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT 0x543c01a8, 0x4, 0x0, 0x0, 0x543c0358
639 #define IOMUXC_PAD_SAI1_RXD0__GPIO1_IO14 0x543c01a8, 0x5, 0x0, 0x0, 0x543c0358
640 #define IOMUXC_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x543c01ac, 0x0, 0x0, 0x0, 0x543c035c
641 #define IOMUXC_PAD_WDOG_ANY__GPIO1_IO15 0x543c01ac, 0x5, 0x0, 0x0, 0x543c035c
642
643 #else
644
645 #define IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI 0x443c0000, 0x0, 0x443c03d8, 0x0, 0x443c01b0
646 #define IOMUXC_PAD_DAP_TDI__MQS2_LEFT 0x443c0000, 0x1, 0x0, 0x0, 0x443c01b0
647 #define IOMUXC_PAD_DAP_TDI__CAN2_TX 0x443c0000, 0x3, 0x0, 0x0, 0x443c01b0
648 #define IOMUXC_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x443c0000, 0x4, 0x0, 0x0, 0x443c01b0
649 #define IOMUXC_PAD_DAP_TDI__GPIO3_IO28 0x443c0000, 0x5, 0x0, 0x0, 0x443c01b0
650 #define IOMUXC_PAD_DAP_TDI__LPUART5_RX 0x443c0000, 0x6, 0x443c0430, 0x0, 0x443c01b0
651 #define IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x443c0004, 0x0, 0x443c03dc, 0x0, 0x443c01b4
652 #define IOMUXC_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x443c0004, 0x4, 0x0, 0x0, 0x443c01b4
653 #define IOMUXC_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x443c0004, 0x5, 0x0, 0x0, 0x443c01b4
654 #define IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x443c0004, 0x6, 0x0, 0x0, 0x443c01b4
655 #define IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x443c0008, 0x0, 0x443c03d4, 0x0, 0x443c01b8
656 #define IOMUXC_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x443c0008, 0x4, 0x0, 0x0, 0x443c01b8
657 #define IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x443c0008, 0x5, 0x0, 0x0, 0x443c01b8
658 #define IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x443c0008, 0x6, 0x443c042c, 0x0, 0x443c01b8
659 #define IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x443c000c, 0x0, 0x0, 0x0, 0x443c01bc
660 #define IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x443c000c, 0x1, 0x0, 0x0, 0x443c01bc
661 #define IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x443c000c, 0x3, 0x443c0364, 0x0, 0x443c01bc
662 #define IOMUXC_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x443c000c, 0x4, 0x0, 0x0, 0x443c01bc
663 #define IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x443c000c, 0x5, 0x0, 0x0, 0x443c01bc
664 #define IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x443c000c, 0x6, 0x443c0434, 0x0, 0x443c01bc
665 #define IOMUXC_PAD_GPIO_IO00__GPIO2_IO00 0x443c0010, 0x0, 0x0, 0x0, 0x443c01c0
666 #define IOMUXC_PAD_GPIO_IO00__LPI2C3_SDA 0x443c0010, 0x1, 0x443c03e4, 0x0, 0x443c01c0
667 #define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x443c0010, 0x2, 0x0, 0x0, 0x443c01c0
668 #define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x443c0010, 0x3, 0x0, 0x0, 0x443c01c0
669 #define IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0 0x443c0010, 0x4, 0x0, 0x0, 0x443c01c0
670 #define IOMUXC_PAD_GPIO_IO00__LPUART5_TX 0x443c0010, 0x5, 0x443c0434, 0x1, 0x443c01c0
671 #define IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA 0x443c0010, 0x6, 0x443c03ec, 0x0, 0x443c01c0
672 #define IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x443c0010, 0x7, 0x443c036c, 0x0, 0x443c01c0
673 #define IOMUXC_PAD_GPIO_IO01__GPIO2_IO01 0x443c0014, 0x0, 0x0, 0x0, 0x443c01c4
674 #define IOMUXC_PAD_GPIO_IO01__LPI2C3_SCL 0x443c0014, 0x1, 0x443c03e0, 0x0, 0x443c01c4
675 #define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x443c0014, 0x2, 0x0, 0x0, 0x443c01c4
676 #define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x443c0014, 0x3, 0x0, 0x0, 0x443c01c4
677 #define IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN 0x443c0014, 0x4, 0x0, 0x0, 0x443c01c4
678 #define IOMUXC_PAD_GPIO_IO01__LPUART5_RX 0x443c0014, 0x5, 0x443c0430, 0x1, 0x443c01c4
679 #define IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL 0x443c0014, 0x6, 0x443c03e8, 0x0, 0x443c01c4
680 #define IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x443c0014, 0x7, 0x443c0370, 0x0, 0x443c01c4
681 #define IOMUXC_PAD_GPIO_IO02__GPIO2_IO02 0x443c0018, 0x0, 0x0, 0x0, 0x443c01c8
682 #define IOMUXC_PAD_GPIO_IO02__LPI2C4_SDA 0x443c0018, 0x1, 0x0, 0x0, 0x443c01c8
683 #define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x443c0018, 0x2, 0x0, 0x0, 0x443c01c8
684 #define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x443c0018, 0x3, 0x0, 0x0, 0x443c01c8
685 #define IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT 0x443c0018, 0x4, 0x0, 0x0, 0x443c01c8
686 #define IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B 0x443c0018, 0x5, 0x443c042c, 0x1, 0x443c01c8
687 #define IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA 0x443c0018, 0x6, 0x443c03f4, 0x0, 0x443c01c8
688 #define IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x443c0018, 0x7, 0x443c0374, 0x0, 0x443c01c8
689 #define IOMUXC_PAD_GPIO_IO03__GPIO2_IO03 0x443c001c, 0x0, 0x0, 0x0, 0x443c01cc
690 #define IOMUXC_PAD_GPIO_IO03__LPI2C4_SCL 0x443c001c, 0x1, 0x0, 0x0, 0x443c01cc
691 #define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x443c001c, 0x2, 0x0, 0x0, 0x443c01cc
692 #define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x443c001c, 0x3, 0x0, 0x0, 0x443c01cc
693 #define IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK 0x443c001c, 0x4, 0x0, 0x0, 0x443c01cc
694 #define IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B 0x443c001c, 0x5, 0x0, 0x0, 0x443c01cc
695 #define IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL 0x443c001c, 0x6, 0x443c03f0, 0x0, 0x443c01cc
696 #define IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x443c001c, 0x7, 0x443c0378, 0x0, 0x443c01cc
697 #define IOMUXC_PAD_GPIO_IO04__GPIO2_IO04 0x443c0020, 0x0, 0x0, 0x0, 0x443c01d0
698 #define IOMUXC_PAD_GPIO_IO04__TPM3_CH0 0x443c0020, 0x1, 0x0, 0x0, 0x443c01d0
699 #define IOMUXC_PAD_GPIO_IO04__PDM_CLK 0x443c0020, 0x2, 0x0, 0x0, 0x443c01d0
700 #define IOMUXC_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x443c0020, 0x3, 0x0, 0x0, 0x443c01d0
701 #define IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0 0x443c0020, 0x4, 0x0, 0x0, 0x443c01d0
702 #define IOMUXC_PAD_GPIO_IO04__LPUART6_TX 0x443c0020, 0x5, 0x0, 0x0, 0x443c01d0
703 #define IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA 0x443c0020, 0x6, 0x443c03f4, 0x1, 0x443c01d0
704 #define IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x443c0020, 0x7, 0x443c037c, 0x0, 0x443c01d0
705 #define IOMUXC_PAD_GPIO_IO05__GPIO2_IO05 0x443c0024, 0x0, 0x0, 0x0, 0x443c01d4
706 #define IOMUXC_PAD_GPIO_IO05__TPM4_CH0 0x443c0024, 0x1, 0x0, 0x0, 0x443c01d4
707 #define IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x443c0024, 0x2, 0x443c0438, 0x0, 0x443c01d4
708 #define IOMUXC_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x443c0024, 0x3, 0x0, 0x0, 0x443c01d4
709 #define IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN 0x443c0024, 0x4, 0x0, 0x0, 0x443c01d4
710 #define IOMUXC_PAD_GPIO_IO05__LPUART6_RX 0x443c0024, 0x5, 0x0, 0x0, 0x443c01d4
711 #define IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL 0x443c0024, 0x6, 0x443c03f0, 0x1, 0x443c01d4
712 #define IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x443c0024, 0x7, 0x443c0380, 0x0, 0x443c01d4
713 #define IOMUXC_PAD_GPIO_IO06__GPIO2_IO06 0x443c0028, 0x0, 0x0, 0x0, 0x443c01d8
714 #define IOMUXC_PAD_GPIO_IO06__TPM5_CH0 0x443c0028, 0x1, 0x0, 0x0, 0x443c01d8
715 #define IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x443c0028, 0x2, 0x443c043c, 0x0, 0x443c01d8
716 #define IOMUXC_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x443c0028, 0x3, 0x0, 0x0, 0x443c01d8
717 #define IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT 0x443c0028, 0x4, 0x0, 0x0, 0x443c01d8
718 #define IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B 0x443c0028, 0x5, 0x0, 0x0, 0x443c01d8
719 #define IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA 0x443c0028, 0x6, 0x443c03fc, 0x0, 0x443c01d8
720 #define IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x443c0028, 0x7, 0x443c0384, 0x0, 0x443c01d8
721 #define IOMUXC_PAD_GPIO_IO07__GPIO2_IO07 0x443c002c, 0x0, 0x0, 0x0, 0x443c01dc
722 #define IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1 0x443c002c, 0x1, 0x0, 0x0, 0x443c01dc
723 #define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x443c002c, 0x2, 0x0, 0x0, 0x443c01dc
724 #define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x443c002c, 0x3, 0x0, 0x0, 0x443c01dc
725 #define IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK 0x443c002c, 0x4, 0x0, 0x0, 0x443c01dc
726 #define IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B 0x443c002c, 0x5, 0x0, 0x0, 0x443c01dc
727 #define IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL 0x443c002c, 0x6, 0x443c03f8, 0x0, 0x443c01dc
728 #define IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x443c002c, 0x7, 0x443c0388, 0x0, 0x443c01dc
729 #define IOMUXC_PAD_GPIO_IO08__GPIO2_IO08 0x443c0030, 0x0, 0x0, 0x0, 0x443c01e0
730 #define IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0 0x443c0030, 0x1, 0x0, 0x0, 0x443c01e0
731 #define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x443c0030, 0x2, 0x0, 0x0, 0x443c01e0
732 #define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x443c0030, 0x3, 0x0, 0x0, 0x443c01e0
733 #define IOMUXC_PAD_GPIO_IO08__TPM6_CH0 0x443c0030, 0x4, 0x0, 0x0, 0x443c01e0
734 #define IOMUXC_PAD_GPIO_IO08__LPUART7_TX 0x443c0030, 0x5, 0x0, 0x0, 0x443c01e0
735 #define IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA 0x443c0030, 0x6, 0x443c03fc, 0x1, 0x443c01e0
736 #define IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x443c0030, 0x7, 0x443c038c, 0x0, 0x443c01e0
737 #define IOMUXC_PAD_GPIO_IO09__GPIO2_IO09 0x443c0034, 0x0, 0x0, 0x0, 0x443c01e4
738 #define IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN 0x443c0034, 0x1, 0x0, 0x0, 0x443c01e4
739 #define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x443c0034, 0x2, 0x0, 0x0, 0x443c01e4
740 #define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x443c0034, 0x3, 0x0, 0x0, 0x443c01e4
741 #define IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK 0x443c0034, 0x4, 0x0, 0x0, 0x443c01e4
742 #define IOMUXC_PAD_GPIO_IO09__LPUART7_RX 0x443c0034, 0x5, 0x0, 0x0, 0x443c01e4
743 #define IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL 0x443c0034, 0x6, 0x443c03f8, 0x1, 0x443c01e4
744 #define IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x443c0034, 0x7, 0x443c0390, 0x0, 0x443c01e4
745 #define IOMUXC_PAD_GPIO_IO10__GPIO2_IO10 0x443c0038, 0x0, 0x0, 0x0, 0x443c01e8
746 #define IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT 0x443c0038, 0x1, 0x0, 0x0, 0x443c01e8
747 #define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x443c0038, 0x2, 0x0, 0x0, 0x443c01e8
748 #define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x443c0038, 0x3, 0x0, 0x0, 0x443c01e8
749 #define IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK 0x443c0038, 0x4, 0x0, 0x0, 0x443c01e8
750 #define IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B 0x443c0038, 0x5, 0x0, 0x0, 0x443c01e8
751 #define IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA 0x443c0038, 0x6, 0x443c0404, 0x0, 0x443c01e8
752 #define IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x443c0038, 0x7, 0x443c0394, 0x0, 0x443c01e8
753 #define IOMUXC_PAD_GPIO_IO11__GPIO2_IO11 0x443c003c, 0x0, 0x0, 0x0, 0x443c01ec
754 #define IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK 0x443c003c, 0x1, 0x0, 0x0, 0x443c01ec
755 #define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x443c003c, 0x2, 0x0, 0x0, 0x443c01ec
756 #define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x443c003c, 0x3, 0x0, 0x0, 0x443c01ec
757 #define IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK 0x443c003c, 0x4, 0x0, 0x0, 0x443c01ec
758 #define IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B 0x443c003c, 0x5, 0x0, 0x0, 0x443c01ec
759 #define IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL 0x443c003c, 0x6, 0x443c0400, 0x0, 0x443c01ec
760 #define IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x443c003c, 0x7, 0x443c0398, 0x0, 0x443c01ec
761 #define IOMUXC_PAD_GPIO_IO12__GPIO2_IO12 0x443c0040, 0x0, 0x0, 0x0, 0x443c01f0
762 #define IOMUXC_PAD_GPIO_IO12__TPM3_CH2 0x443c0040, 0x1, 0x0, 0x0, 0x443c01f0
763 #define IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x443c0040, 0x2, 0x443c0440, 0x0, 0x443c01f0
764 #define IOMUXC_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x443c0040, 0x3, 0x0, 0x0, 0x443c01f0
765 #define IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0 0x443c0040, 0x4, 0x0, 0x0, 0x443c01f0
766 #define IOMUXC_PAD_GPIO_IO12__LPUART8_TX 0x443c0040, 0x5, 0x0, 0x0, 0x443c01f0
767 #define IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA 0x443c0040, 0x6, 0x443c0404, 0x1, 0x443c01f0
768 #define IOMUXC_PAD_GPIO_IO12__SAI3_RX_SYNC 0x443c0040, 0x7, 0x443c0450, 0x0, 0x443c01f0
769 #define IOMUXC_PAD_GPIO_IO13__GPIO2_IO13 0x443c0044, 0x0, 0x0, 0x0, 0x443c01f4
770 #define IOMUXC_PAD_GPIO_IO13__TPM4_CH2 0x443c0044, 0x1, 0x0, 0x0, 0x443c01f4
771 #define IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x443c0044, 0x2, 0x443c0444, 0x0, 0x443c01f4
772 #define IOMUXC_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x443c0044, 0x3, 0x0, 0x0, 0x443c01f4
773 #define IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN 0x443c0044, 0x4, 0x0, 0x0, 0x443c01f4
774 #define IOMUXC_PAD_GPIO_IO13__LPUART8_RX 0x443c0044, 0x5, 0x0, 0x0, 0x443c01f4
775 #define IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL 0x443c0044, 0x6, 0x443c0400, 0x1, 0x443c01f4
776 #define IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x443c0044, 0x7, 0x443c039c, 0x0, 0x443c01f4
777 #define IOMUXC_PAD_GPIO_IO14__GPIO2_IO14 0x443c0048, 0x0, 0x0, 0x0, 0x443c01f8
778 #define IOMUXC_PAD_GPIO_IO14__LPUART3_TX 0x443c0048, 0x1, 0x443c041c, 0x0, 0x443c01f8
779 #define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x443c0048, 0x2, 0x0, 0x0, 0x443c01f8
780 #define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x443c0048, 0x3, 0x0, 0x0, 0x443c01f8
781 #define IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT 0x443c0048, 0x4, 0x0, 0x0, 0x443c01f8
782 #define IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B 0x443c0048, 0x5, 0x0, 0x0, 0x443c01f8
783 #define IOMUXC_PAD_GPIO_IO14__LPUART4_TX 0x443c0048, 0x6, 0x443c0428, 0x0, 0x443c01f8
784 #define IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x443c0048, 0x7, 0x443c03a0, 0x0, 0x443c01f8
785 #define IOMUXC_PAD_GPIO_IO15__GPIO2_IO15 0x443c004c, 0x0, 0x0, 0x0, 0x443c01fc
786 #define IOMUXC_PAD_GPIO_IO15__LPUART3_RX 0x443c004c, 0x1, 0x443c0418, 0x0, 0x443c01fc
787 #define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x443c004c, 0x2, 0x0, 0x0, 0x443c01fc
788 #define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x443c004c, 0x3, 0x0, 0x0, 0x443c01fc
789 #define IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK 0x443c004c, 0x4, 0x0, 0x0, 0x443c01fc
790 #define IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B 0x443c004c, 0x5, 0x0, 0x0, 0x443c01fc
791 #define IOMUXC_PAD_GPIO_IO15__LPUART4_RX 0x443c004c, 0x6, 0x443c0424, 0x0, 0x443c01fc
792 #define IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x443c004c, 0x7, 0x443c03a4, 0x0, 0x443c01fc
793 #define IOMUXC_PAD_GPIO_IO16__GPIO2_IO16 0x443c0050, 0x0, 0x0, 0x0, 0x443c0200
794 #define IOMUXC_PAD_GPIO_IO16__SAI3_TX_BCLK 0x443c0050, 0x1, 0x0, 0x0, 0x443c0200
795 #define IOMUXC_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x443c0050, 0x2, 0x443c0440, 0x1, 0x443c0200
796 #define IOMUXC_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x443c0050, 0x3, 0x0, 0x0, 0x443c0200
797 #define IOMUXC_PAD_GPIO_IO16__LPUART3_CTS_B 0x443c0050, 0x4, 0x443c0414, 0x0, 0x443c0200
798 #define IOMUXC_PAD_GPIO_IO16__LPSPI4_PCS2 0x443c0050, 0x5, 0x0, 0x0, 0x443c0200
799 #define IOMUXC_PAD_GPIO_IO16__LPUART4_CTS_B 0x443c0050, 0x6, 0x443c0420, 0x0, 0x443c0200
800 #define IOMUXC_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x443c0050, 0x7, 0x443c03a8, 0x0, 0x443c0200
801 #define IOMUXC_PAD_GPIO_IO17__GPIO2_IO17 0x443c0054, 0x0, 0x0, 0x0, 0x443c0204
802 #define IOMUXC_PAD_GPIO_IO17__SAI3_MCLK 0x443c0054, 0x1, 0x0, 0x0, 0x443c0204
803 #define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x443c0054, 0x2, 0x0, 0x0, 0x443c0204
804 #define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x443c0054, 0x3, 0x0, 0x0, 0x443c0204
805 #define IOMUXC_PAD_GPIO_IO17__LPUART3_RTS_B 0x443c0054, 0x4, 0x0, 0x0, 0x443c0204
806 #define IOMUXC_PAD_GPIO_IO17__LPSPI4_PCS1 0x443c0054, 0x5, 0x0, 0x0, 0x443c0204
807 #define IOMUXC_PAD_GPIO_IO17__LPUART4_RTS_B 0x443c0054, 0x6, 0x0, 0x0, 0x443c0204
808 #define IOMUXC_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x443c0054, 0x7, 0x443c03ac, 0x0, 0x443c0204
809 #define IOMUXC_PAD_GPIO_IO18__GPIO2_IO18 0x443c0058, 0x0, 0x0, 0x0, 0x443c0208
810 #define IOMUXC_PAD_GPIO_IO18__SAI3_RX_BCLK 0x443c0058, 0x1, 0x443c044c, 0x0, 0x443c0208
811 #define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x443c0058, 0x2, 0x0, 0x0, 0x443c0208
812 #define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x443c0058, 0x3, 0x0, 0x0, 0x443c0208
813 #define IOMUXC_PAD_GPIO_IO18__LPSPI5_PCS0 0x443c0058, 0x4, 0x0, 0x0, 0x443c0208
814 #define IOMUXC_PAD_GPIO_IO18__LPSPI4_PCS0 0x443c0058, 0x5, 0x0, 0x0, 0x443c0208
815 #define IOMUXC_PAD_GPIO_IO18__TPM5_CH2 0x443c0058, 0x6, 0x0, 0x0, 0x443c0208
816 #define IOMUXC_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x443c0058, 0x7, 0x443c03b0, 0x0, 0x443c0208
817 #define IOMUXC_PAD_GPIO_IO19__GPIO2_IO19 0x443c005c, 0x0, 0x0, 0x0, 0x443c020c
818 #define IOMUXC_PAD_GPIO_IO19__SAI3_RX_SYNC 0x443c005c, 0x1, 0x443c0450, 0x1, 0x443c020c
819 #define IOMUXC_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x443c005c, 0x2, 0x443c0444, 0x1, 0x443c020c
820 #define IOMUXC_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x443c005c, 0x3, 0x0, 0x0, 0x443c020c
821 #define IOMUXC_PAD_GPIO_IO19__LPSPI5_SIN 0x443c005c, 0x4, 0x0, 0x0, 0x443c020c
822 #define IOMUXC_PAD_GPIO_IO19__LPSPI4_SIN 0x443c005c, 0x5, 0x0, 0x0, 0x443c020c
823 #define IOMUXC_PAD_GPIO_IO19__TPM6_CH2 0x443c005c, 0x6, 0x0, 0x0, 0x443c020c
824 #define IOMUXC_PAD_GPIO_IO19__SAI3_TX_DATA00 0x443c005c, 0x7, 0x0, 0x0, 0x443c020c
825 #define IOMUXC_PAD_GPIO_IO20__GPIO2_IO20 0x443c0060, 0x0, 0x0, 0x0, 0x443c0210
826 #define IOMUXC_PAD_GPIO_IO20__SAI3_RX_DATA00 0x443c0060, 0x1, 0x0, 0x0, 0x443c0210
827 #define IOMUXC_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x443c0060, 0x2, 0x443c0438, 0x1, 0x443c0210
828 #define IOMUXC_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x443c0060, 0x3, 0x0, 0x0, 0x443c0210
829 #define IOMUXC_PAD_GPIO_IO20__LPSPI5_SOUT 0x443c0060, 0x4, 0x0, 0x0, 0x443c0210
830 #define IOMUXC_PAD_GPIO_IO20__LPSPI4_SOUT 0x443c0060, 0x5, 0x0, 0x0, 0x443c0210
831 #define IOMUXC_PAD_GPIO_IO20__TPM3_CH1 0x443c0060, 0x6, 0x0, 0x0, 0x443c0210
832 #define IOMUXC_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x443c0060, 0x7, 0x443c03b4, 0x0, 0x443c0210
833 #define IOMUXC_PAD_GPIO_IO21__GPIO2_IO21 0x443c0064, 0x0, 0x0, 0x0, 0x443c0214
834 #define IOMUXC_PAD_GPIO_IO21__SAI3_TX_DATA00 0x443c0064, 0x1, 0x0, 0x0, 0x443c0214
835 #define IOMUXC_PAD_GPIO_IO21__PDM_CLK 0x443c0064, 0x2, 0x0, 0x0, 0x443c0214
836 #define IOMUXC_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x443c0064, 0x3, 0x0, 0x0, 0x443c0214
837 #define IOMUXC_PAD_GPIO_IO21__LPSPI5_SCK 0x443c0064, 0x4, 0x0, 0x0, 0x443c0214
838 #define IOMUXC_PAD_GPIO_IO21__LPSPI4_SCK 0x443c0064, 0x5, 0x0, 0x0, 0x443c0214
839 #define IOMUXC_PAD_GPIO_IO21__TPM4_CH1 0x443c0064, 0x6, 0x0, 0x0, 0x443c0214
840 #define IOMUXC_PAD_GPIO_IO21__SAI3_RX_BCLK 0x443c0064, 0x7, 0x443c044c, 0x1, 0x443c0214
841 #define IOMUXC_PAD_GPIO_IO22__GPIO2_IO22 0x443c0068, 0x0, 0x0, 0x0, 0x443c0218
842 #define IOMUXC_PAD_GPIO_IO22__USDHC3_CLK 0x443c0068, 0x1, 0x443c0458, 0x0, 0x443c0218
843 #define IOMUXC_PAD_GPIO_IO22__SPDIF_IN 0x443c0068, 0x2, 0x443c0454, 0x0, 0x443c0218
844 #define IOMUXC_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x443c0068, 0x3, 0x0, 0x0, 0x443c0218
845 #define IOMUXC_PAD_GPIO_IO22__TPM5_CH1 0x443c0068, 0x4, 0x0, 0x0, 0x443c0218
846 #define IOMUXC_PAD_GPIO_IO22__TPM6_EXTCLK 0x443c0068, 0x5, 0x0, 0x0, 0x443c0218
847 #define IOMUXC_PAD_GPIO_IO22__LPI2C5_SDA 0x443c0068, 0x6, 0x443c03ec, 0x1, 0x443c0218
848 #define IOMUXC_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x443c0068, 0x7, 0x443c03b8, 0x0, 0x443c0218
849 #define IOMUXC_PAD_GPIO_IO23__GPIO2_IO23 0x443c006c, 0x0, 0x0, 0x0, 0x443c021c
850 #define IOMUXC_PAD_GPIO_IO23__USDHC3_CMD 0x443c006c, 0x1, 0x443c045c, 0x0, 0x443c021c
851 #define IOMUXC_PAD_GPIO_IO23__SPDIF_OUT 0x443c006c, 0x2, 0x0, 0x0, 0x443c021c
852 #define IOMUXC_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x443c006c, 0x3, 0x0, 0x0, 0x443c021c
853 #define IOMUXC_PAD_GPIO_IO23__TPM6_CH1 0x443c006c, 0x4, 0x0, 0x0, 0x443c021c
854 #define IOMUXC_PAD_GPIO_IO23__LPI2C5_SCL 0x443c006c, 0x6, 0x443c03e8, 0x1, 0x443c021c
855 #define IOMUXC_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x443c006c, 0x7, 0x443c03bc, 0x0, 0x443c021c
856 #define IOMUXC_PAD_GPIO_IO24__GPIO2_IO24 0x443c0070, 0x0, 0x0, 0x0, 0x443c0220
857 #define IOMUXC_PAD_GPIO_IO24__USDHC3_DATA0 0x443c0070, 0x1, 0x443c0460, 0x0, 0x443c0220
858 #define IOMUXC_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x443c0070, 0x3, 0x0, 0x0, 0x443c0220
859 #define IOMUXC_PAD_GPIO_IO24__TPM3_CH3 0x443c0070, 0x4, 0x0, 0x0, 0x443c0220
860 #define IOMUXC_PAD_GPIO_IO24__JTAG_MUX_TDO 0x443c0070, 0x5, 0x0, 0x0, 0x443c0220
861 #define IOMUXC_PAD_GPIO_IO24__LPSPI6_PCS1 0x443c0070, 0x6, 0x0, 0x0, 0x443c0220
862 #define IOMUXC_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x443c0070, 0x7, 0x443c03c0, 0x0, 0x443c0220
863 #define IOMUXC_PAD_GPIO_IO25__GPIO2_IO25 0x443c0074, 0x0, 0x0, 0x0, 0x443c0224
864 #define IOMUXC_PAD_GPIO_IO25__USDHC3_DATA1 0x443c0074, 0x1, 0x443c0464, 0x0, 0x443c0224
865 #define IOMUXC_PAD_GPIO_IO25__CAN2_TX 0x443c0074, 0x2, 0x0, 0x0, 0x443c0224
866 #define IOMUXC_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x443c0074, 0x3, 0x0, 0x0, 0x443c0224
867 #define IOMUXC_PAD_GPIO_IO25__TPM4_CH3 0x443c0074, 0x4, 0x0, 0x0, 0x443c0224
868 #define IOMUXC_PAD_GPIO_IO25__JTAG_MUX_TCK 0x443c0074, 0x5, 0x443c03d4, 0x1, 0x443c0224
869 #define IOMUXC_PAD_GPIO_IO25__LPSPI7_PCS1 0x443c0074, 0x6, 0x0, 0x0, 0x443c0224
870 #define IOMUXC_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x443c0074, 0x7, 0x443c03c4, 0x0, 0x443c0224
871 #define IOMUXC_PAD_GPIO_IO26__GPIO2_IO26 0x443c0078, 0x0, 0x0, 0x0, 0x443c0228
872 #define IOMUXC_PAD_GPIO_IO26__USDHC3_DATA2 0x443c0078, 0x1, 0x443c0468, 0x0, 0x443c0228
873 #define IOMUXC_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x443c0078, 0x2, 0x443c043c, 0x1, 0x443c0228
874 #define IOMUXC_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x443c0078, 0x3, 0x0, 0x0, 0x443c0228
875 #define IOMUXC_PAD_GPIO_IO26__TPM5_CH3 0x443c0078, 0x4, 0x0, 0x0, 0x443c0228
876 #define IOMUXC_PAD_GPIO_IO26__JTAG_MUX_TDI 0x443c0078, 0x5, 0x443c03d8, 0x1, 0x443c0228
877 #define IOMUXC_PAD_GPIO_IO26__LPSPI8_PCS1 0x443c0078, 0x6, 0x0, 0x0, 0x443c0228
878 #define IOMUXC_PAD_GPIO_IO26__SAI3_TX_SYNC 0x443c0078, 0x7, 0x0, 0x0, 0x443c0228
879 #define IOMUXC_PAD_GPIO_IO27__GPIO2_IO27 0x443c007c, 0x0, 0x0, 0x0, 0x443c022c
880 #define IOMUXC_PAD_GPIO_IO27__USDHC3_DATA3 0x443c007c, 0x1, 0x443c046c, 0x0, 0x443c022c
881 #define IOMUXC_PAD_GPIO_IO27__CAN2_RX 0x443c007c, 0x2, 0x443c0364, 0x1, 0x443c022c
882 #define IOMUXC_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x443c007c, 0x3, 0x0, 0x0, 0x443c022c
883 #define IOMUXC_PAD_GPIO_IO27__TPM6_CH3 0x443c007c, 0x4, 0x0, 0x0, 0x443c022c
884 #define IOMUXC_PAD_GPIO_IO27__JTAG_MUX_TMS 0x443c007c, 0x5, 0x443c03dc, 0x1, 0x443c022c
885 #define IOMUXC_PAD_GPIO_IO27__LPSPI5_PCS1 0x443c007c, 0x6, 0x0, 0x0, 0x443c022c
886 #define IOMUXC_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x443c007c, 0x7, 0x443c03c8, 0x0, 0x443c022c
887 #define IOMUXC_PAD_GPIO_IO28__GPIO2_IO28 0x443c0080, 0x0, 0x0, 0x0, 0x443c0230
888 #define IOMUXC_PAD_GPIO_IO28__LPI2C3_SDA 0x443c0080, 0x1, 0x443c03e4, 0x1, 0x443c0230
889 #define IOMUXC_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x443c0080, 0x7, 0x0, 0x0, 0x443c0230
890 #define IOMUXC_PAD_GPIO_IO29__GPIO2_IO29 0x443c0084, 0x0, 0x0, 0x0, 0x443c0234
891 #define IOMUXC_PAD_GPIO_IO29__LPI2C3_SCL 0x443c0084, 0x1, 0x443c03e0, 0x1, 0x443c0234
892 #define IOMUXC_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x443c0084, 0x7, 0x0, 0x0, 0x443c0234
893 #define IOMUXC_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x443c0088, 0x0, 0x0, 0x0, 0x443c0238
894 #define IOMUXC_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x443c0088, 0x4, 0x0, 0x0, 0x443c0238
895 #define IOMUXC_PAD_CCM_CLKO1__GPIO3_IO26 0x443c0088, 0x5, 0x0, 0x0, 0x443c0238
896 #define IOMUXC_PAD_CCM_CLKO2__GPIO3_IO27 0x443c008c, 0x5, 0x0, 0x0, 0x443c023c
897 #define IOMUXC_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x443c008c, 0x0, 0x0, 0x0, 0x443c023c
898 #define IOMUXC_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x443c008c, 0x4, 0x443c03c8, 0x1, 0x443c023c
899 #define IOMUXC_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x443c0090, 0x0, 0x0, 0x0, 0x443c0240
900 #define IOMUXC_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x443c0090, 0x4, 0x0, 0x0, 0x443c0240
901 #define IOMUXC_PAD_CCM_CLKO3__GPIO4_IO28 0x443c0090, 0x5, 0x0, 0x0, 0x443c0240
902 #define IOMUXC_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x443c0094, 0x0, 0x0, 0x0, 0x443c0244
903 #define IOMUXC_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x443c0094, 0x4, 0x0, 0x0, 0x443c0244
904 #define IOMUXC_PAD_CCM_CLKO4__GPIO4_IO29 0x443c0094, 0x5, 0x0, 0x0, 0x443c0244
905 #define IOMUXC_PAD_ENET1_MDC__ENET_QOS_MDC 0x443c0098, 0x0, 0x0, 0x0, 0x443c0248
906 #define IOMUXC_PAD_ENET1_MDC__LPUART3_DCB_B 0x443c0098, 0x1, 0x0, 0x0, 0x443c0248
907 #define IOMUXC_PAD_ENET1_MDC__I3C2_SCL 0x443c0098, 0x2, 0x443c03cc, 0x0, 0x443c0248
908 #define IOMUXC_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x443c0098, 0x3, 0x0, 0x0, 0x443c0248
909 #define IOMUXC_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x443c0098, 0x4, 0x0, 0x0, 0x443c0248
910 #define IOMUXC_PAD_ENET1_MDC__GPIO4_IO00 0x443c0098, 0x5, 0x0, 0x0, 0x443c0248
911 #define IOMUXC_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x443c009c, 0x0, 0x0, 0x0, 0x443c024c
912 #define IOMUXC_PAD_ENET1_MDIO__LPUART3_RIN_B 0x443c009c, 0x1, 0x0, 0x0, 0x443c024c
913 #define IOMUXC_PAD_ENET1_MDIO__I3C2_SDA 0x443c009c, 0x2, 0x443c03d0, 0x0, 0x443c024c
914 #define IOMUXC_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x443c009c, 0x3, 0x0, 0x0, 0x443c024c
915 #define IOMUXC_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x443c009c, 0x4, 0x0, 0x0, 0x443c024c
916 #define IOMUXC_PAD_ENET1_MDIO__GPIO4_IO01 0x443c009c, 0x5, 0x0, 0x0, 0x443c024c
917 #define IOMUXC_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x443c00a0, 0x0, 0x0, 0x0, 0x443c0250
918 #define IOMUXC_PAD_ENET1_TD3__CAN2_TX 0x443c00a0, 0x2, 0x0, 0x0, 0x443c0250
919 #define IOMUXC_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x443c00a0, 0x3, 0x0, 0x0, 0x443c0250
920 #define IOMUXC_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x443c00a0, 0x4, 0x0, 0x0, 0x443c0250
921 #define IOMUXC_PAD_ENET1_TD3__GPIO4_IO02 0x443c00a0, 0x5, 0x0, 0x0, 0x443c0250
922 #define IOMUXC_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x443c00a4, 0x0, 0x0, 0x0, 0x443c0254
923 #define IOMUXC_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x443c00a4, 0x1, 0x0, 0x0, 0x443c0254
924 #define IOMUXC_PAD_ENET1_TD2__CAN2_RX 0x443c00a4, 0x2, 0x443c0364, 0x2, 0x443c0254
925 #define IOMUXC_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x443c00a4, 0x3, 0x0, 0x0, 0x443c0254
926 #define IOMUXC_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x443c00a4, 0x4, 0x0, 0x0, 0x443c0254
927 #define IOMUXC_PAD_ENET1_TD2__GPIO4_IO03 0x443c00a4, 0x5, 0x0, 0x0, 0x443c0254
928 #define IOMUXC_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x443c00a8, 0x0, 0x0, 0x0, 0x443c0258
929 #define IOMUXC_PAD_ENET1_TD1__LPUART3_RTS_B 0x443c00a8, 0x1, 0x0, 0x0, 0x443c0258
930 #define IOMUXC_PAD_ENET1_TD1__I3C2_PUR 0x443c00a8, 0x2, 0x0, 0x0, 0x443c0258
931 #define IOMUXC_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x443c00a8, 0x3, 0x0, 0x0, 0x443c0258
932 #define IOMUXC_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x443c00a8, 0x4, 0x0, 0x0, 0x443c0258
933 #define IOMUXC_PAD_ENET1_TD1__GPIO4_IO04 0x443c00a8, 0x5, 0x0, 0x0, 0x443c0258
934 #define IOMUXC_PAD_ENET1_TD1__I3C2_PUR_B 0x443c00a8, 0x6, 0x0, 0x0, 0x443c0258
935 #define IOMUXC_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x443c00ac, 0x0, 0x0, 0x0, 0x443c025c
936 #define IOMUXC_PAD_ENET1_TD0__LPUART3_TX 0x443c00ac, 0x1, 0x443c041c, 0x1, 0x443c025c
937 #define IOMUXC_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x443c00ac, 0x4, 0x0, 0x0, 0x443c025c
938 #define IOMUXC_PAD_ENET1_TD0__GPIO4_IO05 0x443c00ac, 0x5, 0x0, 0x0, 0x443c025c
939 #define IOMUXC_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x443c00b0, 0x0, 0x0, 0x0, 0x443c0260
940 #define IOMUXC_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x443c00b0, 0x1, 0x0, 0x0, 0x443c0260
941 #define IOMUXC_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x443c00b0, 0x4, 0x0, 0x0, 0x443c0260
942 #define IOMUXC_PAD_ENET1_TX_CTL__GPIO4_IO06 0x443c00b0, 0x5, 0x0, 0x0, 0x443c0260
943 #define IOMUXC_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x443c00b4, 0x0, 0x0, 0x0, 0x443c0264
944 #define IOMUXC_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x443c00b4, 0x1, 0x0, 0x0, 0x443c0264
945 #define IOMUXC_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x443c00b4, 0x4, 0x0, 0x0, 0x443c0264
946 #define IOMUXC_PAD_ENET1_TXC__GPIO4_IO07 0x443c00b4, 0x5, 0x0, 0x0, 0x443c0264
947 #define IOMUXC_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x443c00b8, 0x0, 0x0, 0x0, 0x443c0268
948 #define IOMUXC_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x443c00b8, 0x1, 0x0, 0x0, 0x443c0268
949 #define IOMUXC_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x443c00b8, 0x3, 0x0, 0x0, 0x443c0268
950 #define IOMUXC_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x443c00b8, 0x4, 0x0, 0x0, 0x443c0268
951 #define IOMUXC_PAD_ENET1_RX_CTL__GPIO4_IO08 0x443c00b8, 0x5, 0x0, 0x0, 0x443c0268
952 #define IOMUXC_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x443c00bc, 0x0, 0x0, 0x0, 0x443c026c
953 #define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x443c00bc, 0x1, 0x0, 0x0, 0x443c026c
954 #define IOMUXC_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x443c00bc, 0x4, 0x0, 0x0, 0x443c026c
955 #define IOMUXC_PAD_ENET1_RXC__GPIO4_IO09 0x443c00bc, 0x5, 0x0, 0x0, 0x443c026c
956 #define IOMUXC_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x443c00c0, 0x0, 0x0, 0x0, 0x443c0270
957 #define IOMUXC_PAD_ENET1_RD0__LPUART3_RX 0x443c00c0, 0x1, 0x443c0418, 0x1, 0x443c0270
958 #define IOMUXC_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x443c00c0, 0x4, 0x0, 0x0, 0x443c0270
959 #define IOMUXC_PAD_ENET1_RD0__GPIO4_IO10 0x443c00c0, 0x5, 0x0, 0x0, 0x443c0270
960 #define IOMUXC_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x443c00c4, 0x0, 0x0, 0x0, 0x443c0274
961 #define IOMUXC_PAD_ENET1_RD1__LPUART3_CTS_B 0x443c00c4, 0x1, 0x443c0414, 0x1, 0x443c0274
962 #define IOMUXC_PAD_ENET1_RD1__LPTMR2_ALT1 0x443c00c4, 0x3, 0x443c0408, 0x0, 0x443c0274
963 #define IOMUXC_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x443c00c4, 0x4, 0x0, 0x0, 0x443c0274
964 #define IOMUXC_PAD_ENET1_RD1__GPIO4_IO11 0x443c00c4, 0x5, 0x0, 0x0, 0x443c0274
965 #define IOMUXC_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x443c00c8, 0x0, 0x0, 0x0, 0x443c0278
966 #define IOMUXC_PAD_ENET1_RD2__LPTMR2_ALT2 0x443c00c8, 0x3, 0x443c040c, 0x0, 0x443c0278
967 #define IOMUXC_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x443c00c8, 0x4, 0x0, 0x0, 0x443c0278
968 #define IOMUXC_PAD_ENET1_RD2__GPIO4_IO12 0x443c00c8, 0x5, 0x0, 0x0, 0x443c0278
969 #define IOMUXC_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x443c00cc, 0x0, 0x0, 0x0, 0x443c027c
970 #define IOMUXC_PAD_ENET1_RD3__LPTMR2_ALT3 0x443c00cc, 0x3, 0x443c0410, 0x0, 0x443c027c
971 #define IOMUXC_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x443c00cc, 0x4, 0x0, 0x0, 0x443c027c
972 #define IOMUXC_PAD_ENET1_RD3__GPIO4_IO13 0x443c00cc, 0x5, 0x0, 0x0, 0x443c027c
973 #define IOMUXC_PAD_ENET2_MDC__ENET1_MDC 0x443c00d0, 0x0, 0x0, 0x0, 0x443c0280
974 #define IOMUXC_PAD_ENET2_MDC__LPUART4_DCB_B 0x443c00d0, 0x1, 0x0, 0x0, 0x443c0280
975 #define IOMUXC_PAD_ENET2_MDC__SAI2_RX_SYNC 0x443c00d0, 0x2, 0x0, 0x0, 0x443c0280
976 #define IOMUXC_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x443c00d0, 0x4, 0x0, 0x0, 0x443c0280
977 #define IOMUXC_PAD_ENET2_MDC__GPIO4_IO14 0x443c00d0, 0x5, 0x0, 0x0, 0x443c0280
978 #define IOMUXC_PAD_ENET2_MDIO__ENET1_MDIO 0x443c00d4, 0x0, 0x0, 0x0, 0x443c0284
979 #define IOMUXC_PAD_ENET2_MDIO__LPUART4_RIN_B 0x443c00d4, 0x1, 0x0, 0x0, 0x443c0284
980 #define IOMUXC_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x443c00d4, 0x2, 0x0, 0x0, 0x443c0284
981 #define IOMUXC_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x443c00d4, 0x4, 0x0, 0x0, 0x443c0284
982 #define IOMUXC_PAD_ENET2_MDIO__GPIO4_IO15 0x443c00d4, 0x5, 0x0, 0x0, 0x443c0284
983 #define IOMUXC_PAD_ENET2_TD3__SAI2_RX_DATA00 0x443c00d8, 0x2, 0x0, 0x0, 0x443c0288
984 #define IOMUXC_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x443c00d8, 0x4, 0x0, 0x0, 0x443c0288
985 #define IOMUXC_PAD_ENET2_TD3__GPIO4_IO16 0x443c00d8, 0x5, 0x0, 0x0, 0x443c0288
986 #define IOMUXC_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x443c00d8, 0x0, 0x0, 0x0, 0x443c0288
987 #define IOMUXC_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x443c00dc, 0x0, 0x0, 0x0, 0x443c028c
988 #define IOMUXC_PAD_ENET2_TD2__ENET1_TX_CLK 0x443c00dc, 0x1, 0x0, 0x0, 0x443c028c
989 #define IOMUXC_PAD_ENET2_TD2__SAI2_RX_DATA01 0x443c00dc, 0x2, 0x0, 0x0, 0x443c028c
990 #define IOMUXC_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x443c00dc, 0x4, 0x0, 0x0, 0x443c028c
991 #define IOMUXC_PAD_ENET2_TD2__GPIO4_IO17 0x443c00dc, 0x5, 0x0, 0x0, 0x443c028c
992 #define IOMUXC_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x443c00e0, 0x0, 0x0, 0x0, 0x443c0290
993 #define IOMUXC_PAD_ENET2_TD1__LPUART4_RTS_B 0x443c00e0, 0x1, 0x0, 0x0, 0x443c0290
994 #define IOMUXC_PAD_ENET2_TD1__SAI2_RX_DATA02 0x443c00e0, 0x2, 0x0, 0x0, 0x443c0290
995 #define IOMUXC_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x443c00e0, 0x4, 0x0, 0x0, 0x443c0290
996 #define IOMUXC_PAD_ENET2_TD1__GPIO4_IO18 0x443c00e0, 0x5, 0x0, 0x0, 0x443c0290
997 #define IOMUXC_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x443c00e4, 0x0, 0x0, 0x0, 0x443c0294
998 #define IOMUXC_PAD_ENET2_TD0__LPUART4_TX 0x443c00e4, 0x1, 0x443c0428, 0x1, 0x443c0294
999 #define IOMUXC_PAD_ENET2_TD0__SAI2_RX_DATA03 0x443c00e4, 0x2, 0x0, 0x0, 0x443c0294
1000 #define IOMUXC_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x443c00e4, 0x4, 0x0, 0x0, 0x443c0294
1001 #define IOMUXC_PAD_ENET2_TD0__GPIO4_IO19 0x443c00e4, 0x5, 0x0, 0x0, 0x443c0294
1002 #define IOMUXC_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x443c00e8, 0x0, 0x0, 0x0, 0x443c0298
1003 #define IOMUXC_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x443c00e8, 0x1, 0x0, 0x0, 0x443c0298
1004 #define IOMUXC_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x443c00e8, 0x2, 0x0, 0x0, 0x443c0298
1005 #define IOMUXC_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x443c00e8, 0x4, 0x0, 0x0, 0x443c0298
1006 #define IOMUXC_PAD_ENET2_TX_CTL__GPIO4_IO20 0x443c00e8, 0x5, 0x0, 0x0, 0x443c0298
1007 #define IOMUXC_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x443c00ec, 0x0, 0x0, 0x0, 0x443c029c
1008 #define IOMUXC_PAD_ENET2_TXC__ENET1_TX_ER 0x443c00ec, 0x1, 0x0, 0x0, 0x443c029c
1009 #define IOMUXC_PAD_ENET2_TXC__SAI2_TX_BCLK 0x443c00ec, 0x2, 0x0, 0x0, 0x443c029c
1010 #define IOMUXC_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x443c00ec, 0x4, 0x0, 0x0, 0x443c029c
1011 #define IOMUXC_PAD_ENET2_TXC__GPIO4_IO21 0x443c00ec, 0x5, 0x0, 0x0, 0x443c029c
1012 #define IOMUXC_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x443c00f0, 0x0, 0x0, 0x0, 0x443c02a0
1013 #define IOMUXC_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x443c00f0, 0x1, 0x0, 0x0, 0x443c02a0
1014 #define IOMUXC_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x443c00f0, 0x2, 0x0, 0x0, 0x443c02a0
1015 #define IOMUXC_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x443c00f0, 0x4, 0x0, 0x0, 0x443c02a0
1016 #define IOMUXC_PAD_ENET2_RX_CTL__GPIO4_IO22 0x443c00f0, 0x5, 0x0, 0x0, 0x443c02a0
1017 #define IOMUXC_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x443c00f4, 0x0, 0x0, 0x0, 0x443c02a4
1018 #define IOMUXC_PAD_ENET2_RXC__ENET1_RX_ER 0x443c00f4, 0x1, 0x0, 0x0, 0x443c02a4
1019 #define IOMUXC_PAD_ENET2_RXC__SAI2_TX_DATA01 0x443c00f4, 0x2, 0x0, 0x0, 0x443c02a4
1020 #define IOMUXC_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x443c00f4, 0x4, 0x0, 0x0, 0x443c02a4
1021 #define IOMUXC_PAD_ENET2_RXC__GPIO4_IO23 0x443c00f4, 0x5, 0x0, 0x0, 0x443c02a4
1022 #define IOMUXC_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x443c00f8, 0x0, 0x0, 0x0, 0x443c02a8
1023 #define IOMUXC_PAD_ENET2_RD0__LPUART4_RX 0x443c00f8, 0x1, 0x443c0424, 0x1, 0x443c02a8
1024 #define IOMUXC_PAD_ENET2_RD0__SAI2_TX_DATA02 0x443c00f8, 0x2, 0x0, 0x0, 0x443c02a8
1025 #define IOMUXC_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x443c00f8, 0x4, 0x0, 0x0, 0x443c02a8
1026 #define IOMUXC_PAD_ENET2_RD0__GPIO4_IO24 0x443c00f8, 0x5, 0x0, 0x0, 0x443c02a8
1027 #define IOMUXC_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x443c00fc, 0x0, 0x0, 0x0, 0x443c02ac
1028 #define IOMUXC_PAD_ENET2_RD1__SPDIF_IN 0x443c00fc, 0x1, 0x443c0454, 0x1, 0x443c02ac
1029 #define IOMUXC_PAD_ENET2_RD1__SAI2_TX_DATA03 0x443c00fc, 0x2, 0x0, 0x0, 0x443c02ac
1030 #define IOMUXC_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x443c00fc, 0x4, 0x0, 0x0, 0x443c02ac
1031 #define IOMUXC_PAD_ENET2_RD1__GPIO4_IO25 0x443c00fc, 0x5, 0x0, 0x0, 0x443c02ac
1032 #define IOMUXC_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x443c0100, 0x0, 0x0, 0x0, 0x443c02b0
1033 #define IOMUXC_PAD_ENET2_RD2__LPUART4_CTS_B 0x443c0100, 0x1, 0x443c0420, 0x1, 0x443c02b0
1034 #define IOMUXC_PAD_ENET2_RD2__SAI2_MCLK 0x443c0100, 0x2, 0x0, 0x0, 0x443c02b0
1035 #define IOMUXC_PAD_ENET2_RD2__MQS2_RIGHT 0x443c0100, 0x3, 0x0, 0x0, 0x443c02b0
1036 #define IOMUXC_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x443c0100, 0x4, 0x0, 0x0, 0x443c02b0
1037 #define IOMUXC_PAD_ENET2_RD2__GPIO4_IO26 0x443c0100, 0x5, 0x0, 0x0, 0x443c02b0
1038 #define IOMUXC_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x443c0104, 0x0, 0x0, 0x0, 0x443c02b4
1039 #define IOMUXC_PAD_ENET2_RD3__SPDIF_OUT 0x443c0104, 0x1, 0x0, 0x0, 0x443c02b4
1040 #define IOMUXC_PAD_ENET2_RD3__SPDIF_IN 0x443c0104, 0x2, 0x443c0454, 0x2, 0x443c02b4
1041 #define IOMUXC_PAD_ENET2_RD3__MQS2_LEFT 0x443c0104, 0x3, 0x0, 0x0, 0x443c02b4
1042 #define IOMUXC_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x443c0104, 0x4, 0x0, 0x0, 0x443c02b4
1043 #define IOMUXC_PAD_ENET2_RD3__GPIO4_IO27 0x443c0104, 0x5, 0x0, 0x0, 0x443c02b4
1044 #define IOMUXC_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x443c0108, 0x4, 0x443c038c, 0x1, 0x443c02b8
1045 #define IOMUXC_PAD_SD1_CLK__GPIO3_IO08 0x443c0108, 0x5, 0x0, 0x0, 0x443c02b8
1046 #define IOMUXC_PAD_SD1_CLK__USDHC1_CLK 0x443c0108, 0x0, 0x0, 0x0, 0x443c02b8
1047 #define IOMUXC_PAD_SD1_CMD__USDHC1_CMD 0x443c010c, 0x0, 0x0, 0x0, 0x443c02bc
1048 #define IOMUXC_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x443c010c, 0x4, 0x443c0390, 0x1, 0x443c02bc
1049 #define IOMUXC_PAD_SD1_CMD__GPIO3_IO09 0x443c010c, 0x5, 0x0, 0x0, 0x443c02bc
1050 #define IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0 0x443c0110, 0x0, 0x0, 0x0, 0x443c02c0
1051 #define IOMUXC_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x443c0110, 0x4, 0x443c0394, 0x1, 0x443c02c0
1052 #define IOMUXC_PAD_SD1_DATA0__GPIO3_IO10 0x443c0110, 0x5, 0x0, 0x0, 0x443c02c0
1053 #define IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1 0x443c0114, 0x0, 0x0, 0x0, 0x443c02c4
1054 #define IOMUXC_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x443c0114, 0x4, 0x443c0398, 0x1, 0x443c02c4
1055 #define IOMUXC_PAD_SD1_DATA1__GPIO3_IO11 0x443c0114, 0x5, 0x0, 0x0, 0x443c02c4
1056 #define IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2 0x443c0118, 0x0, 0x0, 0x0, 0x443c02c8
1057 #define IOMUXC_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x443c0118, 0x4, 0x0, 0x0, 0x443c02c8
1058 #define IOMUXC_PAD_SD1_DATA2__GPIO3_IO12 0x443c0118, 0x5, 0x0, 0x0, 0x443c02c8
1059 #define IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3 0x443c011c, 0x0, 0x0, 0x0, 0x443c02cc
1060 #define IOMUXC_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x443c011c, 0x1, 0x0, 0x0, 0x443c02cc
1061 #define IOMUXC_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x443c011c, 0x4, 0x443c039c, 0x1, 0x443c02cc
1062 #define IOMUXC_PAD_SD1_DATA3__GPIO3_IO13 0x443c011c, 0x5, 0x0, 0x0, 0x443c02cc
1063 #define IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4 0x443c0120, 0x0, 0x0, 0x0, 0x443c02d0
1064 #define IOMUXC_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x443c0120, 0x1, 0x0, 0x0, 0x443c02d0
1065 #define IOMUXC_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x443c0120, 0x4, 0x443c03a0, 0x1, 0x443c02d0
1066 #define IOMUXC_PAD_SD1_DATA4__GPIO3_IO14 0x443c0120, 0x5, 0x0, 0x0, 0x443c02d0
1067 #define IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5 0x443c0124, 0x0, 0x0, 0x0, 0x443c02d4
1068 #define IOMUXC_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x443c0124, 0x1, 0x0, 0x0, 0x443c02d4
1069 #define IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B 0x443c0124, 0x2, 0x0, 0x0, 0x443c02d4
1070 #define IOMUXC_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x443c0124, 0x4, 0x443c03a4, 0x1, 0x443c02d4
1071 #define IOMUXC_PAD_SD1_DATA5__GPIO3_IO15 0x443c0124, 0x5, 0x0, 0x0, 0x443c02d4
1072 #define IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6 0x443c0128, 0x0, 0x0, 0x0, 0x443c02d8
1073 #define IOMUXC_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x443c0128, 0x1, 0x0, 0x0, 0x443c02d8
1074 #define IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B 0x443c0128, 0x2, 0x0, 0x0, 0x443c02d8
1075 #define IOMUXC_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x443c0128, 0x4, 0x443c03a8, 0x1, 0x443c02d8
1076 #define IOMUXC_PAD_SD1_DATA6__GPIO3_IO16 0x443c0128, 0x5, 0x0, 0x0, 0x443c02d8
1077 #define IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7 0x443c012c, 0x0, 0x0, 0x0, 0x443c02dc
1078 #define IOMUXC_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x443c012c, 0x1, 0x0, 0x0, 0x443c02dc
1079 #define IOMUXC_PAD_SD1_DATA7__USDHC1_WP 0x443c012c, 0x2, 0x0, 0x0, 0x443c02dc
1080 #define IOMUXC_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x443c012c, 0x4, 0x443c03ac, 0x1, 0x443c02dc
1081 #define IOMUXC_PAD_SD1_DATA7__GPIO3_IO17 0x443c012c, 0x5, 0x0, 0x0, 0x443c02dc
1082 #define IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE 0x443c0130, 0x0, 0x0, 0x0, 0x443c02e0
1083 #define IOMUXC_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x443c0130, 0x1, 0x0, 0x0, 0x443c02e0
1084 #define IOMUXC_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x443c0130, 0x4, 0x443c03b0, 0x1, 0x443c02e0
1085 #define IOMUXC_PAD_SD1_STROBE__GPIO3_IO18 0x443c0130, 0x5, 0x0, 0x0, 0x443c02e0
1086 #define IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT 0x443c0134, 0x0, 0x0, 0x0, 0x443c02e4
1087 #define IOMUXC_PAD_SD2_VSELECT__USDHC2_WP 0x443c0134, 0x1, 0x0, 0x0, 0x443c02e4
1088 #define IOMUXC_PAD_SD2_VSELECT__LPTMR2_ALT3 0x443c0134, 0x2, 0x443c0410, 0x1, 0x443c02e4
1089 #define IOMUXC_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x443c0134, 0x4, 0x0, 0x0, 0x443c02e4
1090 #define IOMUXC_PAD_SD2_VSELECT__GPIO3_IO19 0x443c0134, 0x5, 0x0, 0x0, 0x443c02e4
1091 #define IOMUXC_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x443c0134, 0x6, 0x443c0368, 0x0, 0x443c02e4
1092 #define IOMUXC_PAD_SD3_CLK__USDHC3_CLK 0x443c0138, 0x0, 0x443c0458, 0x1, 0x443c02e8
1093 #define IOMUXC_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x443c0138, 0x1, 0x0, 0x0, 0x443c02e8
1094 #define IOMUXC_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x443c0138, 0x4, 0x443c03b4, 0x1, 0x443c02e8
1095 #define IOMUXC_PAD_SD3_CLK__GPIO3_IO20 0x443c0138, 0x5, 0x0, 0x0, 0x443c02e8
1096 #define IOMUXC_PAD_SD3_CMD__USDHC3_CMD 0x443c013c, 0x0, 0x443c045c, 0x1, 0x443c02ec
1097 #define IOMUXC_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x443c013c, 0x1, 0x0, 0x0, 0x443c02ec
1098 #define IOMUXC_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x443c013c, 0x4, 0x0, 0x0, 0x443c02ec
1099 #define IOMUXC_PAD_SD3_CMD__GPIO3_IO21 0x443c013c, 0x5, 0x0, 0x0, 0x443c02ec
1100 #define IOMUXC_PAD_SD3_DATA0__USDHC3_DATA0 0x443c0140, 0x0, 0x443c0460, 0x1, 0x443c02f0
1101 #define IOMUXC_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x443c0140, 0x1, 0x0, 0x0, 0x443c02f0
1102 #define IOMUXC_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x443c0140, 0x4, 0x443c03b8, 0x1, 0x443c02f0
1103 #define IOMUXC_PAD_SD3_DATA0__GPIO3_IO22 0x443c0140, 0x5, 0x0, 0x0, 0x443c02f0
1104 #define IOMUXC_PAD_SD3_DATA1__USDHC3_DATA1 0x443c0144, 0x0, 0x443c0464, 0x1, 0x443c02f4
1105 #define IOMUXC_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x443c0144, 0x1, 0x0, 0x0, 0x443c02f4
1106 #define IOMUXC_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x443c0144, 0x4, 0x443c03bc, 0x1, 0x443c02f4
1107 #define IOMUXC_PAD_SD3_DATA1__GPIO3_IO23 0x443c0144, 0x5, 0x0, 0x0, 0x443c02f4
1108 #define IOMUXC_PAD_SD3_DATA2__USDHC3_DATA2 0x443c0148, 0x0, 0x443c0468, 0x1, 0x443c02f8
1109 #define IOMUXC_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x443c0148, 0x1, 0x0, 0x0, 0x443c02f8
1110 #define IOMUXC_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x443c0148, 0x4, 0x443c03c0, 0x1, 0x443c02f8
1111 #define IOMUXC_PAD_SD3_DATA2__GPIO3_IO24 0x443c0148, 0x5, 0x0, 0x0, 0x443c02f8
1112 #define IOMUXC_PAD_SD3_DATA3__USDHC3_DATA3 0x443c014c, 0x0, 0x443c046c, 0x1, 0x443c02fc
1113 #define IOMUXC_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x443c014c, 0x1, 0x0, 0x0, 0x443c02fc
1114 #define IOMUXC_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x443c014c, 0x4, 0x443c03c4, 0x1, 0x443c02fc
1115 #define IOMUXC_PAD_SD3_DATA3__GPIO3_IO25 0x443c014c, 0x5, 0x0, 0x0, 0x443c02fc
1116 #define IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B 0x443c0150, 0x0, 0x0, 0x0, 0x443c0300
1117 #define IOMUXC_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x443c0150, 0x1, 0x0, 0x0, 0x443c0300
1118 #define IOMUXC_PAD_SD2_CD_B__I3C2_SCL 0x443c0150, 0x2, 0x443c03cc, 0x1, 0x443c0300
1119 #define IOMUXC_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x443c0150, 0x4, 0x443c036c, 0x1, 0x443c0300
1120 #define IOMUXC_PAD_SD2_CD_B__GPIO3_IO00 0x443c0150, 0x5, 0x0, 0x0, 0x443c0300
1121 #define IOMUXC_PAD_SD2_CLK__USDHC2_CLK 0x443c0154, 0x0, 0x0, 0x0, 0x443c0304
1122 #define IOMUXC_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x443c0154, 0x1, 0x0, 0x0, 0x443c0304
1123 #define IOMUXC_PAD_SD2_CLK__I3C2_SDA 0x443c0154, 0x2, 0x443c03d0, 0x1, 0x443c0304
1124 #define IOMUXC_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x443c0154, 0x4, 0x443c0370, 0x1, 0x443c0304
1125 #define IOMUXC_PAD_SD2_CLK__GPIO3_IO01 0x443c0154, 0x5, 0x0, 0x0, 0x443c0304
1126 #define IOMUXC_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x443c0154, 0x6, 0x0, 0x0, 0x443c0304
1127 #define IOMUXC_PAD_SD2_CMD__USDHC2_CMD 0x443c0158, 0x0, 0x0, 0x0, 0x443c0308
1128 #define IOMUXC_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x443c0158, 0x1, 0x0, 0x0, 0x443c0308
1129 #define IOMUXC_PAD_SD2_CMD__I3C2_PUR 0x443c0158, 0x2, 0x0, 0x0, 0x443c0308
1130 #define IOMUXC_PAD_SD2_CMD__I3C2_PUR_B 0x443c0158, 0x3, 0x0, 0x0, 0x443c0308
1131 #define IOMUXC_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x443c0158, 0x4, 0x443c0374, 0x1, 0x443c0308
1132 #define IOMUXC_PAD_SD2_CMD__GPIO3_IO02 0x443c0158, 0x5, 0x0, 0x0, 0x443c0308
1133 #define IOMUXC_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x443c0158, 0x6, 0x0, 0x0, 0x443c0308
1134 #define IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0 0x443c015c, 0x0, 0x0, 0x0, 0x443c030c
1135 #define IOMUXC_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x443c015c, 0x1, 0x0, 0x0, 0x443c030c
1136 #define IOMUXC_PAD_SD2_DATA0__CAN2_TX 0x443c015c, 0x2, 0x0, 0x0, 0x443c030c
1137 #define IOMUXC_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x443c015c, 0x4, 0x443c0378, 0x1, 0x443c030c
1138 #define IOMUXC_PAD_SD2_DATA0__GPIO3_IO03 0x443c015c, 0x5, 0x0, 0x0, 0x443c030c
1139 #define IOMUXC_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x443c015c, 0x6, 0x0, 0x0, 0x443c030c
1140 #define IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1 0x443c0160, 0x0, 0x0, 0x0, 0x443c0310
1141 #define IOMUXC_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x443c0160, 0x1, 0x0, 0x0, 0x443c0310
1142 #define IOMUXC_PAD_SD2_DATA1__CAN2_RX 0x443c0160, 0x2, 0x443c0364, 0x3, 0x443c0310
1143 #define IOMUXC_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x443c0160, 0x4, 0x443c037c, 0x1, 0x443c0310
1144 #define IOMUXC_PAD_SD2_DATA1__GPIO3_IO04 0x443c0160, 0x5, 0x0, 0x0, 0x443c0310
1145 #define IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2 0x443c0164, 0x0, 0x0, 0x0, 0x443c0314
1146 #define IOMUXC_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x443c0164, 0x1, 0x0, 0x0, 0x443c0314
1147 #define IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT 0x443c0164, 0x2, 0x0, 0x0, 0x443c0314
1148 #define IOMUXC_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x443c0164, 0x4, 0x443c0380, 0x1, 0x443c0314
1149 #define IOMUXC_PAD_SD2_DATA2__GPIO3_IO05 0x443c0164, 0x5, 0x0, 0x0, 0x443c0314
1150 #define IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3 0x443c0168, 0x0, 0x0, 0x0, 0x443c0318
1151 #define IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT1 0x443c0168, 0x1, 0x443c0408, 0x1, 0x443c0318
1152 #define IOMUXC_PAD_SD2_DATA3__MQS2_LEFT 0x443c0168, 0x2, 0x0, 0x0, 0x443c0318
1153 #define IOMUXC_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x443c0168, 0x4, 0x443c0384, 0x1, 0x443c0318
1154 #define IOMUXC_PAD_SD2_DATA3__GPIO3_IO06 0x443c0168, 0x5, 0x0, 0x0, 0x443c0318
1155 #define IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B 0x443c016c, 0x0, 0x0, 0x0, 0x443c031c
1156 #define IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT2 0x443c016c, 0x1, 0x443c040c, 0x1, 0x443c031c
1157 #define IOMUXC_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x443c016c, 0x4, 0x443c0388, 0x1, 0x443c031c
1158 #define IOMUXC_PAD_SD2_RESET_B__GPIO3_IO07 0x443c016c, 0x5, 0x0, 0x0, 0x443c031c
1159 #define IOMUXC_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x443c016c, 0x6, 0x0, 0x0, 0x443c031c
1160 #define IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL 0x443c0170, 0x0, 0x0, 0x0, 0x443c0320
1161 #define IOMUXC_PAD_I2C1_SCL__I3C1_SCL 0x443c0170, 0x1, 0x0, 0x0, 0x443c0320
1162 #define IOMUXC_PAD_I2C1_SCL__LPUART1_DCB_B 0x443c0170, 0x2, 0x0, 0x0, 0x443c0320
1163 #define IOMUXC_PAD_I2C1_SCL__TPM2_CH0 0x443c0170, 0x3, 0x0, 0x0, 0x443c0320
1164 #define IOMUXC_PAD_I2C1_SCL__GPIO1_IO00 0x443c0170, 0x5, 0x0, 0x0, 0x443c0320
1165 #define IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA 0x443c0174, 0x0, 0x0, 0x0, 0x443c0324
1166 #define IOMUXC_PAD_I2C1_SDA__I3C1_SDA 0x443c0174, 0x1, 0x0, 0x0, 0x443c0324
1167 #define IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B 0x443c0174, 0x2, 0x0, 0x0, 0x443c0324
1168 #define IOMUXC_PAD_I2C1_SDA__TPM2_CH1 0x443c0174, 0x3, 0x0, 0x0, 0x443c0324
1169 #define IOMUXC_PAD_I2C1_SDA__GPIO1_IO01 0x443c0174, 0x5, 0x0, 0x0, 0x443c0324
1170 #define IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL 0x443c0178, 0x0, 0x0, 0x0, 0x443c0328
1171 #define IOMUXC_PAD_I2C2_SCL__I3C1_PUR 0x443c0178, 0x1, 0x0, 0x0, 0x443c0328
1172 #define IOMUXC_PAD_I2C2_SCL__LPUART2_DCB_B 0x443c0178, 0x2, 0x0, 0x0, 0x443c0328
1173 #define IOMUXC_PAD_I2C2_SCL__TPM2_CH2 0x443c0178, 0x3, 0x0, 0x0, 0x443c0328
1174 #define IOMUXC_PAD_I2C2_SCL__SAI1_RX_SYNC 0x443c0178, 0x4, 0x0, 0x0, 0x443c0328
1175 #define IOMUXC_PAD_I2C2_SCL__GPIO1_IO02 0x443c0178, 0x5, 0x0, 0x0, 0x443c0328
1176 #define IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B 0x443c0178, 0x6, 0x0, 0x0, 0x443c0328
1177 #define IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA 0x443c017c, 0x0, 0x0, 0x0, 0x443c032c
1178 #define IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B 0x443c017c, 0x2, 0x0, 0x0, 0x443c032c
1179 #define IOMUXC_PAD_I2C2_SDA__TPM2_CH3 0x443c017c, 0x3, 0x0, 0x0, 0x443c032c
1180 #define IOMUXC_PAD_I2C2_SDA__SAI1_RX_BCLK 0x443c017c, 0x4, 0x0, 0x0, 0x443c032c
1181 #define IOMUXC_PAD_I2C2_SDA__GPIO1_IO03 0x443c017c, 0x5, 0x0, 0x0, 0x443c032c
1182 #define IOMUXC_PAD_UART1_RXD__LPUART1_RX 0x443c0180, 0x0, 0x0, 0x0, 0x443c0330
1183 #define IOMUXC_PAD_UART1_RXD__S400_UART_RX 0x443c0180, 0x1, 0x0, 0x0, 0x443c0330
1184 #define IOMUXC_PAD_UART1_RXD__LPSPI2_SIN 0x443c0180, 0x2, 0x0, 0x0, 0x443c0330
1185 #define IOMUXC_PAD_UART1_RXD__TPM1_CH0 0x443c0180, 0x3, 0x0, 0x0, 0x443c0330
1186 #define IOMUXC_PAD_UART1_RXD__GPIO1_IO04 0x443c0180, 0x5, 0x0, 0x0, 0x443c0330
1187 #define IOMUXC_PAD_UART1_TXD__LPUART1_TX 0x443c0184, 0x0, 0x0, 0x0, 0x443c0334
1188 #define IOMUXC_PAD_UART1_TXD__S400_UART_TX 0x443c0184, 0x1, 0x0, 0x0, 0x443c0334
1189 #define IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0 0x443c0184, 0x2, 0x0, 0x0, 0x443c0334
1190 #define IOMUXC_PAD_UART1_TXD__TPM1_CH1 0x443c0184, 0x3, 0x0, 0x0, 0x443c0334
1191 #define IOMUXC_PAD_UART1_TXD__GPIO1_IO05 0x443c0184, 0x5, 0x0, 0x0, 0x443c0334
1192 #define IOMUXC_PAD_UART2_RXD__LPUART2_RX 0x443c0188, 0x0, 0x0, 0x0, 0x443c0338
1193 #define IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B 0x443c0188, 0x1, 0x0, 0x0, 0x443c0338
1194 #define IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT 0x443c0188, 0x2, 0x0, 0x0, 0x443c0338
1195 #define IOMUXC_PAD_UART2_RXD__TPM1_CH2 0x443c0188, 0x3, 0x0, 0x0, 0x443c0338
1196 #define IOMUXC_PAD_UART2_RXD__SAI1_MCLK 0x443c0188, 0x4, 0x443c0448, 0x0, 0x443c0338
1197 #define IOMUXC_PAD_UART2_RXD__GPIO1_IO06 0x443c0188, 0x5, 0x0, 0x0, 0x443c0338
1198 #define IOMUXC_PAD_UART2_TXD__LPUART2_TX 0x443c018c, 0x0, 0x0, 0x0, 0x443c033c
1199 #define IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B 0x443c018c, 0x1, 0x0, 0x0, 0x443c033c
1200 #define IOMUXC_PAD_UART2_TXD__LPSPI2_SCK 0x443c018c, 0x2, 0x0, 0x0, 0x443c033c
1201 #define IOMUXC_PAD_UART2_TXD__TPM1_CH3 0x443c018c, 0x3, 0x0, 0x0, 0x443c033c
1202 #define IOMUXC_PAD_UART2_TXD__GPIO1_IO07 0x443c018c, 0x5, 0x0, 0x0, 0x443c033c
1203 #define IOMUXC_PAD_PDM_CLK__PDM_CLK 0x443c0190, 0x0, 0x0, 0x0, 0x443c0340
1204 #define IOMUXC_PAD_PDM_CLK__MQS1_LEFT 0x443c0190, 0x1, 0x0, 0x0, 0x443c0340
1205 #define IOMUXC_PAD_PDM_CLK__LPTMR1_ALT1 0x443c0190, 0x4, 0x0, 0x0, 0x443c0340
1206 #define IOMUXC_PAD_PDM_CLK__GPIO1_IO08 0x443c0190, 0x5, 0x0, 0x0, 0x443c0340
1207 #define IOMUXC_PAD_PDM_CLK__CAN1_TX 0x443c0190, 0x6, 0x0, 0x0, 0x443c0340
1208 #define IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x443c0194, 0x0, 0x443c0438, 0x2, 0x443c0344
1209 #define IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x443c0194, 0x1, 0x0, 0x0, 0x443c0344
1210 #define IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x443c0194, 0x2, 0x0, 0x0, 0x443c0344
1211 #define IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x443c0194, 0x3, 0x0, 0x0, 0x443c0344
1212 #define IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x443c0194, 0x4, 0x0, 0x0, 0x443c0344
1213 #define IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x443c0194, 0x5, 0x0, 0x0, 0x443c0344
1214 #define IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX 0x443c0194, 0x6, 0x443c0360, 0x0, 0x443c0344
1215 #define IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x443c0198, 0x0, 0x443c043c, 0x2, 0x443c0348
1216 #define IOMUXC_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x443c0198, 0x1, 0x0, 0x0, 0x443c0348
1217 #define IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x443c0198, 0x2, 0x0, 0x0, 0x443c0348
1218 #define IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x443c0198, 0x3, 0x0, 0x0, 0x443c0348
1219 #define IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x443c0198, 0x4, 0x0, 0x0, 0x443c0348
1220 #define IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x443c0198, 0x5, 0x0, 0x0, 0x443c0348
1221 #define IOMUXC_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x443c0198, 0x6, 0x443c0368, 0x1, 0x443c0348
1222 #define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x443c019c, 0x0, 0x0, 0x0, 0x443c034c
1223 #define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x443c019c, 0x1, 0x0, 0x0, 0x443c034c
1224 #define IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0 0x443c019c, 0x2, 0x0, 0x0, 0x443c034c
1225 #define IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B 0x443c019c, 0x3, 0x0, 0x0, 0x443c034c
1226 #define IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT 0x443c019c, 0x4, 0x0, 0x0, 0x443c034c
1227 #define IOMUXC_PAD_SAI1_TXFS__GPIO1_IO11 0x443c019c, 0x5, 0x0, 0x0, 0x443c034c
1228 #define IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK 0x443c01a0, 0x0, 0x0, 0x0, 0x443c0350
1229 #define IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B 0x443c01a0, 0x1, 0x0, 0x0, 0x443c0350
1230 #define IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN 0x443c01a0, 0x2, 0x0, 0x0, 0x443c0350
1231 #define IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B 0x443c01a0, 0x3, 0x0, 0x0, 0x443c0350
1232 #define IOMUXC_PAD_SAI1_TXC__CAN1_RX 0x443c01a0, 0x4, 0x443c0360, 0x1, 0x443c0350
1233 #define IOMUXC_PAD_SAI1_TXC__GPIO1_IO12 0x443c01a0, 0x5, 0x0, 0x0, 0x443c0350
1234 #define IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x443c01a4, 0x0, 0x0, 0x0, 0x443c0354
1235 #define IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B 0x443c01a4, 0x1, 0x0, 0x0, 0x443c0354
1236 #define IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK 0x443c01a4, 0x2, 0x0, 0x0, 0x443c0354
1237 #define IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B 0x443c01a4, 0x3, 0x0, 0x0, 0x443c0354
1238 #define IOMUXC_PAD_SAI1_TXD0__CAN1_TX 0x443c01a4, 0x4, 0x0, 0x0, 0x443c0354
1239 #define IOMUXC_PAD_SAI1_TXD0__GPIO1_IO13 0x443c01a4, 0x5, 0x0, 0x0, 0x443c0354
1240 #define IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x443c01a8, 0x0, 0x0, 0x0, 0x443c0358
1241 #define IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK 0x443c01a8, 0x1, 0x443c0448, 0x1, 0x443c0358
1242 #define IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT 0x443c01a8, 0x2, 0x0, 0x0, 0x443c0358
1243 #define IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B 0x443c01a8, 0x3, 0x0, 0x0, 0x443c0358
1244 #define IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT 0x443c01a8, 0x4, 0x0, 0x0, 0x443c0358
1245 #define IOMUXC_PAD_SAI1_RXD0__GPIO1_IO14 0x443c01a8, 0x5, 0x0, 0x0, 0x443c0358
1246 #define IOMUXC_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x443c01ac, 0x0, 0x0, 0x0, 0x443c035c
1247 #define IOMUXC_PAD_WDOG_ANY__GPIO1_IO15 0x443c01ac, 0x5, 0x0, 0x0, 0x443c035c
1248
1249 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) */
1250 /*@}*/
1251
1252 #define IOMUXC_PAD_MUX_MODE_MASK (0x7U)
1253 #define IOMUXC_PAD_MUX_MODE_SHIFT (0U)
1254 #define IOMUXC_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_MUX_MODE_SHIFT)) & IOMUXC_PAD_MUX_MODE_MASK)
1255 #define IOMUXC_PAD_SION_MASK (0x10U)
1256 #define IOMUXC_PAD_SION_SHIFT (4U)
1257 #define IOMUXC_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_SION_SHIFT)) & IOMUXC_PAD_SION_MASK)
1258
1259 #define IOMUXC_PAD_DSE_MASK (0x7EU)
1260 #define IOMUXC_PAD_DSE_SHIFT (1U)
1261 #define IOMUXC_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_DSE_SHIFT)) & IOMUXC_PAD_DSE_MASK)
1262 #define IOMUXC_PAD_FSEL1_MASK (0x180U)
1263 #define IOMUXC_PAD_FSEL1_SHIFT (7U)
1264 #define IOMUXC_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_FSEL1_SHIFT)) & IOMUXC_PAD_FSEL1_MASK)
1265 #define IOMUXC_PAD_PU_MASK (0x200U)
1266 #define IOMUXC_PAD_PU_SHIFT (9U)
1267 #define IOMUXC_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PU_SHIFT)) & IOMUXC_PAD_PU_MASK)
1268 #define IOMUXC_PAD_PD_MASK (0x400U)
1269 #define IOMUXC_PAD_PD_SHIFT (10U)
1270 #define IOMUXC_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PD_SHIFT)) & IOMUXC_PAD_PD_MASK)
1271 #define IOMUXC_PAD_OD_MASK (0x800U)
1272 #define IOMUXC_PAD_OD_SHIFT (11U)
1273 #define IOMUXC_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_OD_SHIFT)) & IOMUXC_PAD_OD_MASK)
1274 #define IOMUXC_PAD_HYS_MASK (0x1000U)
1275 #define IOMUXC_PAD_HYS_SHIFT (11U)
1276 #define IOMUXC_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_HYS_SHIFT)) & IOMUXC_PAD_HYS_MASK)
1277 #define IOMUXC_PAD_APC_MASK (0xFF000000U)
1278 #define IOMUXC_PAD_APC_SHIFT (24U)
1279 #define IOMUXC_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_APC_SHIFT)) & IOMUXC_PAD_APC_MASK)
1280
1281 /*******************************************************************************
1282 * APIs
1283 ******************************************************************************/
1284 #if defined(__cplusplus)
1285 extern "C" {
1286 #endif /*__cplusplus */
1287
1288 /*! @name Configuration */
1289 /*@{*/
1290
1291 /*!
1292 * @brief Sets the IOMUXC pin mux mode.
1293 * @note The first five parameters can be filled with the pin function ID macros.
1294 *
1295 * @param muxRegister The pin mux register
1296 * @param muxMode The pin mux mode
1297 * @param inputRegister The select input register
1298 * @param inputDaisy The input daisy
1299 * @param configRegister The config register
1300 * @param inputOn The software input on
1301 */
IOMUXC_SetPinMux(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t inputOnfield)1302 static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
1303 uint32_t muxMode,
1304 uint32_t inputRegister,
1305 uint32_t inputDaisy,
1306 uint32_t configRegister,
1307 uint32_t inputOnfield)
1308 {
1309 if (muxRegister != 0U)
1310 {
1311 *((volatile uint32_t *)(uintptr_t)muxRegister) = IOMUXC_PAD_MUX_MODE(muxMode) | IOMUXC_PAD_SION(inputOnfield);
1312 }
1313
1314 if (inputRegister != 0U)
1315 {
1316 *((volatile uint32_t *)(uintptr_t)inputRegister) = inputDaisy;
1317 }
1318 }
1319 /*!
1320 * @brief Sets the IOMUXC pin configuration.
1321 * @note The previous five parameters can be filled with the pin function ID macros.
1322 *
1323 * @param muxRegister The pin mux register
1324 * @param muxMode The pin mux mode
1325 * @param inputRegister The select input register
1326 * @param inputDaisy The input daisy
1327 * @param configRegister The config register
1328 * @param configValue The pin config value
1329 */
IOMUXC_SetPinConfig(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t configValue)1330 static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
1331 uint32_t muxMode,
1332 uint32_t inputRegister,
1333 uint32_t inputDaisy,
1334 uint32_t configRegister,
1335 uint32_t configValue)
1336 {
1337 if (configRegister != 0U)
1338 {
1339 *((volatile uint32_t *)(uintptr_t)configRegister) = configValue;
1340 }
1341 }
1342 /*@}*/
1343
1344 #if defined(__cplusplus)
1345 }
1346 #endif /*__cplusplus */
1347
1348 /*! @}*/
1349
1350 #endif /* _FSL_IOMUXC_H_ */
1351
