1 /*
2 * Copyright 2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef _FSL_IOMUXC_H_
7 #define _FSL_IOMUXC_H_
8
9 #include "fsl_common.h"
10
11 /*!
12 * @addtogroup iomuxc_driver
13 * @{
14 */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21 /* Component ID definition, used by tools. */
22 #ifndef FSL_COMPONENT_ID
23 #define FSL_COMPONENT_ID "platform.drivers.iomuxc"
24 #endif
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief IOMUXC driver version 1.0.0. */
29 #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
30 /*@}*/
31
32 /*!
33 * @name Pin function ID
34 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
35 *
36 * @{
37 */
38 #define IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI 0x543c0000, 0x00, 0x543c03d8, 0x00, 0x543c01b0
39 #define IOMUXC_PAD_DAP_TDI__MQS2_LEFT 0x543c0000, 0x01, 0x0, 0x00, 0x543c01b0
40 #define IOMUXC_PAD_DAP_TDI__CAN2_TX 0x543c0000, 0x03, 0x0, 0x00, 0x543c01b0
41 #define IOMUXC_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x543c0000, 0x04, 0x0, 0x00, 0x543c01b0
42 #define IOMUXC_PAD_DAP_TDI__GPIO3_IO28 0x543c0000, 0x05, 0x0, 0x00, 0x543c01b0
43 #define IOMUXC_PAD_DAP_TDI__LPUART5_RX 0x543c0000, 0x06, 0x543c0488, 0x00, 0x543c01b0
44 #define IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x543c0004, 0x00, 0x543c03dc, 0x00, 0x543c01b4
45 #define IOMUXC_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x543c0004, 0x04, 0x0, 0x00, 0x543c01b4
46 #define IOMUXC_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x543c0004, 0x05, 0x0, 0x00, 0x543c01b4
47 #define IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x543c0004, 0x06, 0x0, 0x00, 0x543c01b4
48 #define IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x543c0008, 0x00, 0x543c03d4, 0x00, 0x543c01b8
49 #define IOMUXC_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x543c0008, 0x04, 0x0, 0x00, 0x543c01b8
50 #define IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x543c0008, 0x05, 0x0, 0x00, 0x543c01b8
51 #define IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x543c0008, 0x06, 0x543c0484, 0x00, 0x543c01b8
52 #define IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x543c000c, 0x00, 0x0, 0x00, 0x543c01bc
53 #define IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x543c000c, 0x01, 0x0, 0x00, 0x543c01bc
54 #define IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x543c000c, 0x03, 0x543c0364, 0x00, 0x543c01bc
55 #define IOMUXC_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x543c000c, 0x04, 0x0, 0x00, 0x543c01bc
56 #define IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x543c000c, 0x05, 0x0, 0x00, 0x543c01bc
57 #define IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x543c000c, 0x06, 0x543c048c, 0x00, 0x543c01bc
58 #define IOMUXC_PAD_GPIO_IO00__GPIO2_IO0 0x543c0010, 0x00, 0x0, 0x00, 0x543c01c0
59 #define IOMUXC_PAD_GPIO_IO00__LPI2C3_SDA 0x543c0010, 0x01, 0x543c03f4, 0x00, 0x543c01c0
60 #define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x543c0010, 0x02, 0x543c04bc, 0x00, 0x543c01c0
61 #define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x543c0010, 0x03, 0x0, 0x00, 0x543c01c0
62 #define IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0 0x543c0010, 0x04, 0x0, 0x00, 0x543c01c0
63 #define IOMUXC_PAD_GPIO_IO00__LPUART5_TX 0x543c0010, 0x05, 0x543c048c, 0x01, 0x543c01c0
64 #define IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA 0x543c0010, 0x06, 0x543c0404, 0x00, 0x543c01c0
65 #define IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x543c0010, 0x07, 0x543c036c, 0x00, 0x543c01c0
66 #define IOMUXC_PAD_GPIO_IO01__GPIO2_IO1 0x543c0014, 0x00, 0x0, 0x00, 0x543c01c4
67 #define IOMUXC_PAD_GPIO_IO01__LPI2C3_SCL 0x543c0014, 0x01, 0x543c03f0, 0x00, 0x543c01c4
68 #define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x543c0014, 0x02, 0x543c0490, 0x00, 0x543c01c4
69 #define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x543c0014, 0x03, 0x0, 0x00, 0x543c01c4
70 #define IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN 0x543c0014, 0x04, 0x0, 0x00, 0x543c01c4
71 #define IOMUXC_PAD_GPIO_IO01__LPUART5_RX 0x543c0014, 0x05, 0x543c0488, 0x01, 0x543c01c4
72 #define IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL 0x543c0014, 0x06, 0x543c0400, 0x00, 0x543c01c4
73 #define IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x543c0014, 0x07, 0x543c0370, 0x00, 0x543c01c4
74 #define IOMUXC_PAD_GPIO_IO02__GPIO2_IO3 0x543c0018, 0x00, 0x0, 0x00, 0x543c01c8
75 #define IOMUXC_PAD_GPIO_IO02__LPI2C4_SDA 0x543c0018, 0x01, 0x543c03fc, 0x00, 0x543c01c8
76 #define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x543c0018, 0x02, 0x543c04c0, 0x00, 0x543c01c8
77 #define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x543c0018, 0x03, 0x0, 0x00, 0x543c01c8
78 #define IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT 0x543c0018, 0x04, 0x0, 0x00, 0x543c01c8
79 #define IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B 0x543c0018, 0x05, 0x543c0484, 0x01, 0x543c01c8
80 #define IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA 0x543c0018, 0x06, 0x543c040c, 0x00, 0x543c01c8
81 #define IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO3 0x543c0018, 0x07, 0x543c0374, 0x00, 0x543c01c8
82 #define IOMUXC_PAD_GPIO_IO03__GPIO2_IO3 0x543c001c, 0x00, 0x0, 0x00, 0x543c01cc
83 #define IOMUXC_PAD_GPIO_IO03__LPI2C4_SCL 0x543c001c, 0x01, 0x543c03f8, 0x00, 0x543c01cc
84 #define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x543c001c, 0x02, 0x543c04b8, 0x00, 0x543c01cc
85 #define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x543c001c, 0x03, 0x0, 0x00, 0x543c01cc
86 #define IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK 0x543c001c, 0x04, 0x0, 0x00, 0x543c01cc
87 #define IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B 0x543c001c, 0x05, 0x0, 0x00, 0x543c01cc
88 #define IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL 0x543c001c, 0x06, 0x543c0408, 0x00, 0x543c01cc
89 #define IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x543c001c, 0x07, 0x543c0378, 0x00, 0x543c01cc
90 #define IOMUXC_PAD_GPIO_IO04__GPIO2_IO4 0x543c0020, 0x00, 0x0, 0x00, 0x543c01d0
91 #define IOMUXC_PAD_GPIO_IO04__TPM3_CH0 0x543c0020, 0x01, 0x0, 0x00, 0x543c01d0
92 #define IOMUXC_PAD_GPIO_IO04__PDM_CLK 0x543c0020, 0x02, 0x0, 0x00, 0x543c01d0
93 #define IOMUXC_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x543c0020, 0x03, 0x0, 0x00, 0x543c01d0
94 #define IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0 0x543c0020, 0x04, 0x0, 0x00, 0x543c01d0
95 #define IOMUXC_PAD_GPIO_IO04__LPUART6_TX 0x543c0020, 0x05, 0x0, 0x00, 0x543c01d0
96 #define IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA 0x543c0020, 0x06, 0x543c040c, 0x01, 0x543c01d0
97 #define IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x543c0020, 0x07, 0x543c037c, 0x00, 0x543c01d0
98 #define IOMUXC_PAD_GPIO_IO05__GPIO2_IO5 0x543c0024, 0x00, 0x0, 0x00, 0x543c01d4
99 #define IOMUXC_PAD_GPIO_IO05__TPM4_CH0 0x543c0024, 0x01, 0x0, 0x00, 0x543c01d4
100 #define IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x543c0024, 0x02, 0x543c04c4, 0x00, 0x543c01d4
101 #define IOMUXC_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x543c0024, 0x03, 0x0, 0x00, 0x543c01d4
102 #define IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN 0x543c0024, 0x04, 0x0, 0x00, 0x543c01d4
103 #define IOMUXC_PAD_GPIO_IO05__LPUART6_RX 0x543c0024, 0x05, 0x0, 0x00, 0x543c01d4
104 #define IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL 0x543c0024, 0x06, 0x543c0408, 0x01, 0x543c01d4
105 #define IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x543c0024, 0x07, 0x543c0380, 0x00, 0x543c01d4
106 #define IOMUXC_PAD_GPIO_IO06__GPIO2_IO6 0x543c0028, 0x00, 0x0, 0x00, 0x543c01d8
107 #define IOMUXC_PAD_GPIO_IO06__TPM5_CH0 0x543c0028, 0x01, 0x0, 0x00, 0x543c01d8
108 #define IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x543c0028, 0x02, 0x543c04c8, 0x00, 0x543c01d8
109 #define IOMUXC_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x543c0028, 0x03, 0x0, 0x00, 0x543c01d8
110 #define IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT 0x543c0028, 0x04, 0x0, 0x00, 0x543c01d8
111 #define IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B 0x543c0028, 0x05, 0x0, 0x00, 0x543c01d8
112 #define IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA 0x543c0028, 0x06, 0x543c0414, 0x00, 0x543c01d8
113 #define IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x543c0028, 0x07, 0x543c0384, 0x00, 0x543c01d8
114 #define IOMUXC_PAD_GPIO_IO07__GPIO2_IO7 0x543c002c, 0x00, 0x0, 0x00, 0x543c01dc
115 #define IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1 0x543c002c, 0x01, 0x0, 0x00, 0x543c01dc
116 #define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x543c002c, 0x02, 0x543c0494, 0x00, 0x543c01dc
117 #define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x543c002c, 0x03, 0x0, 0x00, 0x543c01dc
118 #define IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK 0x543c002c, 0x04, 0x0, 0x00, 0x543c01dc
119 #define IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B 0x543c002c, 0x05, 0x0, 0x00, 0x543c01dc
120 #define IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL 0x543c002c, 0x06, 0x543c0410, 0x00, 0x543c01dc
121 #define IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x543c002c, 0x07, 0x543c0388, 0x00, 0x543c01dc
122 #define IOMUXC_PAD_GPIO_IO08__GPIO2_IO8 0x543c0030, 0x00, 0x0, 0x00, 0x543c01e0
123 #define IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0 0x543c0030, 0x01, 0x0, 0x00, 0x543c01e0
124 #define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x543c0030, 0x02, 0x543c0498, 0x00, 0x543c01e0
125 #define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x543c0030, 0x03, 0x0, 0x00, 0x543c01e0
126 #define IOMUXC_PAD_GPIO_IO08__TPM6_CH0 0x543c0030, 0x04, 0x0, 0x00, 0x543c01e0
127 #define IOMUXC_PAD_GPIO_IO08__LPUART7_TX 0x543c0030, 0x05, 0x0, 0x00, 0x543c01e0
128 #define IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA 0x543c0030, 0x06, 0x543c0414, 0x01, 0x543c01e0
129 #define IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x543c0030, 0x07, 0x543c038c, 0x00, 0x543c01e0
130 #define IOMUXC_PAD_GPIO_IO09__GPIO2_IO9 0x543c0034, 0x00, 0x0, 0x00, 0x543c01e4
131 #define IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN 0x543c0034, 0x01, 0x0, 0x00, 0x543c01e4
132 #define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x543c0034, 0x02, 0x543c049c, 0x00, 0x543c01e4
133 #define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x543c0034, 0x03, 0x0, 0x00, 0x543c01e4
134 #define IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK 0x543c0034, 0x04, 0x0, 0x00, 0x543c01e4
135 #define IOMUXC_PAD_GPIO_IO09__LPUART7_RX 0x543c0034, 0x05, 0x0, 0x00, 0x543c01e4
136 #define IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL 0x543c0034, 0x06, 0x543c0410, 0x01, 0x543c01e4
137 #define IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x543c0034, 0x07, 0x543c0390, 0x00, 0x543c01e4
138 #define IOMUXC_PAD_GPIO_IO10__GPIO2_IO10 0x543c0038, 0x00, 0x0, 0x00, 0x543c01e8
139 #define IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT 0x543c0038, 0x01, 0x0, 0x00, 0x543c01e8
140 #define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x543c0038, 0x02, 0x543c04a0, 0x00, 0x543c01e8
141 #define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x543c0038, 0x03, 0x0, 0x00, 0x543c01e8
142 #define IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK 0x543c0038, 0x04, 0x0, 0x00, 0x543c01e8
143 #define IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B 0x543c0038, 0x05, 0x0, 0x00, 0x543c01e8
144 #define IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA 0x543c0038, 0x06, 0x543c041c, 0x00, 0x543c01e8
145 #define IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x543c0038, 0x07, 0x543c0394, 0x00, 0x543c01e8
146 #define IOMUXC_PAD_GPIO_IO11__GPIO2_IO11 0x543c003c, 0x00, 0x0, 0x00, 0x543c01ec
147 #define IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK 0x543c003c, 0x01, 0x0, 0x00, 0x543c01ec
148 #define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x543c003c, 0x02, 0x543c04a4, 0x00, 0x543c01ec
149 #define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x543c003c, 0x03, 0x0, 0x00, 0x543c01ec
150 #define IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK 0x543c003c, 0x04, 0x0, 0x00, 0x543c01ec
151 #define IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B 0x543c003c, 0x05, 0x0, 0x00, 0x543c01ec
152 #define IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL 0x543c003c, 0x06, 0x543c0418, 0x00, 0x543c01ec
153 #define IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x543c003c, 0x07, 0x543c0398, 0x00, 0x543c01ec
154 #define IOMUXC_PAD_GPIO_IO12__GPIO2_IO12 0x543c0040, 0x00, 0x0, 0x00, 0x543c01f0
155 #define IOMUXC_PAD_GPIO_IO12__TPM3_CH2 0x543c0040, 0x01, 0x0, 0x00, 0x543c01f0
156 #define IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x543c0040, 0x02, 0x543c04cc, 0x00, 0x543c01f0
157 #define IOMUXC_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x543c0040, 0x03, 0x0, 0x00, 0x543c01f0
158 #define IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0 0x543c0040, 0x04, 0x0, 0x00, 0x543c01f0
159 #define IOMUXC_PAD_GPIO_IO12__LPUART8_TX 0x543c0040, 0x05, 0x0, 0x00, 0x543c01f0
160 #define IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA 0x543c0040, 0x06, 0x543c041c, 0x01, 0x543c01f0
161 #define IOMUXC_PAD_GPIO_IO12__SAI3_RX_SYNC 0x543c0040, 0x07, 0x543c04dc, 0x00, 0x543c01f0
162 #define IOMUXC_PAD_GPIO_IO13__GPIO2_IO13 0x543c0044, 0x00, 0x0, 0x00, 0x543c01f4
163 #define IOMUXC_PAD_GPIO_IO13__TPM4_CH2 0x543c0044, 0x01, 0x0, 0x00, 0x543c01f4
164 #define IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x543c0044, 0x02, 0x543c04d0, 0x00, 0x543c01f4
165 #define IOMUXC_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x543c0044, 0x03, 0x0, 0x00, 0x543c01f4
166 #define IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN 0x543c0044, 0x04, 0x0, 0x00, 0x543c01f4
167 #define IOMUXC_PAD_GPIO_IO13__LPUART8_RX 0x543c0044, 0x05, 0x0, 0x00, 0x543c01f4
168 #define IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL 0x543c0044, 0x06, 0x543c0418, 0x01, 0x543c01f4
169 #define IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x543c0044, 0x07, 0x543c039c, 0x00, 0x543c01f4
170 #define IOMUXC_PAD_GPIO_IO14__GPIO2_IO14 0x543c0048, 0x00, 0x0, 0x00, 0x543c01f8
171 #define IOMUXC_PAD_GPIO_IO14__LPUART3_TX 0x543c0048, 0x01, 0x543c0474, 0x00, 0x543c01f8
172 #define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x543c0048, 0x02, 0x543c04a8, 0x00, 0x543c01f8
173 #define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x543c0048, 0x03, 0x0, 0x00, 0x543c01f8
174 #define IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT 0x543c0048, 0x04, 0x0, 0x00, 0x543c01f8
175 #define IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B 0x543c0048, 0x05, 0x0, 0x00, 0x543c01f8
176 #define IOMUXC_PAD_GPIO_IO14__LPUART4_TX 0x543c0048, 0x06, 0x543c0480, 0x00, 0x543c01f8
177 #define IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x543c0048, 0x07, 0x543c03a0, 0x00, 0x543c01f8
178 #define IOMUXC_PAD_GPIO_IO15__GPIO2_IO15 0x543c004c, 0x00, 0x0, 0x00, 0x543c01fc
179 #define IOMUXC_PAD_GPIO_IO15__LPUART3_RX 0x543c004c, 0x01, 0x543c0470, 0x00, 0x543c01fc
180 #define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x543c004c, 0x02, 0x543c04ac, 0x00, 0x543c01fc
181 #define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x543c004c, 0x03, 0x0, 0x00, 0x543c01fc
182 #define IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK 0x543c004c, 0x04, 0x0, 0x00, 0x543c01fc
183 #define IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B 0x543c004c, 0x05, 0x0, 0x00, 0x543c01fc
184 #define IOMUXC_PAD_GPIO_IO15__LPUART4_RX 0x543c004c, 0x06, 0x543c047c, 0x00, 0x543c01fc
185 #define IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x543c004c, 0x07, 0x543c03a4, 0x00, 0x543c01fc
186 #define IOMUXC_PAD_GPIO_IO16__GPIO2_IO16 0x543c0050, 0x00, 0x0, 0x00, 0x543c0200
187 #define IOMUXC_PAD_GPIO_IO16__SAI3_TX_BCLK 0x543c0050, 0x01, 0x0, 0x00, 0x543c0200
188 #define IOMUXC_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x543c0050, 0x02, 0x543c04cc, 0x01, 0x543c0200
189 #define IOMUXC_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x543c0050, 0x03, 0x0, 0x00, 0x543c0200
190 #define IOMUXC_PAD_GPIO_IO16__LPUART3_CTS_B 0x543c0050, 0x04, 0x543c046c, 0x00, 0x543c0200
191 #define IOMUXC_PAD_GPIO_IO16__LPSPI4_PCS2 0x543c0050, 0x05, 0x0, 0x00, 0x543c0200
192 #define IOMUXC_PAD_GPIO_IO16__LPUART4_CTS_B 0x543c0050, 0x06, 0x543c0478, 0x00, 0x543c0200
193 #define IOMUXC_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x543c0050, 0x07, 0x543c03a8, 0x00, 0x543c0200
194 #define IOMUXC_PAD_GPIO_IO17__GPIO2_IO17 0x543c0054, 0x00, 0x0, 0x00, 0x543c0204
195 #define IOMUXC_PAD_GPIO_IO17__SAI3_MCLK 0x543c0054, 0x01, 0x0, 0x00, 0x543c0204
196 #define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x543c0054, 0x02, 0x543c04b0, 0x00, 0x543c0204
197 #define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x543c0054, 0x03, 0x0, 0x00, 0x543c0204
198 #define IOMUXC_PAD_GPIO_IO17__LPUART3_RTS_B 0x543c0054, 0x04, 0x0, 0x00, 0x543c0204
199 #define IOMUXC_PAD_GPIO_IO17__LPSPI4_PCS1 0x543c0054, 0x05, 0x0, 0x00, 0x543c0204
200 #define IOMUXC_PAD_GPIO_IO17__LPUART4_RTS_B 0x543c0054, 0x06, 0x0, 0x00, 0x543c0204
201 #define IOMUXC_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x543c0054, 0x07, 0x543c03ac, 0x00, 0x543c0204
202 #define IOMUXC_PAD_GPIO_IO18__GPIO2_IO18 0x543c0058, 0x00, 0x0, 0x00, 0x543c0208
203 #define IOMUXC_PAD_GPIO_IO18__SAI3_RX_BCLK 0x543c0058, 0x01, 0x543c04d8, 0x00, 0x543c0208
204 #define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x543c0058, 0x02, 0x543c04b4, 0x00, 0x543c0208
205 #define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x543c0058, 0x03, 0x0, 0x00, 0x543c0208
206 #define IOMUXC_PAD_GPIO_IO18__LPSPI5_PCS0 0x543c0058, 0x04, 0x0, 0x00, 0x543c0208
207 #define IOMUXC_PAD_GPIO_IO18__LPSPI4_PCS0 0x543c0058, 0x05, 0x0, 0x00, 0x543c0208
208 #define IOMUXC_PAD_GPIO_IO18__TPM5_CH2 0x543c0058, 0x06, 0x0, 0x00, 0x543c0208
209 #define IOMUXC_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x543c0058, 0x07, 0x543c03b0, 0x00, 0x543c0208
210 #define IOMUXC_PAD_GPIO_IO19__GPIO2_IO19 0x543c005c, 0x00, 0x0, 0x00, 0x543c020c
211 #define IOMUXC_PAD_GPIO_IO19__SAI3_RX_SYNC 0x543c005c, 0x01, 0x543c04dc, 0x01, 0x543c020c
212 #define IOMUXC_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x543c005c, 0x02, 0x543c04d0, 0x01, 0x543c020c
213 #define IOMUXC_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x543c005c, 0x03, 0x0, 0x00, 0x543c020c
214 #define IOMUXC_PAD_GPIO_IO19__LPSPI5_SIN 0x543c005c, 0x04, 0x0, 0x00, 0x543c020c
215 #define IOMUXC_PAD_GPIO_IO19__LPSPI4_SIN 0x543c005c, 0x05, 0x0, 0x00, 0x543c020c
216 #define IOMUXC_PAD_GPIO_IO19__TPM6_CH2 0x543c005c, 0x06, 0x0, 0x00, 0x543c020c
217 #define IOMUXC_PAD_GPIO_IO19__SAI3_TX_DATA0 0x543c005c, 0x07, 0x0, 0x00, 0x543c020c
218 #define IOMUXC_PAD_GPIO_IO20__GPIO2_IO20 0x543c0060, 0x00, 0x0, 0x00, 0x543c0210
219 #define IOMUXC_PAD_GPIO_IO20__SAI3_RX_DATA0 0x543c0060, 0x01, 0x0, 0x00, 0x543c0210
220 #define IOMUXC_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x543c0060, 0x02, 0x543c04c4, 0x01, 0x543c0210
221 #define IOMUXC_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x543c0060, 0x03, 0x0, 0x00, 0x543c0210
222 #define IOMUXC_PAD_GPIO_IO20__LPSPI5_SOUT 0x543c0060, 0x04, 0x0, 0x00, 0x543c0210
223 #define IOMUXC_PAD_GPIO_IO20__LPSPI4_SOUT 0x543c0060, 0x05, 0x0, 0x00, 0x543c0210
224 #define IOMUXC_PAD_GPIO_IO20__TPM3_CH1 0x543c0060, 0x06, 0x0, 0x00, 0x543c0210
225 #define IOMUXC_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x543c0060, 0x07, 0x543c03b4, 0x00, 0x543c0210
226 #define IOMUXC_PAD_GPIO_IO21__GPIO2_IO21 0x543c0064, 0x00, 0x0, 0x00, 0x543c0214
227 #define IOMUXC_PAD_GPIO_IO21__SAI3_TX_DATA0 0x543c0064, 0x01, 0x0, 0x00, 0x543c0214
228 #define IOMUXC_PAD_GPIO_IO21__PDM_CLK 0x543c0064, 0x02, 0x0, 0x00, 0x543c0214
229 #define IOMUXC_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x543c0064, 0x03, 0x0, 0x00, 0x543c0214
230 #define IOMUXC_PAD_GPIO_IO21__LPSPI5_SCK 0x543c0064, 0x04, 0x0, 0x00, 0x543c0214
231 #define IOMUXC_PAD_GPIO_IO21__LPSPI4_SCK 0x543c0064, 0x05, 0x0, 0x00, 0x543c0214
232 #define IOMUXC_PAD_GPIO_IO21__TPM4_CH1 0x543c0064, 0x06, 0x0, 0x00, 0x543c0214
233 #define IOMUXC_PAD_GPIO_IO21__SAI3_RX_BCLK 0x543c0064, 0x07, 0x543c04d8, 0x01, 0x543c0214
234 #define IOMUXC_PAD_GPIO_IO22__GPIO2_IO22 0x543c0068, 0x00, 0x0, 0x00, 0x543c0218
235 #define IOMUXC_PAD_GPIO_IO22__USDHC3_CLK 0x543c0068, 0x01, 0x543c04e8, 0x00, 0x543c0218
236 #define IOMUXC_PAD_GPIO_IO22__SPDIF_IN 0x543c0068, 0x02, 0x543c04e4, 0x00, 0x543c0218
237 #define IOMUXC_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x543c0068, 0x03, 0x0, 0x00, 0x543c0218
238 #define IOMUXC_PAD_GPIO_IO22__TPM5_CH1 0x543c0068, 0x04, 0x0, 0x00, 0x543c0218
239 #define IOMUXC_PAD_GPIO_IO22__TPM6_EXTCLK 0x543c0068, 0x05, 0x0, 0x00, 0x543c0218
240 #define IOMUXC_PAD_GPIO_IO22__LPI2C5_SDA 0x543c0068, 0x06, 0x543c0404, 0x01, 0x543c0218
241 #define IOMUXC_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x543c0068, 0x07, 0x543c03b8, 0x00, 0x543c0218
242 #define IOMUXC_PAD_GPIO_IO23__GPIO2_IO23 0x543c006c, 0x00, 0x0, 0x00, 0x543c021c
243 #define IOMUXC_PAD_GPIO_IO23__USDHC3_CMD 0x543c006c, 0x01, 0x543c04ec, 0x00, 0x543c021c
244 #define IOMUXC_PAD_GPIO_IO23__SPDIF_OUT 0x543c006c, 0x02, 0x0, 0x00, 0x543c021c
245 #define IOMUXC_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x543c006c, 0x03, 0x0, 0x00, 0x543c021c
246 #define IOMUXC_PAD_GPIO_IO23__TPM6_CH1 0x543c006c, 0x04, 0x0, 0x00, 0x543c021c
247 #define IOMUXC_PAD_GPIO_IO23__LPI2C5_SCL 0x543c006c, 0x06, 0x543c0400, 0x01, 0x543c021c
248 #define IOMUXC_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x543c006c, 0x07, 0x543c03bc, 0x00, 0x543c021c
249 #define IOMUXC_PAD_GPIO_IO24__GPIO2_IO24 0x543c0070, 0x00, 0x0, 0x00, 0x543c0220
250 #define IOMUXC_PAD_GPIO_IO24__USDHC3_DATA0 0x543c0070, 0x01, 0x543c04f0, 0x00, 0x543c0220
251 #define IOMUXC_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x543c0070, 0x03, 0x0, 0x00, 0x543c0220
252 #define IOMUXC_PAD_GPIO_IO24__TPM3_CH3 0x543c0070, 0x04, 0x0, 0x00, 0x543c0220
253 #define IOMUXC_PAD_GPIO_IO24__JTAG_MUX_TDO 0x543c0070, 0x05, 0x0, 0x00, 0x543c0220
254 #define IOMUXC_PAD_GPIO_IO24__LPSPI6_PCS1 0x543c0070, 0x06, 0x0, 0x00, 0x543c0220
255 #define IOMUXC_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x543c0070, 0x07, 0x543c03c0, 0x00, 0x543c0220
256 #define IOMUXC_PAD_GPIO_IO25__GPIO2_IO25 0x543c0074, 0x00, 0x0, 0x00, 0x543c0224
257 #define IOMUXC_PAD_GPIO_IO25__USDHC3_DATA1 0x543c0074, 0x01, 0x543c04f4, 0x00, 0x543c0224
258 #define IOMUXC_PAD_GPIO_IO25__CAN2_TX 0x543c0074, 0x02, 0x0, 0x00, 0x543c0224
259 #define IOMUXC_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x543c0074, 0x03, 0x0, 0x00, 0x543c0224
260 #define IOMUXC_PAD_GPIO_IO25__TPM4_CH3 0x543c0074, 0x04, 0x0, 0x00, 0x543c0224
261 #define IOMUXC_PAD_GPIO_IO25__JTAG_MUX_TCK 0x543c0074, 0x05, 0x543c03d4, 0x01, 0x543c0224
262 #define IOMUXC_PAD_GPIO_IO25__LPSPI7_PCS1 0x543c0074, 0x06, 0x0, 0x00, 0x543c0224
263 #define IOMUXC_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x543c0074, 0x07, 0x543c03c4, 0x00, 0x543c0224
264 #define IOMUXC_PAD_GPIO_IO26__GPIO2_IO26 0x543c0078, 0x00, 0x0, 0x00, 0x543c0228
265 #define IOMUXC_PAD_GPIO_IO26__USDHC3_DATA2 0x543c0078, 0x01, 0x543c04f8, 0x00, 0x543c0228
266 #define IOMUXC_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x543c0078, 0x02, 0x543c04c8, 0x01, 0x543c0228
267 #define IOMUXC_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x543c0078, 0x03, 0x0, 0x00, 0x543c0228
268 #define IOMUXC_PAD_GPIO_IO26__TPM5_CH3 0x543c0078, 0x04, 0x0, 0x00, 0x543c0228
269 #define IOMUXC_PAD_GPIO_IO26__JTAG_MUX_TDI 0x543c0078, 0x05, 0x543c03d8, 0x01, 0x543c0228
270 #define IOMUXC_PAD_GPIO_IO26__LPSPI8_PCS1 0x543c0078, 0x06, 0x0, 0x00, 0x543c0228
271 #define IOMUXC_PAD_GPIO_IO26__SAI3_TX_SYNC 0x543c0078, 0x07, 0x543c04e0, 0x00, 0x543c0228
272 #define IOMUXC_PAD_GPIO_IO27__GPIO2_IO27 0x543c007c, 0x00, 0x0, 0x00, 0x543c022c
273 #define IOMUXC_PAD_GPIO_IO27__USDHC3_DATA3 0x543c007c, 0x01, 0x543c04fc, 0x00, 0x543c022c
274 #define IOMUXC_PAD_GPIO_IO27__CAN2_RX 0x543c007c, 0x02, 0x543c0364, 0x01, 0x543c022c
275 #define IOMUXC_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x543c007c, 0x03, 0x0, 0x00, 0x543c022c
276 #define IOMUXC_PAD_GPIO_IO27__TPM6_CH3 0x543c007c, 0x04, 0x0, 0x00, 0x543c022c
277 #define IOMUXC_PAD_GPIO_IO27__JTAG_MUX_TMS 0x543c007c, 0x05, 0x543c03dc, 0x01, 0x543c022c
278 #define IOMUXC_PAD_GPIO_IO27__LPSPI5_PCS1 0x543c007c, 0x06, 0x0, 0x00, 0x543c022c
279 #define IOMUXC_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x543c007c, 0x07, 0x543c03c8, 0x00, 0x543c022c
280 #define IOMUXC_PAD_GPIO_IO28__GPIO2_IO28 0x543c0080, 0x00, 0x0, 0x00, 0x543c0230
281 #define IOMUXC_PAD_GPIO_IO28__LPI2C3_SDA 0x543c0080, 0x01, 0x543c03f4, 0x01, 0x543c0230
282 #define IOMUXC_PAD_GPIO_IO28__CAN1_TX 0x543c0080, 0x02, 0x0, 0x00, 0x543c0230
283 #define IOMUXC_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x543c0080, 0x07, 0x0, 0x00, 0x543c0230
284 #define IOMUXC_PAD_GPIO_IO29__GPIO2_IO29 0x543c0084, 0x00, 0x0, 0x00, 0x543c0234
285 #define IOMUXC_PAD_GPIO_IO29__LPI2C3_SCL 0x543c0084, 0x01, 0x543c03f0, 0x01, 0x543c0234
286 #define IOMUXC_PAD_GPIO_IO29__CAN1_RX 0x543c0084, 0x02, 0x543c0360, 0x00, 0x543c0234
287 #define IOMUXC_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x543c0084, 0x07, 0x0, 0x00, 0x543c0234
288 #define IOMUXC_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x543c0088, 0x00, 0x0, 0x00, 0x543c0238
289 #define IOMUXC_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x543c0088, 0x04, 0x0, 0x00, 0x543c0238
290 #define IOMUXC_PAD_CCM_CLKO1__GPIO3_IO26 0x543c0088, 0x05, 0x0, 0x00, 0x543c0238
291 #define IOMUXC_PAD_CCM_CLKO2__GPIO3_IO27 0x543c008c, 0x05, 0x0, 0x00, 0x543c023c
292 #define IOMUXC_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x543c008c, 0x00, 0x0, 0x00, 0x543c023c
293 #define IOMUXC_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x543c008c, 0x04, 0x543c03c8, 0x01, 0x543c023c
294 #define IOMUXC_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x543c0090, 0x00, 0x0, 0x00, 0x543c0240
295 #define IOMUXC_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x543c0090, 0x04, 0x0, 0x00, 0x543c0240
296 #define IOMUXC_PAD_CCM_CLKO3__GPIO4_IO28 0x543c0090, 0x05, 0x0, 0x00, 0x543c0240
297 #define IOMUXC_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x543c0094, 0x00, 0x0, 0x00, 0x543c0244
298 #define IOMUXC_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x543c0094, 0x04, 0x0, 0x00, 0x543c0244
299 #define IOMUXC_PAD_CCM_CLKO4__GPIO4_IO29 0x543c0094, 0x05, 0x0, 0x00, 0x543c0244
300 #define IOMUXC_PAD_ENET1_MDC__ENET1_MDC 0x543c0098, 0x00, 0x0, 0x00, 0x543c0248
301 #define IOMUXC_PAD_ENET1_MDC__LPUART3_DCB_B 0x543c0098, 0x01, 0x0, 0x00, 0x543c0248
302 #define IOMUXC_PAD_ENET1_MDC__I3C2_SCL 0x543c0098, 0x02, 0x543c03cc, 0x00, 0x543c0248
303 #define IOMUXC_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x543c0098, 0x03, 0x0, 0x00, 0x543c0248
304 #define IOMUXC_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x543c0098, 0x04, 0x0, 0x00, 0x543c0248
305 #define IOMUXC_PAD_ENET1_MDC__GPIO4_IO0 0x543c0098, 0x05, 0x0, 0x00, 0x543c0248
306 #define IOMUXC_PAD_ENET1_MDC__LPI2C1_SCL 0x543c0098, 0x06, 0x543c03e0, 0x00, 0x543c0248
307 #define IOMUXC_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x543c009c, 0x00, 0x0, 0x00, 0x543c024c
308 #define IOMUXC_PAD_ENET1_MDIO__LPUART3_RIN_B 0x543c009c, 0x01, 0x0, 0x00, 0x543c024c
309 #define IOMUXC_PAD_ENET1_MDIO__I3C2_SDA 0x543c009c, 0x02, 0x543c03d0, 0x00, 0x543c024c
310 #define IOMUXC_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x543c009c, 0x03, 0x0, 0x00, 0x543c024c
311 #define IOMUXC_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x543c009c, 0x04, 0x0, 0x00, 0x543c024c
312 #define IOMUXC_PAD_ENET1_MDIO__GPIO4_IO1 0x543c009c, 0x05, 0x0, 0x00, 0x543c024c
313 #define IOMUXC_PAD_ENET1_MDIO__LPI2C1_SDA 0x543c009c, 0x06, 0x543c03e4, 0x00, 0x543c024c
314 #define IOMUXC_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x543c00a0, 0x00, 0x0, 0x00, 0x543c0250
315 #define IOMUXC_PAD_ENET1_TD3__CAN2_TX 0x543c00a0, 0x02, 0x0, 0x00, 0x543c0250
316 #define IOMUXC_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x543c00a0, 0x03, 0x0, 0x00, 0x543c0250
317 #define IOMUXC_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x543c00a0, 0x04, 0x0, 0x00, 0x543c0250
318 #define IOMUXC_PAD_ENET1_TD3__GPIO4_IO3 0x543c00a0, 0x05, 0x0, 0x00, 0x543c0250
319 #define IOMUXC_PAD_ENET1_TD3__LPI2C1_SCL 0x543c00a0, 0x06, 0x543c03e8, 0x00, 0x543c0250
320 #define IOMUXC_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x543c00a4, 0x00, 0x0, 0x00, 0x543c0254
321 #define IOMUXC_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x543c00a4, 0x01, 0x0, 0x00, 0x543c0254
322 #define IOMUXC_PAD_ENET1_TD2__CAN2_RX 0x543c00a4, 0x02, 0x543c0364, 0x02, 0x543c0254
323 #define IOMUXC_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x543c00a4, 0x03, 0x0, 0x00, 0x543c0254
324 #define IOMUXC_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x543c00a4, 0x04, 0x0, 0x00, 0x543c0254
325 #define IOMUXC_PAD_ENET1_TD2__GPIO4_IO3 0x543c00a4, 0x05, 0x0, 0x00, 0x543c0254
326 #define IOMUXC_PAD_ENET1_TD2__LPI2C2_SDA 0x543c00a4, 0x06, 0x543c03ec, 0x00, 0x543c0254
327 #define IOMUXC_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x543c00a8, 0x00, 0x0, 0x00, 0x543c0258
328 #define IOMUXC_PAD_ENET1_TD1__LPUART3_RTS_B 0x543c00a8, 0x01, 0x0, 0x00, 0x543c0258
329 #define IOMUXC_PAD_ENET1_TD1__I3C2_PUR 0x543c00a8, 0x02, 0x0, 0x00, 0x543c0258
330 #define IOMUXC_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x543c00a8, 0x03, 0x0, 0x00, 0x543c0258
331 #define IOMUXC_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x543c00a8, 0x04, 0x0, 0x00, 0x543c0258
332 #define IOMUXC_PAD_ENET1_TD1__GPIO4_IO4 0x543c00a8, 0x05, 0x0, 0x00, 0x543c0258
333 #define IOMUXC_PAD_ENET1_TD1__I3C2_PUR_B 0x543c00a8, 0x06, 0x0, 0x00, 0x543c0258
334 #define IOMUXC_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x543c00ac, 0x00, 0x0, 0x00, 0x543c025c
335 #define IOMUXC_PAD_ENET1_TD0__LPUART3_TX 0x543c00ac, 0x01, 0x543c0474, 0x01, 0x543c025c
336 #define IOMUXC_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x543c00ac, 0x04, 0x0, 0x00, 0x543c025c
337 #define IOMUXC_PAD_ENET1_TD0__GPIO4_IO5 0x543c00ac, 0x05, 0x0, 0x00, 0x543c025c
338 #define IOMUXC_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x543c00b0, 0x00, 0x0, 0x00, 0x543c0260
339 #define IOMUXC_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x543c00b0, 0x01, 0x0, 0x00, 0x543c0260
340 #define IOMUXC_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x543c00b0, 0x04, 0x0, 0x00, 0x543c0260
341 #define IOMUXC_PAD_ENET1_TX_CTL__GPIO4_IO6 0x543c00b0, 0x05, 0x0, 0x00, 0x543c0260
342 #define IOMUXC_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x543c00b0, 0x02, 0x543c043c, 0x00, 0x543c0260
343 #define IOMUXC_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x543c00b4, 0x00, 0x0, 0x00, 0x543c0264
344 #define IOMUXC_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x543c00b4, 0x01, 0x0, 0x00, 0x543c0264
345 #define IOMUXC_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x543c00b4, 0x04, 0x0, 0x00, 0x543c0264
346 #define IOMUXC_PAD_ENET1_TXC__GPIO4_IO7 0x543c00b4, 0x05, 0x0, 0x00, 0x543c0264
347 #define IOMUXC_PAD_ENET1_TXC__LPSPI2_SIN 0x543c00b4, 0x02, 0x543c0440, 0x00, 0x543c0264
348 #define IOMUXC_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x543c00b8, 0x00, 0x0, 0x00, 0x543c0268
349 #define IOMUXC_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x543c00b8, 0x01, 0x0, 0x00, 0x543c0268
350 #define IOMUXC_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x543c00b8, 0x03, 0x0, 0x00, 0x543c0268
351 #define IOMUXC_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x543c00b8, 0x04, 0x0, 0x00, 0x543c0268
352 #define IOMUXC_PAD_ENET1_RX_CTL__GPIO4_IO8 0x543c00b8, 0x05, 0x0, 0x00, 0x543c0268
353 #define IOMUXC_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x543c00b8, 0x02, 0x543c0434, 0x00, 0x543c0268
354 #define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x543c00bc, 0x00, 0x0, 0x00, 0x543c026c
355 #define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x543c00bc, 0x01, 0x0, 0x00, 0x543c026c
356 #define IOMUXC_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x543c00bc, 0x04, 0x0, 0x00, 0x543c026c
357 #define IOMUXC_PAD_ENET1_RXC__GPIO4_IO9 0x543c00bc, 0x05, 0x0, 0x00, 0x543c026c
358 #define IOMUXC_PAD_ENET1_RXC__LPSPI2_SOUT 0x543c00bc, 0x02, 0x543c0444, 0x00, 0x543c026c
359 #define IOMUXC_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x543c00c0, 0x00, 0x0, 0x00, 0x543c0270
360 #define IOMUXC_PAD_ENET1_RD0__LPUART3_RX 0x543c00c0, 0x01, 0x543c0470, 0x01, 0x543c0270
361 #define IOMUXC_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x543c00c0, 0x04, 0x0, 0x00, 0x543c0270
362 #define IOMUXC_PAD_ENET1_RD0__GPIO4_IO10 0x543c00c0, 0x05, 0x0, 0x00, 0x543c0270
363 #define IOMUXC_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x543c00c4, 0x00, 0x0, 0x00, 0x543c0274
364 #define IOMUXC_PAD_ENET1_RD1__LPUART3_CTS_B 0x543c00c4, 0x01, 0x543c046c, 0x01, 0x543c0274
365 #define IOMUXC_PAD_ENET1_RD1__LPTMR2_ALT1 0x543c00c4, 0x03, 0x543c0448, 0x00, 0x543c0274
366 #define IOMUXC_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x543c00c4, 0x04, 0x0, 0x00, 0x543c0274
367 #define IOMUXC_PAD_ENET1_RD1__GPIO4_IO11 0x543c00c4, 0x05, 0x0, 0x00, 0x543c0274
368 #define IOMUXC_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x543c00c8, 0x00, 0x0, 0x00, 0x543c0278
369 #define IOMUXC_PAD_ENET1_RD2__LPTMR2_ALT2 0x543c00c8, 0x03, 0x543c044c, 0x00, 0x543c0278
370 #define IOMUXC_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x543c00c8, 0x04, 0x0, 0x00, 0x543c0278
371 #define IOMUXC_PAD_ENET1_RD2__GPIO4_IO12 0x543c00c8, 0x05, 0x0, 0x00, 0x543c0278
372 #define IOMUXC_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x543c00cc, 0x00, 0x0, 0x00, 0x543c027c
373 #define IOMUXC_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x543c00cc, 0x02, 0x0, 0x00, 0x543c027c
374 #define IOMUXC_PAD_ENET1_RD3__LPTMR2_ALT3 0x543c00cc, 0x03, 0x543c0450, 0x00, 0x543c027c
375 #define IOMUXC_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x543c00cc, 0x04, 0x0, 0x00, 0x543c027c
376 #define IOMUXC_PAD_ENET1_RD3__GPIO4_IO13 0x543c00cc, 0x05, 0x0, 0x00, 0x543c027c
377 #define IOMUXC_PAD_ENET2_MDC__ENET2_MDC 0x543c00d0, 0x00, 0x0, 0x00, 0x543c0280
378 #define IOMUXC_PAD_ENET2_MDC__LPUART4_DCB_B 0x543c00d0, 0x01, 0x0, 0x00, 0x543c0280
379 #define IOMUXC_PAD_ENET2_MDC__SAI2_RX_SYNC 0x543c00d0, 0x02, 0x0, 0x00, 0x543c0280
380 #define IOMUXC_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x543c00d0, 0x04, 0x0, 0x00, 0x543c0280
381 #define IOMUXC_PAD_ENET2_MDC__GPIO4_IO14 0x543c00d0, 0x05, 0x0, 0x00, 0x543c0280
382 #define IOMUXC_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x543c00d0, 0x06, 0x543c04bc, 0x01, 0x543c0280
383 #define IOMUXC_PAD_ENET2_MDIO__ENET2_MDIO 0x543c00d4, 0x00, 0x0, 0x00, 0x543c0284
384 #define IOMUXC_PAD_ENET2_MDIO__LPUART4_RIN_B 0x543c00d4, 0x01, 0x0, 0x00, 0x543c0284
385 #define IOMUXC_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x543c00d4, 0x02, 0x0, 0x00, 0x543c0284
386 #define IOMUXC_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x543c00d4, 0x04, 0x0, 0x00, 0x543c0284
387 #define IOMUXC_PAD_ENET2_MDIO__GPIO4_IO15 0x543c00d4, 0x05, 0x0, 0x00, 0x543c0284
388 #define IOMUXC_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x543c00d4, 0x06, 0x543c0490, 0x01, 0x543c0284
389 #define IOMUXC_PAD_ENET2_TD3__SAI2_RX_DATA0 0x543c00d8, 0x02, 0x0, 0x00, 0x543c0288
390 #define IOMUXC_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x543c00d8, 0x04, 0x0, 0x00, 0x543c0288
391 #define IOMUXC_PAD_ENET2_TD3__GPIO4_IO16 0x543c00d8, 0x05, 0x0, 0x00, 0x543c0288
392 #define IOMUXC_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x543c00d8, 0x06, 0x543c04c0, 0x01, 0x543c0288
393 #define IOMUXC_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x543c00d8, 0x00, 0x0, 0x00, 0x543c0288
394 #define IOMUXC_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x543c00dc, 0x00, 0x0, 0x00, 0x543c028c
395 #define IOMUXC_PAD_ENET2_TD2__ENET2_TX_CLK2 0x543c00dc, 0x01, 0x0, 0x00, 0x543c028c
396 #define IOMUXC_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x543c00dc, 0x04, 0x0, 0x00, 0x543c028c
397 #define IOMUXC_PAD_ENET2_TD2__GPIO4_IO17 0x543c00dc, 0x05, 0x0, 0x00, 0x543c028c
398 #define IOMUXC_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x543c00dc, 0x06, 0x543c04b8, 0x01, 0x543c028c
399 #define IOMUXC_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x543c00e0, 0x00, 0x0, 0x00, 0x543c0290
400 #define IOMUXC_PAD_ENET2_TD1__LPUART4_RTS_B 0x543c00e0, 0x01, 0x0, 0x00, 0x543c0290
401 #define IOMUXC_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x543c00e0, 0x04, 0x0, 0x00, 0x543c0290
402 #define IOMUXC_PAD_ENET2_TD1__GPIO4_IO18 0x543c00e0, 0x05, 0x0, 0x00, 0x543c0290
403 #define IOMUXC_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x543c00e0, 0x06, 0x543c0494, 0x01, 0x543c0290
404 #define IOMUXC_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x543c00e4, 0x00, 0x0, 0x00, 0x543c0294
405 #define IOMUXC_PAD_ENET2_TD0__LPUART4_TX 0x543c00e4, 0x01, 0x543c0480, 0x01, 0x543c0294
406 #define IOMUXC_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x543c00e4, 0x04, 0x0, 0x00, 0x543c0294
407 #define IOMUXC_PAD_ENET2_TD0__GPIO4_IO19 0x543c00e4, 0x05, 0x0, 0x00, 0x543c0294
408 #define IOMUXC_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x543c00e4, 0x06, 0x543c0498, 0x01, 0x543c0294
409 #define IOMUXC_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x543c00e8, 0x00, 0x0, 0x00, 0x543c0298
410 #define IOMUXC_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x543c00e8, 0x01, 0x0, 0x00, 0x543c0298
411 #define IOMUXC_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x543c00e8, 0x02, 0x0, 0x00, 0x543c0298
412 #define IOMUXC_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x543c00e8, 0x04, 0x0, 0x00, 0x543c0298
413 #define IOMUXC_PAD_ENET2_TX_CTL__GPIO4_IO20 0x543c00e8, 0x05, 0x0, 0x00, 0x543c0298
414 #define IOMUXC_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x543c00e8, 0x06, 0x543c049c, 0x01, 0x543c0298
415 #define IOMUXC_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x543c00ec, 0x00, 0x0, 0x00, 0x543c029c
416 #define IOMUXC_PAD_ENET2_TXC__ENET2_TX_ER 0x543c00ec, 0x01, 0x0, 0x00, 0x543c029c
417 #define IOMUXC_PAD_ENET2_TXC__SAI2_TX_BCLK 0x543c00ec, 0x02, 0x0, 0x00, 0x543c029c
418 #define IOMUXC_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x543c00ec, 0x04, 0x0, 0x00, 0x543c029c
419 #define IOMUXC_PAD_ENET2_TXC__GPIO4_IO21 0x543c00ec, 0x05, 0x0, 0x00, 0x543c029c
420 #define IOMUXC_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x543c00ec, 0x06, 0x543c04a0, 0x01, 0x543c029c
421 #define IOMUXC_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x543c00f0, 0x00, 0x0, 0x00, 0x543c02a0
422 #define IOMUXC_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x543c00f0, 0x01, 0x0, 0x00, 0x543c02a0
423 #define IOMUXC_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x543c00f0, 0x02, 0x0, 0x00, 0x543c02a0
424 #define IOMUXC_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x543c00f0, 0x04, 0x0, 0x00, 0x543c02a0
425 #define IOMUXC_PAD_ENET2_RX_CTL__GPIO4_IO22 0x543c00f0, 0x05, 0x0, 0x00, 0x543c02a0
426 #define IOMUXC_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x543c00f0, 0x06, 0x543c04a4, 0x01, 0x543c02a0
427 #define IOMUXC_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x543c00f4, 0x00, 0x0, 0x00, 0x543c02a4
428 #define IOMUXC_PAD_ENET2_RXC__ENET2_RX_ER 0x543c00f4, 0x01, 0x0, 0x00, 0x543c02a4
429 #define IOMUXC_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x543c00f4, 0x04, 0x0, 0x00, 0x543c02a4
430 #define IOMUXC_PAD_ENET2_RXC__GPIO4_IO23 0x543c00f4, 0x05, 0x0, 0x00, 0x543c02a4
431 #define IOMUXC_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x543c00f4, 0x06, 0x543c04a8, 0x01, 0x543c02a4
432 #define IOMUXC_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x543c00f8, 0x00, 0x0, 0x00, 0x543c02a8
433 #define IOMUXC_PAD_ENET2_RD0__LPUART4_RX 0x543c00f8, 0x01, 0x543c047c, 0x01, 0x543c02a8
434 #define IOMUXC_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x543c00f8, 0x04, 0x0, 0x00, 0x543c02a8
435 #define IOMUXC_PAD_ENET2_RD0__GPIO4_IO24 0x543c00f8, 0x05, 0x0, 0x00, 0x543c02a8
436 #define IOMUXC_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x543c00f8, 0x06, 0x543c04ac, 0x01, 0x543c02a8
437 #define IOMUXC_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x543c00fc, 0x00, 0x0, 0x00, 0x543c02ac
438 #define IOMUXC_PAD_ENET2_RD1__SPDIF_IN 0x543c00fc, 0x01, 0x543c04e4, 0x01, 0x543c02ac
439 #define IOMUXC_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x543c00fc, 0x04, 0x0, 0x00, 0x543c02ac
440 #define IOMUXC_PAD_ENET2_RD1__GPIO4_IO25 0x543c00fc, 0x05, 0x0, 0x00, 0x543c02ac
441 #define IOMUXC_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x543c00fc, 0x06, 0x543c04b0, 0x01, 0x543c02ac
442 #define IOMUXC_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x543c0100, 0x00, 0x0, 0x00, 0x543c02b0
443 #define IOMUXC_PAD_ENET2_RD2__LPUART4_CTS_B 0x543c0100, 0x01, 0x543c0478, 0x01, 0x543c02b0
444 #define IOMUXC_PAD_ENET2_RD2__SAI2_MCLK 0x543c0100, 0x02, 0x0, 0x00, 0x543c02b0
445 #define IOMUXC_PAD_ENET2_RD2__MQS2_RIGHT 0x543c0100, 0x03, 0x0, 0x00, 0x543c02b0
446 #define IOMUXC_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x543c0100, 0x04, 0x0, 0x00, 0x543c02b0
447 #define IOMUXC_PAD_ENET2_RD2__GPIO4_IO26 0x543c0100, 0x05, 0x0, 0x00, 0x543c02b0
448 #define IOMUXC_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x543c0100, 0x06, 0x543c04b4, 0x01, 0x543c02b0
449 #define IOMUXC_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x543c0104, 0x00, 0x0, 0x00, 0x543c02b4
450 #define IOMUXC_PAD_ENET2_RD3__SPDIF_OUT 0x543c0104, 0x01, 0x0, 0x00, 0x543c02b4
451 #define IOMUXC_PAD_ENET2_RD3__SPDIF_IN 0x543c0104, 0x02, 0x543c04e4, 0x02, 0x543c02b4
452 #define IOMUXC_PAD_ENET2_RD3__MQS2_LEFT 0x543c0104, 0x03, 0x0, 0x00, 0x543c02b4
453 #define IOMUXC_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x543c0104, 0x04, 0x0, 0x00, 0x543c02b4
454 #define IOMUXC_PAD_ENET2_RD3__GPIO4_IO27 0x543c0104, 0x05, 0x0, 0x00, 0x543c02b4
455 #define IOMUXC_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x543c0108, 0x04, 0x543c038c, 0x01, 0x543c02b8
456 #define IOMUXC_PAD_SD1_CLK__GPIO3_IO8 0x543c0108, 0x05, 0x0, 0x00, 0x543c02b8
457 #define IOMUXC_PAD_SD1_CLK__USDHC1_CLK 0x543c0108, 0x00, 0x0, 0x00, 0x543c02b8
458 #define IOMUXC_PAD_SD1_CLK__LPSPI2_SCK 0x543c0108, 0x03, 0x543c043c, 0x01, 0x543c02b8
459 #define IOMUXC_PAD_SD1_CMD__USDHC1_CMD 0x543c010c, 0x00, 0x0, 0x00, 0x543c02bc
460 #define IOMUXC_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x543c010c, 0x04, 0x543c0390, 0x01, 0x543c02bc
461 #define IOMUXC_PAD_SD1_CMD__GPIO3_IO9 0x543c010c, 0x05, 0x0, 0x00, 0x543c02bc
462 #define IOMUXC_PAD_SD1_CMD__LPSPI2_SIN 0x543c010c, 0x03, 0x543c0440, 0x01, 0x543c02bc
463 #define IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0 0x543c0110, 0x00, 0x0, 0x00, 0x543c02c0
464 #define IOMUXC_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x543c0110, 0x04, 0x543c0394, 0x01, 0x543c02c0
465 #define IOMUXC_PAD_SD1_DATA0__GPIO3_IO10 0x543c0110, 0x05, 0x0, 0x00, 0x543c02c0
466 #define IOMUXC_PAD_SD1_DATA0__LPSPI2_PCS0 0x543c0110, 0x03, 0x543c0434, 0x01, 0x543c02c0
467 #define IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1 0x543c0114, 0x00, 0x0, 0x00, 0x543c02c4
468 #define IOMUXC_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x543c0114, 0x04, 0x543c0398, 0x01, 0x543c02c4
469 #define IOMUXC_PAD_SD1_DATA1__GPIO3_IO11 0x543c0114, 0x05, 0x0, 0x00, 0x543c02c4
470 #define IOMUXC_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x543c0114, 0x06, 0x0, 0x00, 0x543c02c4
471 #define IOMUXC_PAD_SD1_DATA1__LPSPI2_SOUT 0x543c0114, 0x03, 0x543c0444, 0x01, 0x543c02c4
472 #define IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2 0x543c0118, 0x00, 0x0, 0x00, 0x543c02c8
473 #define IOMUXC_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x543c0118, 0x04, 0x0, 0x00, 0x543c02c8
474 #define IOMUXC_PAD_SD1_DATA2__GPIO3_IO12 0x543c0118, 0x05, 0x0, 0x00, 0x543c02c8
475 #define IOMUXC_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x543c0118, 0x06, 0x0, 0x00, 0x543c02c8
476 #define IOMUXC_PAD_SD1_DATA2__LPSPI2_PCS1 0x543c0118, 0x03, 0x543c0438, 0x00, 0x543c02c8
477 #define IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3 0x543c011c, 0x00, 0x0, 0x00, 0x543c02cc
478 #define IOMUXC_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x543c011c, 0x01, 0x0, 0x00, 0x543c02cc
479 #define IOMUXC_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x543c011c, 0x04, 0x543c039c, 0x01, 0x543c02cc
480 #define IOMUXC_PAD_SD1_DATA3__GPIO3_IO13 0x543c011c, 0x05, 0x0, 0x00, 0x543c02cc
481 #define IOMUXC_PAD_SD1_DATA3__LPSPI1_PCS1 0x543c011c, 0x03, 0x543c0424, 0x00, 0x543c02cc
482 #define IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4 0x543c0120, 0x00, 0x0, 0x00, 0x543c02d0
483 #define IOMUXC_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x543c0120, 0x01, 0x0, 0x00, 0x543c02d0
484 #define IOMUXC_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x543c0120, 0x04, 0x543c03a0, 0x01, 0x543c02d0
485 #define IOMUXC_PAD_SD1_DATA4__GPIO3_IO14 0x543c0120, 0x05, 0x0, 0x00, 0x543c02d0
486 #define IOMUXC_PAD_SD1_DATA4__LPSPI1_PCS0 0x543c0120, 0x03, 0x543c0420, 0x00, 0x543c02d0
487 #define IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5 0x543c0124, 0x00, 0x0, 0x00, 0x543c02d4
488 #define IOMUXC_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x543c0124, 0x01, 0x0, 0x00, 0x543c02d4
489 #define IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B 0x543c0124, 0x02, 0x0, 0x00, 0x543c02d4
490 #define IOMUXC_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x543c0124, 0x04, 0x543c03a4, 0x01, 0x543c02d4
491 #define IOMUXC_PAD_SD1_DATA5__GPIO3_IO15 0x543c0124, 0x05, 0x0, 0x00, 0x543c02d4
492 #define IOMUXC_PAD_SD1_DATA5__LPSPI1_SIN 0x543c0124, 0x03, 0x543c042c, 0x00, 0x543c02d4
493 #define IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6 0x543c0128, 0x00, 0x0, 0x00, 0x543c02d8
494 #define IOMUXC_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x543c0128, 0x01, 0x0, 0x00, 0x543c02d8
495 #define IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B 0x543c0128, 0x02, 0x0, 0x00, 0x543c02d8
496 #define IOMUXC_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x543c0128, 0x04, 0x543c03a8, 0x01, 0x543c02d8
497 #define IOMUXC_PAD_SD1_DATA6__GPIO3_IO16 0x543c0128, 0x05, 0x0, 0x00, 0x543c02d8
498 #define IOMUXC_PAD_SD1_DATA6__LPSPI1_SCK 0x543c0128, 0x03, 0x543c0428, 0x00, 0x543c02d8
499 #define IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7 0x543c012c, 0x00, 0x0, 0x00, 0x543c02dc
500 #define IOMUXC_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x543c012c, 0x01, 0x0, 0x00, 0x543c02dc
501 #define IOMUXC_PAD_SD1_DATA7__USDHC1_WP 0x543c012c, 0x02, 0x0, 0x00, 0x543c02dc
502 #define IOMUXC_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x543c012c, 0x04, 0x543c03ac, 0x01, 0x543c02dc
503 #define IOMUXC_PAD_SD1_DATA7__GPIO3_IO17 0x543c012c, 0x05, 0x0, 0x00, 0x543c02dc
504 #define IOMUXC_PAD_SD1_DATA7__LPSPI1_SOUT 0x543c012c, 0x03, 0x543c0430, 0x00, 0x543c02dc
505 #define IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE 0x543c0130, 0x00, 0x0, 0x00, 0x543c02e0
506 #define IOMUXC_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x543c0130, 0x01, 0x0, 0x00, 0x543c02e0
507 #define IOMUXC_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x543c0130, 0x04, 0x543c03b0, 0x01, 0x543c02e0
508 #define IOMUXC_PAD_SD1_STROBE__GPIO3_IO18 0x543c0130, 0x05, 0x0, 0x00, 0x543c02e0
509 #define IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT 0x543c0134, 0x00, 0x0, 0x00, 0x543c02e4
510 #define IOMUXC_PAD_SD2_VSELECT__USDHC2_WP 0x543c0134, 0x01, 0x0, 0x00, 0x543c02e4
511 #define IOMUXC_PAD_SD2_VSELECT__LPTMR2_ALT3 0x543c0134, 0x02, 0x543c0450, 0x01, 0x543c02e4
512 #define IOMUXC_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x543c0134, 0x04, 0x0, 0x00, 0x543c02e4
513 #define IOMUXC_PAD_SD2_VSELECT__GPIO3_IO19 0x543c0134, 0x05, 0x0, 0x00, 0x543c02e4
514 #define IOMUXC_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x543c0134, 0x06, 0x543c0368, 0x00, 0x543c02e4
515 #define IOMUXC_PAD_SD3_CLK__USDHC3_CLK 0x543c0138, 0x00, 0x543c04e8, 0x01, 0x543c02e8
516 #define IOMUXC_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x543c0138, 0x01, 0x0, 0x00, 0x543c02e8
517 #define IOMUXC_PAD_SD3_CLK__LPUART1_CTS_B 0x543c0138, 0x02, 0x543c0454, 0x00, 0x543c02e8
518 #define IOMUXC_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x543c0138, 0x04, 0x543c03b4, 0x01, 0x543c02e8
519 #define IOMUXC_PAD_SD3_CLK__GPIO3_IO20 0x543c0138, 0x05, 0x0, 0x00, 0x543c02e8
520 #define IOMUXC_PAD_SD3_CMD__USDHC3_CMD 0x543c013c, 0x00, 0x543c04ec, 0x01, 0x543c02ec
521 #define IOMUXC_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x543c013c, 0x01, 0x0, 0x00, 0x543c02ec
522 #define IOMUXC_PAD_SD3_CMD__LPUART1_RTS_B 0x543c013c, 0x02, 0x0, 0x00, 0x543c02ec
523 #define IOMUXC_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x543c013c, 0x04, 0x0, 0x00, 0x543c02ec
524 #define IOMUXC_PAD_SD3_CMD__GPIO3_IO21 0x543c013c, 0x05, 0x0, 0x00, 0x543c02ec
525 #define IOMUXC_PAD_SD3_DATA0__USDHC3_DATA0 0x543c0140, 0x00, 0x543c04f0, 0x01, 0x543c02f0
526 #define IOMUXC_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x543c0140, 0x01, 0x0, 0x00, 0x543c02f0
527 #define IOMUXC_PAD_SD3_DATA0__LPUART2_CTS_B 0x543c0140, 0x02, 0x543c0460, 0x00, 0x543c02f0
528 #define IOMUXC_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x543c0140, 0x04, 0x543c03b8, 0x01, 0x543c02f0
529 #define IOMUXC_PAD_SD3_DATA0__GPIO3_IO22 0x543c0140, 0x05, 0x0, 0x00, 0x543c02f0
530 #define IOMUXC_PAD_SD3_DATA1__USDHC3_DATA1 0x543c0144, 0x00, 0x543c04f4, 0x01, 0x543c02f4
531 #define IOMUXC_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x543c0144, 0x01, 0x0, 0x00, 0x543c02f4
532 #define IOMUXC_PAD_SD3_DATA1__LPUART2_RTS_B 0x543c0144, 0x02, 0x0, 0x00, 0x543c02f4
533 #define IOMUXC_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x543c0144, 0x04, 0x543c03bc, 0x01, 0x543c02f4
534 #define IOMUXC_PAD_SD3_DATA1__GPIO3_IO23 0x543c0144, 0x05, 0x0, 0x00, 0x543c02f4
535 #define IOMUXC_PAD_SD3_DATA2__USDHC3_DATA2 0x543c0148, 0x00, 0x543c04f8, 0x01, 0x543c02f8
536 #define IOMUXC_PAD_SD3_DATA2__LPI2C4_SDA 0x543c0148, 0x02, 0x543c03fc, 0x01, 0x543c02f8
537 #define IOMUXC_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x543c0148, 0x01, 0x0, 0x00, 0x543c02f8
538 #define IOMUXC_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x543c0148, 0x04, 0x543c03c0, 0x01, 0x543c02f8
539 #define IOMUXC_PAD_SD3_DATA2__GPIO3_IO24 0x543c0148, 0x05, 0x0, 0x00, 0x543c02f8
540 #define IOMUXC_PAD_SD3_DATA3__USDHC3_DATA3 0x543c014c, 0x00, 0x543c04fc, 0x01, 0x543c02fc
541 #define IOMUXC_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x543c014c, 0x01, 0x0, 0x00, 0x543c02fc
542 #define IOMUXC_PAD_SD3_DATA3__LPI2C4_SCL 0x543c014c, 0x02, 0x543c03f8, 0x01, 0x543c02fc
543 #define IOMUXC_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x543c014c, 0x04, 0x543c03c4, 0x01, 0x543c02fc
544 #define IOMUXC_PAD_SD3_DATA3__GPIO3_IO25 0x543c014c, 0x05, 0x0, 0x00, 0x543c02fc
545 #define IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B 0x543c0150, 0x00, 0x0, 0x00, 0x543c0300
546 #define IOMUXC_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x543c0150, 0x01, 0x0, 0x00, 0x543c0300
547 #define IOMUXC_PAD_SD2_CD_B__I3C2_SCL 0x543c0150, 0x02, 0x543c03cc, 0x01, 0x543c0300
548 #define IOMUXC_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x543c0150, 0x04, 0x543c036c, 0x01, 0x543c0300
549 #define IOMUXC_PAD_SD2_CD_B__GPIO3_IO0 0x543c0150, 0x05, 0x0, 0x00, 0x543c0300
550 #define IOMUXC_PAD_SD2_CD_B__LPI2C1_SCL 0x543c0150, 0x03, 0x0, 0x00, 0x543c0300
551 #define IOMUXC_PAD_SD2_CLK__USDHC2_CLK 0x543c0154, 0x00, 0x0, 0x00, 0x543c0304
552 #define IOMUXC_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x543c0154, 0x01, 0x0, 0x00, 0x543c0304
553 #define IOMUXC_PAD_SD2_CLK__I2C1_SDA 0x543c0154, 0x03, 0x0, 0x00, 0x543c0304
554 #define IOMUXC_PAD_SD2_CLK__I3C2_SDA 0x543c0154, 0x02, 0x543c03d0, 0x01, 0x543c0304
555 #define IOMUXC_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x543c0154, 0x04, 0x543c0370, 0x01, 0x543c0304
556 #define IOMUXC_PAD_SD2_CLK__GPIO3_IO1 0x543c0154, 0x05, 0x0, 0x00, 0x543c0304
557 #define IOMUXC_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x543c0154, 0x06, 0x0, 0x00, 0x543c0304
558 #define IOMUXC_PAD_SD2_CLK__LPI2C1_SDA 0x543c0154, 0x03, 0x543c03e4, 0x01, 0x543c0304
559 #define IOMUXC_PAD_SD2_CMD__USDHC2_CMD 0x543c0158, 0x00, 0x0, 0x00, 0x543c0308
560 #define IOMUXC_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x543c0158, 0x01, 0x0, 0x00, 0x543c0308
561 #define IOMUXC_PAD_SD2_CMD__I3C2_PUR 0x543c0158, 0x02, 0x0, 0x00, 0x543c0308
562 #define IOMUXC_PAD_SD2_CMD__I3C2_PUR_B 0x543c0158, 0x03, 0x0, 0x00, 0x543c0308
563 #define IOMUXC_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x543c0158, 0x04, 0x543c0374, 0x01, 0x543c0308
564 #define IOMUXC_PAD_SD2_CMD__GPIO3_IO2 0x543c0158, 0x05, 0x0, 0x00, 0x543c0308
565 #define IOMUXC_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x543c0158, 0x06, 0x0, 0x00, 0x543c0308
566 #define IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0 0x543c015c, 0x00, 0x0, 0x00, 0x543c030c
567 #define IOMUXC_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x543c015c, 0x01, 0x0, 0x00, 0x543c030c
568 #define IOMUXC_PAD_SD2_DATA0__CAN2_TX 0x543c015c, 0x02, 0x0, 0x00, 0x543c030c
569 #define IOMUXC_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x543c015c, 0x04, 0x543c0378, 0x01, 0x543c030c
570 #define IOMUXC_PAD_SD2_DATA0__GPIO3_IO3 0x543c015c, 0x05, 0x0, 0x00, 0x543c030c
571 #define IOMUXC_PAD_SD2_DATA0__LPUART1_TX 0x543c015c, 0x03, 0x543c045c, 0x00, 0x543c030c
572 #define IOMUXC_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x543c015c, 0x06, 0x0, 0x00, 0x543c030c
573 #define IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1 0x543c0160, 0x00, 0x0, 0x00, 0x543c0310
574 #define IOMUXC_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x543c0160, 0x01, 0x0, 0x00, 0x543c0310
575 #define IOMUXC_PAD_SD2_DATA1__CAN2_RX 0x543c0160, 0x02, 0x543c0364, 0x03, 0x543c0310
576 #define IOMUXC_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x543c0160, 0x04, 0x543c037c, 0x01, 0x543c0310
577 #define IOMUXC_PAD_SD2_DATA1__GPIO3_IO4 0x543c0160, 0x05, 0x0, 0x00, 0x543c0310
578 #define IOMUXC_PAD_SD2_DATA1__LPUART1_RX 0x543c0160, 0x03, 0x543c0458, 0x00, 0x543c0310
579 #define IOMUXC_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x543c0160, 0x06, 0x0, 0x00, 0x543c0310
580 #define IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2 0x543c0164, 0x00, 0x0, 0x00, 0x543c0314
581 #define IOMUXC_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x543c0164, 0x01, 0x0, 0x00, 0x543c0314
582 #define IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT 0x543c0164, 0x02, 0x0, 0x00, 0x543c0314
583 #define IOMUXC_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x543c0164, 0x04, 0x543c0380, 0x01, 0x543c0314
584 #define IOMUXC_PAD_SD2_DATA2__GPIO3_IO5 0x543c0164, 0x05, 0x0, 0x00, 0x543c0314
585 #define IOMUXC_PAD_SD2_DATA2__LPUART2_TX 0x543c0164, 0x03, 0x543c0468, 0x00, 0x543c0314
586 #define IOMUXC_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x543c0164, 0x06, 0x0, 0x00, 0x543c0314
587 #define IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3 0x543c0168, 0x00, 0x0, 0x00, 0x543c0318
588 #define IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT1 0x543c0168, 0x01, 0x543c0448, 0x01, 0x543c0318
589 #define IOMUXC_PAD_SD2_DATA3__MQS2_LEFT 0x543c0168, 0x02, 0x0, 0x00, 0x543c0318
590 #define IOMUXC_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x543c0168, 0x04, 0x543c0384, 0x01, 0x543c0318
591 #define IOMUXC_PAD_SD2_DATA3__GPIO3_IO6 0x543c0168, 0x05, 0x0, 0x00, 0x543c0318
592 #define IOMUXC_PAD_SD2_DATA3__LPUART2_RX 0x543c0168, 0x03, 0x543c0464, 0x00, 0x543c0318
593 #define IOMUXC_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x543c0168, 0x06, 0x0, 0x00, 0x543c0318
594 #define IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B 0x543c016c, 0x00, 0x0, 0x00, 0x543c031c
595 #define IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT2 0x543c016c, 0x01, 0x543c044c, 0x01, 0x543c031c
596 #define IOMUXC_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x543c016c, 0x04, 0x543c0388, 0x01, 0x543c031c
597 #define IOMUXC_PAD_SD2_RESET_B__GPIO3_IO7 0x543c016c, 0x05, 0x0, 0x00, 0x543c031c
598 #define IOMUXC_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x543c016c, 0x06, 0x0, 0x00, 0x543c031c
599 #define IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL 0x543c0170, 0x00, 0x543c03e0, 0x02, 0x543c0320
600 #define IOMUXC_PAD_I2C1_SCL__I3C1_SCL 0x543c0170, 0x01, 0x0, 0x00, 0x543c0320
601 #define IOMUXC_PAD_I2C1_SCL__LPUART1_DCB_B 0x543c0170, 0x02, 0x0, 0x00, 0x543c0320
602 #define IOMUXC_PAD_I2C1_SCL__TPM2_CH0 0x543c0170, 0x03, 0x0, 0x00, 0x543c0320
603 #define IOMUXC_PAD_I2C1_SCL__GPIO1_IO0 0x543c0170, 0x05, 0x0, 0x00, 0x543c0320
604 #define IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA 0x543c0174, 0x00, 0x543c03e4, 0x02, 0x543c0324
605 #define IOMUXC_PAD_I2C1_SDA__I3C1_SDA 0x543c0174, 0x01, 0x0, 0x00, 0x543c0324
606 #define IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B 0x543c0174, 0x02, 0x0, 0x00, 0x543c0324
607 #define IOMUXC_PAD_I2C1_SDA__TPM2_CH1 0x543c0174, 0x03, 0x0, 0x00, 0x543c0324
608 #define IOMUXC_PAD_I2C1_SDA__GPIO1_IO1 0x543c0174, 0x05, 0x0, 0x00, 0x543c0324
609 #define IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL 0x543c0178, 0x00, 0x543c03e8, 0x01, 0x543c0328
610 #define IOMUXC_PAD_I2C2_SCL__I3C1_PUR 0x543c0178, 0x01, 0x0, 0x00, 0x543c0328
611 #define IOMUXC_PAD_I2C2_SCL__LPUART2_DCB_B 0x543c0178, 0x02, 0x0, 0x00, 0x543c0328
612 #define IOMUXC_PAD_I2C2_SCL__TPM2_CH2 0x543c0178, 0x03, 0x0, 0x00, 0x543c0328
613 #define IOMUXC_PAD_I2C2_SCL__SAI1_RX_SYNC 0x543c0178, 0x04, 0x0, 0x00, 0x543c0328
614 #define IOMUXC_PAD_I2C2_SCL__GPIO1_IO3 0x543c0178, 0x05, 0x0, 0x00, 0x543c0328
615 #define IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B 0x543c0178, 0x06, 0x0, 0x00, 0x543c0328
616 #define IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA 0x543c017c, 0x00, 0x543c03ec, 0x01, 0x543c032c
617 #define IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B 0x543c017c, 0x02, 0x0, 0x00, 0x543c032c
618 #define IOMUXC_PAD_I2C2_SDA__TPM2_CH3 0x543c017c, 0x03, 0x0, 0x00, 0x543c032c
619 #define IOMUXC_PAD_I2C2_SDA__SAI1_RX_BCLK 0x543c017c, 0x04, 0x0, 0x00, 0x543c032c
620 #define IOMUXC_PAD_I2C2_SDA__GPIO1_IO3 0x543c017c, 0x05, 0x0, 0x00, 0x543c032c
621 #define IOMUXC_PAD_UART1_RXD__LPUART1_RX 0x543c0180, 0x00, 0x543c0458, 0x01, 0x543c0330
622 #define IOMUXC_PAD_UART1_RXD__ELE_UART_RX 0x543c0180, 0x01, 0x0, 0x00, 0x543c0330
623 #define IOMUXC_PAD_UART1_RXD__LPSPI2_SIN 0x543c0180, 0x02, 0x543c0440, 0x02, 0x543c0330
624 #define IOMUXC_PAD_UART1_RXD__TPM1_CH0 0x543c0180, 0x03, 0x0, 0x00, 0x543c0330
625 #define IOMUXC_PAD_UART1_RXD__GPIO1_IO4 0x543c0180, 0x05, 0x0, 0x00, 0x543c0330
626 #define IOMUXC_PAD_UART1_TXD__LPUART1_TX 0x543c0184, 0x00, 0x543c045c, 0x01, 0x543c0334
627 #define IOMUXC_PAD_UART1_TXD__ELE_UART_TX 0x543c0184, 0x01, 0x0, 0x00, 0x543c0334
628 #define IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0 0x543c0184, 0x02, 0x543c0434, 0x02, 0x543c0334
629 #define IOMUXC_PAD_UART1_TXD__TPM1_CH1 0x543c0184, 0x03, 0x0, 0x00, 0x543c0334
630 #define IOMUXC_PAD_UART1_TXD__GPIO1_IO5 0x543c0184, 0x05, 0x0, 0x00, 0x543c0334
631 #define IOMUXC_PAD_UART2_RXD__LPUART2_RX 0x543c0188, 0x00, 0x543c0464, 0x01, 0x543c0338
632 #define IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B 0x543c0188, 0x01, 0x543c0454, 0x01, 0x543c0338
633 #define IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT 0x543c0188, 0x02, 0x543c0444, 0x02, 0x543c0338
634 #define IOMUXC_PAD_UART2_RXD__TPM1_CH2 0x543c0188, 0x03, 0x0, 0x00, 0x543c0338
635 #define IOMUXC_PAD_UART2_RXD__SAI1_MCLK 0x543c0188, 0x04, 0x543c04d4, 0x00, 0x543c0338
636 #define IOMUXC_PAD_UART2_RXD__GPIO1_IO6 0x543c0188, 0x05, 0x0, 0x00, 0x543c0338
637 #define IOMUXC_PAD_UART2_TXD__LPUART2_TX 0x543c018c, 0x00, 0x543c0468, 0x01, 0x543c033c
638 #define IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B 0x543c018c, 0x01, 0x0, 0x00, 0x543c033c
639 #define IOMUXC_PAD_UART2_TXD__LPSPI2_SCK 0x543c018c, 0x02, 0x543c043c, 0x02, 0x543c033c
640 #define IOMUXC_PAD_UART2_TXD__TPM1_CH3 0x543c018c, 0x03, 0x0, 0x00, 0x543c033c
641 #define IOMUXC_PAD_UART2_TXD__GPIO1_IO7 0x543c018c, 0x05, 0x0, 0x00, 0x543c033c
642 #define IOMUXC_PAD_UART2_TXD__SAI3_TX_SYNC 0x543c018c, 0x07, 0x543c04e0, 0x02, 0x543c033c
643 #define IOMUXC_PAD_PDM_CLK__PDM_CLK 0x543c0190, 0x00, 0x0, 0x00, 0x543c0340
644 #define IOMUXC_PAD_PDM_CLK__MQS1_LEFT 0x543c0190, 0x01, 0x0, 0x00, 0x543c0340
645 #define IOMUXC_PAD_PDM_CLK__LPTMR1_ALT1 0x543c0190, 0x04, 0x0, 0x00, 0x543c0340
646 #define IOMUXC_PAD_PDM_CLK__GPIO1_IO8 0x543c0190, 0x05, 0x0, 0x00, 0x543c0340
647 #define IOMUXC_PAD_PDM_CLK__CAN1_TX 0x543c0190, 0x06, 0x0, 0x00, 0x543c0340
648 #define IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x543c0194, 0x00, 0x543c04c4, 0x02, 0x543c0344
649 #define IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x543c0194, 0x01, 0x0, 0x00, 0x543c0344
650 #define IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x543c0194, 0x02, 0x543c0424, 0x01, 0x543c0344
651 #define IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x543c0194, 0x03, 0x0, 0x00, 0x543c0344
652 #define IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x543c0194, 0x04, 0x0, 0x00, 0x543c0344
653 #define IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x543c0194, 0x05, 0x0, 0x00, 0x543c0344
654 #define IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX 0x543c0194, 0x06, 0x543c0360, 0x01, 0x543c0344
655 #define IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x543c0198, 0x00, 0x543c04c8, 0x02, 0x543c0348
656 #define IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x543c0198, 0x02, 0x543c0438, 0x01, 0x543c0348
657 #define IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x543c0198, 0x03, 0x0, 0x00, 0x543c0348
658 #define IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x543c0198, 0x04, 0x0, 0x00, 0x543c0348
659 #define IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x543c0198, 0x05, 0x0, 0x00, 0x543c0348
660 #define IOMUXC_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x543c0198, 0x06, 0x543c0368, 0x01, 0x543c0348
661 #define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x543c019c, 0x00, 0x0, 0x00, 0x543c034c
662 #define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x543c019c, 0x01, 0x0, 0x00, 0x543c034c
663 #define IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0 0x543c019c, 0x02, 0x543c0420, 0x01, 0x543c034c
664 #define IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B 0x543c019c, 0x03, 0x0, 0x00, 0x543c034c
665 #define IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT 0x543c019c, 0x04, 0x0, 0x00, 0x543c034c
666 #define IOMUXC_PAD_SAI1_TXFS__GPIO1_IO11 0x543c019c, 0x05, 0x0, 0x00, 0x543c034c
667 #define IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK 0x543c01a0, 0x00, 0x0, 0x00, 0x543c0350
668 #define IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B 0x543c01a0, 0x01, 0x543c0460, 0x01, 0x543c0350
669 #define IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN 0x543c01a0, 0x02, 0x543c042c, 0x01, 0x543c0350
670 #define IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B 0x543c01a0, 0x03, 0x0, 0x00, 0x543c0350
671 #define IOMUXC_PAD_SAI1_TXC__CAN1_RX 0x543c01a0, 0x04, 0x543c0360, 0x02, 0x543c0350
672 #define IOMUXC_PAD_SAI1_TXC__GPIO1_IO12 0x543c01a0, 0x05, 0x0, 0x00, 0x543c0350
673 #define IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x543c01a4, 0x00, 0x0, 0x00, 0x543c0354
674 #define IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B 0x543c01a4, 0x01, 0x0, 0x00, 0x543c0354
675 #define IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK 0x543c01a4, 0x02, 0x543c0428, 0x01, 0x543c0354
676 #define IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B 0x543c01a4, 0x03, 0x0, 0x00, 0x543c0354
677 #define IOMUXC_PAD_SAI1_TXD0__CAN1_TX 0x543c01a4, 0x04, 0x0, 0x00, 0x543c0354
678 #define IOMUXC_PAD_SAI1_TXD0__GPIO1_IO13 0x543c01a4, 0x05, 0x0, 0x00, 0x543c0354
679 #define IOMUXC_PAD_SAI1_TXD0__SAI1_MCLK 0x543c01a4, 0x06, 0x543c04d4, 0x01, 0x543c0354
680 #define IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x543c01a8, 0x00, 0x0, 0x00, 0x543c0358
681 #define IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK 0x543c01a8, 0x01, 0x543c04d4, 0x02, 0x543c0358
682 #define IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT 0x543c01a8, 0x02, 0x543c0430, 0x01, 0x543c0358
683 #define IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B 0x543c01a8, 0x03, 0x0, 0x00, 0x543c0358
684 #define IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT 0x543c01a8, 0x04, 0x0, 0x00, 0x543c0358
685 #define IOMUXC_PAD_SAI1_RXD0__GPIO1_IO14 0x543c01a8, 0x05, 0x0, 0x00, 0x543c0358
686 #define IOMUXC_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x543c01ac, 0x00, 0x0, 0x00, 0x543c035c
687 #define IOMUXC_PAD_WDOG_ANY__GPIO1_IO15 0x543c01ac, 0x05, 0x0, 0x00, 0x543c035c
688 /*@}*/
689
690 #define IOMUXC_PAD_MUX_MODE_MASK (0x7U)
691 #define IOMUXC_PAD_MUX_MODE_SHIFT (0U)
692 #define IOMUXC_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_MUX_MODE_SHIFT)) & IOMUXC_PAD_MUX_MODE_MASK)
693 #define IOMUXC_PAD_SION_MASK (0x10U)
694 #define IOMUXC_PAD_SION_SHIFT (4U)
695 #define IOMUXC_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_SION_SHIFT)) & IOMUXC_PAD_SION_MASK)
696
697 #define IOMUXC_PAD_DSE_MASK (0x7EU)
698 #define IOMUXC_PAD_DSE_SHIFT (1U)
699 #define IOMUXC_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_DSE_SHIFT)) & IOMUXC_PAD_DSE_MASK)
700 #define IOMUXC_PAD_FSEL1_MASK (0x180U)
701 #define IOMUXC_PAD_FSEL1_SHIFT (7U)
702 #define IOMUXC_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_FSEL1_SHIFT)) & IOMUXC_PAD_FSEL1_MASK)
703 #define IOMUXC_PAD_PU_MASK (0x200U)
704 #define IOMUXC_PAD_PU_SHIFT (9U)
705 #define IOMUXC_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PU_SHIFT)) & IOMUXC_PAD_PU_MASK)
706 #define IOMUXC_PAD_PD_MASK (0x400U)
707 #define IOMUXC_PAD_PD_SHIFT (10U)
708 #define IOMUXC_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PD_SHIFT)) & IOMUXC_PAD_PD_MASK)
709 #define IOMUXC_PAD_OD_MASK (0x800U)
710 #define IOMUXC_PAD_OD_SHIFT (11U)
711 #define IOMUXC_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_OD_SHIFT)) & IOMUXC_PAD_OD_MASK)
712 #define IOMUXC_PAD_HYS_MASK (0x1000U)
713 #define IOMUXC_PAD_HYS_SHIFT (11U)
714 #define IOMUXC_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_HYS_SHIFT)) & IOMUXC_PAD_HYS_MASK)
715 #define IOMUXC_PAD_APC_MASK (0xFF000000U)
716 #define IOMUXC_PAD_APC_SHIFT (24U)
717 #define IOMUXC_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_APC_SHIFT)) & IOMUXC_PAD_APC_MASK)
718
719 #define SECURE_ADDR_MASK (0x10000000U)
720 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
721 #define IOMUXC_REG_ADDR(x) (x)
722 #else
723 #define IOMUXC_REG_ADDR(x) ((x) & (~SECURE_ADDR_MASK))
724 #endif
725
726 /*******************************************************************************
727 * APIs
728 ******************************************************************************/
729 #if defined(__cplusplus)
730 extern "C" {
731 #endif /*__cplusplus */
732
733 /*! @name Configuration */
734 /*@{*/
735
736 /*!
737 * @brief Sets the IOMUXC pin mux mode.
738 * @note The first five parameters can be filled with the pin function ID macros.
739 *
740 * @param muxRegister The pin mux register
741 * @param muxMode The pin mux mode
742 * @param inputRegister The select input register
743 * @param inputDaisy The input daisy
744 * @param configRegister The config register
745 * @param inputOn The software input on
746 */
IOMUXC_SetPinMux(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t inputOnfield)747 static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
748 uint32_t muxMode,
749 uint32_t inputRegister,
750 uint32_t inputDaisy,
751 uint32_t configRegister,
752 uint32_t inputOnfield)
753 {
754 if (muxRegister != 0U)
755 {
756 *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(muxRegister)) =
757 IOMUXC_PAD_MUX_MODE(muxMode) | IOMUXC_PAD_SION(inputOnfield);
758 }
759
760 if (inputRegister != 0U)
761 {
762 *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(inputRegister)) = inputDaisy;
763 }
764 }
765 /*!
766 * @brief Sets the IOMUXC pin configuration.
767 * @note The previous five parameters can be filled with the pin function ID macros.
768 *
769 * @param muxRegister The pin mux register
770 * @param muxMode The pin mux mode
771 * @param inputRegister The select input register
772 * @param inputDaisy The input daisy
773 * @param configRegister The config register
774 * @param configValue The pin config value
775 */
IOMUXC_SetPinConfig(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t configValue)776 static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
777 uint32_t muxMode,
778 uint32_t inputRegister,
779 uint32_t inputDaisy,
780 uint32_t configRegister,
781 uint32_t configValue)
782 {
783 if (configRegister != 0U)
784 {
785 *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(configRegister)) = configValue;
786 }
787 }
788 /*@}*/
789
790 #if defined(__cplusplus)
791 }
792 #endif /*__cplusplus */
793
794 /*! @}*/
795
796 #endif /* _FSL_IOMUXC_H_ */
797
