1 /*
2 ** ###################################################################
3 **     Processors:          MIMX8UD7CVP08_dsp0
4 **                          MIMX8UD7DVK08_dsp0
5 **                          MIMX8UD7DVP08_dsp0
6 **
7 **     Compiler:            Xtensa Compiler
8 **     Reference manual:    IMX8ULPRM, Rev. D, December. 2022
9 **     Version:             rev. 5.0, 2023-04-27
10 **     Build:               b230927
11 **
12 **     Abstract:
13 **         Provides a system configuration function and a global variable that
14 **         contains the system frequency. It configures the device and initializes
15 **         the oscillator (PLL) that is part of the microcontroller device.
16 **
17 **     Copyright 2016 Freescale Semiconductor, Inc.
18 **     Copyright 2016-2023 NXP
19 **     SPDX-License-Identifier: BSD-3-Clause
20 **
21 **     http:                 www.nxp.com
22 **     mail:                 support@nxp.com
23 **
24 **     Revisions:
25 **     - rev. 1.0 (2020-05-25)
26 **         Initial version.
27 **     - rev. 2.0 (2020-09-18)
28 **         Base on rev A RM
29 **     - rev. 3.0 (2021-01-20)
30 **         Base on rev A.1 RM
31 **     - rev. 4.0 (2021-07-05)
32 **         Base on rev B RM
33 **     - rev. 5.0 (2023-04-27)
34 **         Base on rev D RM
35 **
36 ** ###################################################################
37 */
38 
39 /*!
40  * @file MIMX8UD7_dsp0
41  * @version 1.0
42  * @date 270923
43  * @brief Device specific configuration file for MIMX8UD7 (implementation file)
44  *
45  * Provides a system configuration function and a global variable that contains
46  * the system frequency. It configures the device and initializes the oscillator
47  * (PLL) that is part of the microcontroller device.
48  */
49 
50 #include <stdint.h>
51 #include "fsl_device_registers.h"
52 
53 /* ----------------------------------------------------------------------------
54    -- Core clock
55    ---------------------------------------------------------------------------- */
56 
57 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
58 
59 /* ----------------------------------------------------------------------------
60    -- SystemInit()
61    ---------------------------------------------------------------------------- */
getPll0Freq(void)62 static uint32_t getPll0Freq(void)
63 {
64     uint32_t freq;
65     uint32_t mult;
66     uint8_t pll0Multi[] = {0U, 15U, 16U, 20U, 22U, 25U, 30U, 0U};
67 
68     if ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_SOURCE_MASK) != 0UL) /* If use FRO24M */
69     {
70         freq = CLK_FRO_192MHZ / 8U;
71     }
72     else /* Use System OSC. */
73     {
74         freq = CLK_XTAL_OSC_CLK;
75     }
76 
77     mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT);
78     freq *= pll0Multi[mult]; /* Multiplier. */
79 
80 
81     return freq;
82 }
83 
SystemInit(void)84 void SystemInit(void)
85 {
86     SystemInitHook();
87 }
88 
89 /* ----------------------------------------------------------------------------
90    -- SystemCoreClockUpdate()
91    ---------------------------------------------------------------------------- */
92 
SystemCoreClockUpdate(void)93 void SystemCoreClockUpdate(void)
94 {
95     uint32_t fracValue;
96     uint32_t CGCOUTClock;
97     /* Identify current system clock source. */
98     switch (CGC_RTD->FUSIONCLK & CGC_FUSIONCLK_SCS_MASK)
99     {
100         case CGC_FUSIONCLK_SCS(0):
101             /* FRO clock */
102             CGCOUTClock = CLK_FRO_192MHZ;
103             break;
104         case CGC_FUSIONCLK_SCS(1):
105             /* PLL0 PFD0 */
106             CGCOUTClock = getPll0Freq();
107             fracValue   = (CGC_RTD->PLL0PFDCFG & CGC_PLL0PFDCFG_PFD0_MASK) >> CGC_PLL0PFDCFG_PFD0_SHIFT;
108             CGCOUTClock = (uint32_t)(((uint64_t)CGCOUTClock * 18U) / fracValue);
109             break;
110         case CGC_FUSIONCLK_SCS(2):
111             /* PLL0 PFD1 */
112             CGCOUTClock = getPll0Freq();
113             fracValue   = (CGC_RTD->PLL0PFDCFG & CGC_PLL0PFDCFG_PFD1_MASK) >> CGC_PLL0PFDCFG_PFD1_SHIFT;
114             CGCOUTClock = (uint32_t)(((uint64_t)CGCOUTClock * 18U) / fracValue);
115             break;
116         case CGC_FUSIONCLK_SCS(3):
117             /* SOSC */
118             CGCOUTClock = CLK_XTAL_OSC_CLK;
119             break;
120         case CGC_FUSIONCLK_SCS(4):
121             /* RTC32K */
122             CGCOUTClock = CLK_RTC_32K_CLK;
123             break;
124         case CGC_FUSIONCLK_SCS(5):
125             /* LVDS */
126             CGCOUTClock = CLK_LVDS_CLK;
127             break;
128         case CGC_FUSIONCLK_SCS(6):
129             /* PLL0 */
130             CGCOUTClock = getPll0Freq();
131             break;
132         default:
133             CGCOUTClock = 0U;
134             break;
135     }
136     /* Divide the CGC output clock to get the Fusion Core clock. */
137     CGCOUTClock /= ((CGC_RTD->FUSIONCLK & CGC_FUSIONCLK_DIVCORE_MASK) >> CGC_FUSIONCLK_DIVCORE_SHIFT) + 1U;
138     /* Update System Core Clock. */
139     SystemCoreClock = CGCOUTClock;
140 }
141 
142 /* ----------------------------------------------------------------------------
143    -- SystemInitHook()
144    ---------------------------------------------------------------------------- */
145 
SystemInitHook(void)146 __attribute__((weak)) void SystemInitHook(void)
147 {
148     /* Void implementation of the weak function. */
149 }
150